JP2004200532A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
JP2004200532A
JP2004200532A JP2002369215A JP2002369215A JP2004200532A JP 2004200532 A JP2004200532 A JP 2004200532A JP 2002369215 A JP2002369215 A JP 2002369215A JP 2002369215 A JP2002369215 A JP 2002369215A JP 2004200532 A JP2004200532 A JP 2004200532A
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Prior art keywords
semiconductor chip
semiconductor
chip
semiconductor device
sealing
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Japanese (ja)
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Kenji Amano
賢治 天野
Atsushi Fujisawa
敦 藤澤
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Renesas Technology Corp
Renesas Semiconductor Package and Test Solutions Co Ltd
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Renesas Technology Corp
Renesas Northern Japan Semiconductor Inc
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Priority to JP2002369215A priority Critical patent/JP2004200532A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of enhancing reflow resistance properties, and to provide a manufacturing method thereof. <P>SOLUTION: There are provided a semiconductor chip 2, a tub mounted on the semiconductor chip 2, a plurality of inner leads disposed surrounding the semiconductor chip 2, a wire for connecting a bonding pad 2a of the semiconductor chip 2 with the inner leads, a sealer for sealing the semiconductor chip 2, a plurality of the wires and the plurality of inner leads with a resin, and a plurality of outer leads, which are integrally linked with each of the inner leads and project externally of the sealer. A recess 2e is formed at an end of a passivation film 2d of the semiconductor chip 2, and the recess 2e is brought into contact with the sealer, whereby the adhesive properties of the sealer to the end of the passivation film 2d can be enhanced, and the occurrence of a separation at an interface between the passivation film 2d and a sealing resin at the end of a main surface of the chip can be prevented, thereby enhancing the reflow resistance properties of the semiconductor device. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体製造技術に関し、特に、タブを有する樹脂封止型の半導体装置の耐リフロー性向上に適用して有効な技術に関する。
【０００２】
【従来の技術】
従来、樹脂封止型のパッケージ（半導体装置）では、各構成材料がそれぞれ異なった熱膨張係数を持つため、リフローなどの加熱が行われると熱応力が発生する。すなわち、異なった熱膨張係数を持つ半導体チップ、リードフレームおよびパッケージ材の各構成材料が互いに貼り合わされているため、各構成材料が拘束され、伸縮が自由に行えないことにより熱応力が発生する（例えば、非特許文献１参照）。
【０００３】
【非特許文献１】
香山晋、成瀬邦彦（監修）「実践講座ＶＬＳＩパッケージング技術（上）」日経ＢＰ社出版、１９９３年５月３１日（２０６〜２０７頁）
【０００４】
【発明が解決しようとする課題】
樹脂封止型の半導体装置では、リフロー時の加熱によってタブや半導体チップの端部に熱応力が集中する。特に、タブを有する半導体装置では、タブの裏面側とチップ上とで封止体の容積に差がある（レジンバランスが悪い）と、封止体に反りが形成され、その結果、半導体チップの主面の端部に熱応力が集中する。さらに前記熱応力は、図１０の比較例のＳＯＰ１０のＰ部に示すように、主にチップ端部の角部に集中する。
【０００５】
その際、半導体チップ２の主面２ｂに、表面保護膜として封止用樹脂と密着性が弱いパッシベーション膜（例えば、タングステン膜など）２ｄ（図２参照）が形成されていると、半導体チップ２の端部の角部に熱応力が集中した際に、図１０に示すＱ部のように半導体チップ２の端部においてパッシベーション膜２ｄとレジンとの界面で剥離が発生することが問題となる。
【０００６】
その結果、半導体装置の耐リフロー性が低下するという問題が起こる。
【０００７】
本発明の目的は、耐リフロー性の向上を図る半導体装置およびその製造方法を提供することにある。
【０００８】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。
【０００９】
【課題を解決するための手段】
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。
【００１０】
本発明は、半導体集積回路が形成された半導体チップと、半導体チップを樹脂封止する封止体と、半導体チップが搭載されたチップ搭載部とを有しており、半導体チップの主面上に形成された表面保護膜の端部に段差部が形成され、封止体と表面保護膜の段差部とが接触しているものである。
【００１１】
また、本発明は、主面上の表面保護膜の端部に段差部が形成された半導体チップを準備する工程と、半導体チップをチップ搭載部に搭載する工程と、半導体チップを樹脂封止して封止体を形成する工程とを有しており、樹脂封止の際に半導体チップの表面保護膜の段差部と、封止体とが接触するように樹脂封止するものである。
【００１２】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。
【００１３】
図１は本発明の実施の形態の半導体装置の構造の一例を示す断面図、図２は図１に示す半導体装置に組み込まれる半導体チップの構造の一例を示す平面図とその角部の拡大部分平面図、図３は図２に示す半導体チップの表面保護膜の段差部の構造を示す拡大部分断面図、図４は図３に示す段差部の形成方法における表面保護膜の形成状態の一例を示す部分断面図、図５は図３に示す段差部の形成方法における表面保護膜のエッチング状態の一例を示す部分断面図、図６は図３に示す段差部の形成方法における表面保護膜の再形成状態の一例を示す部分断面図、図７および図８はそれぞれ本発明の実施の形態の半導体装置に組み込まれる変形例の半導体チップの構造を示す平面図とその角部の拡大部分平面図、図９は本発明の実施の形態の変形例の半導体装置の構造を示す断面図、図１０は比較例の半導体装置におけるリフロー時のチップ／レジン界面剥離の発生状態を示す断面図である。
【００１４】
図１に示す本実施の形態の半導体装置は、樹脂封止型の半導体パッケージであり、本実施の形態では、前記半導体装置の一例として、チップ搭載部である板状のタブ１ｃを有し、このタブ１ｃ上に半導体チップ２が搭載されたＳＯＰ（Small Outline Package)５を取り上げて説明する。
【００１５】
ＳＯＰ５の構成について説明すると、半導体集積回路が形成された半導体チップ２と、半導体チップ２が搭載された板状のタブ１ｃと、半導体チップ２の周囲に配置された複数の板状のインナリード（リード）１ａと、図２に示す半導体チップ２のボンディング用のパッド２ａとこれに対応するインナリード１ａとを電気的に接続するワイヤ４と、半導体チップ２や複数のワイヤ４およびインナリード１ａを樹脂封止する封止体３と、インナリード１ａそれぞれと一体で繋がり、かつ封止体３から外部に突出する複数のアウタリード１ｂとから成る。
【００１６】
また、本実施の形態のＳＯＰ５に組み込まれた半導体チップ２は、封止用樹脂（レジン）と密着性が比較的弱い表面保護膜であるパッシベーション膜（例えば、タングステン膜など）２ｄが形成されているものであり、半導体チップ２の主面２ｂの端部付近、そのうちでも特に角部でパッシベーション膜２ｄと封止体３との剥離が起こり易い。
【００１７】
そこで、ＳＯＰ５の半導体チップ２には、図２および図３に示すように、その主面２ｂ上に形成された表面保護膜であるパッシベーション膜２ｄの端部全周に亘って凹部（段差部）２ｅが形成されている。本実施の形態では、半導体チップ２の主面２ｂのパッシベーション膜２ｄにおいてパッド列とエッジとの間の領域に、２本の枠状の窪みの段差部である凹部２ｅが並んで形成されている。
【００１８】
この凹部２ｅが形成されていることにより、封止体３のレジンが凹部２ｅ内に入り込んで封止体３とパッシベーション膜２ｄの凹部２ｅとが確実に接触し、これにより、封止体３とパッシベーション膜２ｄの端部との接触面積が増加するとともに、封止体３とパッシベーション膜２ｄの端部との食い付き力も向上するため、両者の密着性を向上させることができる。
【００１９】
したがって、半導体チップ２の主面２ｂの端部におけるパッシベーション膜２ｄと封止用樹脂の界面での剥離の発生を防止することができる。すなわち、図１０の比較例のＳＯＰ１０に示すように、チップ角部Ｐに剥離部Ｑが形成されることを防止できる。
【００２０】
その結果、ＳＯＰ５の耐リフロー性の向上を図ることができる。さらに、ＳＯＰ５の信頼性の向上を図ることができる。
【００２１】
なお、インナリード１ａ、アウタリード１ｂおよびタブ１ｃは、例えば、銅合金や鉄−ニッケル合金などから成る金属の薄板状のものであり、また、ワイヤ４は、例えば、金線などである。さらに、封止体３は、例えば、エポキシ系の熱硬化性樹脂などから形成されたものである。
【００２２】
また、半導体チップ２は、例えば、銀ペーストなどのダイボンド材７を介してタブ１ｃのチップ搭載面１ｄ上に固定されている。すなわち、半導体チップ２の裏面２ｃとタブ１ｃのチップ搭載面１ｄとがダイボンド材７を介して固定されている。
【００２３】
次に、図４〜図６を用いてパッシベーション膜２ｄへの凹部２ｅの形成方法について説明する。
【００２４】
なお、パッシベーション膜２ｄは、半導体ウェハ６の状態で形成する。
【００２５】
まず、素子やパッド２ａなどが形成された半導体ウェハ６の表面保護膜として、図４に示すパッシベーション膜２ｄを形成する。
【００２６】
続いて、凹部２ｅ形成箇所やパッド２ａ上に堆積されたパッシベーション膜２ｄを露光し、さらに、露光後、エッチングして図５に示すように、段差部形成箇所のパッシベーション膜２ｄを取り除く。
【００２７】
その後、図６に示すようにパッシベーション膜２ｄを再塗布して凹部２ｅを形成する。
【００２８】
凹部２ｅ形成完了後、ダイシングを行って個片チップ化する。
【００２９】
次に、本実施の形態のＳＯＰ５の製造方法について説明する。
【００３０】
まず、主面２ｂ上のパッシベーション膜２ｄの端部に段差部である凹部２ｅが形成された図２に示すような半導体チップ２を準備する。
【００３１】
その後、リードフレーム（図示せず）のチップ搭載部であるタブ１ｃにダイボンド材７を介して半導体チップ２を固定する。
【００３２】
続いて、ワイヤボンディングを行って半導体チップ２のパッド２ａとこれに対応するインナリード１ａとを電気的に接続する。
【００３３】
その後、樹脂モールディングを行って、半導体チップ２、複数のワイヤ４およびインナリード１ａを樹脂封止して封止体３を形成する。
【００３４】
その際、封止用樹脂が半導体チップ２のパッシベーション膜２ｄの凹部２ｅに入り込むため、パッシベーション膜２ｄの凹部２ｅと封止体３とを確実に接触させることができる。
【００３５】
その結果、封止体３とパッシベーション膜２ｄの端部との接触面積が増加するとともに、封止体３とパッシベーション膜２ｄの端部との食い付き力も向上するため、両者の密着性を向上させることができる。
【００３６】
これによって、半導体チップ２の主面２ｂの端部におけるパッシベーション膜２ｄと封止体３の剥離の発生を防ぐことができ、ＳＯＰ５の耐リフロー性および信頼性の向上を図ることができる。
【００３７】
樹脂モールディング終了後、リードの切断・成形を行って、各パッケージに個片化するとともに、アウタリード１ｂをガルウィング状に曲げ成形して図１に示すＳＯＰ５の組み立て完了となる。
【００３８】
次に、本実施の形態の変形例について説明する。
【００３９】
図７に示す変形例は、半導体チップ２の外周全周に亘って形成された凹部２ｅにおいて、角部の凹部２ｅを中央寄り端部より高密に形成したものである。すなわち、応力の集中し易い角部の凹部２ｅの密度を中央寄り端部より高くしたものであり、これにより、角部付近のパッシベーション膜２ｄと封止体３の密着性をさらに高めることができる。
【００４０】
その結果、ＳＯＰ５の耐リフロー性や信頼性をさらに向上させることができる。
【００４１】
また、図８に示す変形例は、凹部２ｅの形状を枠状ではなく、ディンプル状としたものである。その際、図７に示す変形例と同様に、ディンプル状の凹部２ｅの密度を中央寄り端部より角部の方を高密に形成したものであり、これにより、応力の集中し易い角部の凹部２ｅの密度を中央寄り端部より高くしたものであり、その結果、図７に示す変形例と同様に、応力の集中し易い角部でのレジン剥離を防ぐことができ、ＳＯＰ５の耐リフロー性や信頼性をさらに向上させることができる。
【００４２】
また、図９に示す変形例は、タブ１ｃが半導体チップ２の主面２ｂより小さな面積のチップ搭載面１ｄを有しており、半導体チップ２が、その端部がチップ搭載面１ｄから迫り出してチップ搭載面１ｄに搭載されている構造のものであり、いわゆる小タブ構造のＳＯＰ５である。
【００４３】
小タブ構造では、半導体チップ２の端部全周がタブ１ｃより突出しており、リフロー時などに熱応力がかかると、半導体チップ２の端部に付与される熱応力も一層大きく、かつ角部に集中する応力も一層大きくなる。したがって、小タブ構造では半導体チップ２の主面２ｂの角部付近でのレジン／パッシベーション膜２ｄの剥離も一層起こり易いが、図９に示す小タブ構造のＳＯＰ５において、図２、図７または図８に示すようなパッシベーション膜２ｄの端部に凹部２ｅが形成された半導体チップ２を搭載することにより、半導体チップ２の端部でのレジンとの剥離の発生を防ぐことができ、小タブ構造のＳＯＰ５の耐リフロー性や信頼性を向上させることができる。
【００４４】
以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。
【００４５】
例えば、前記実施の形態では、半導体チップ２の表面保護膜であるパッシベーション膜２ｄの端部に形成される段差部が凹部２ｅの場合について説明したが、前記段差部は、凸部であってもよい。すなわち、端部におけるパッシベーション膜２ｄと封止体３との接触面積を増やすことが可能な形状であればよい。
【００４６】
さらに、段差部は、端部の全周に亘って形成されていなくてもよく、端部において角部を含んで断続的に並んだ状態などで形成されていてもよい。
【００４７】
また、段差部が形成される表面保護膜（パッシベーション膜２ｄ）としては、封止用樹脂との密着性が弱い材質のものであれば、金属材であっても、樹脂材であってもよい。
【００４８】
また、前記実施の形態では、半導体装置の一例として、ＳＯＰ５を取り上げて説明したが、前記半導体装置は、ＳＯＰ５に限定されるものではなく、樹脂封止型で、かつ表面保護膜の端部に段差部が形成された半導体チップ２を有するものであれば、ＱＦＰ（Quad Flat Package)、ＱＦＮ（Quad Flat Non-leaded Package) 、ＢＧＡ（Ball Grid Array)、ＰＧＡ（Pin Grid Array) またはＬＧＡ（Land Grid Array)などの他の半導体装置であってもよい。
【００４９】
【発明の効果】
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。
【００５０】
半導体チップの表面保護膜の端部に段差部が形成され、この段差部と封止体とが接触していることにより、封止体と表面保護膜の端部との密着性を向上させることができる。これにより、チップ主面の端部における表面保護膜と封止用樹脂の界面での剥離の発生を防止することができ、その結果、半導体装置の耐リフロー性の向上を図ることができる。
【図面の簡単な説明】
【図１】本発明の実施の形態の半導体装置の構造の一例を示す断面図である。
【図２】図１に示す半導体装置に組み込まれる半導体チップの構造の一例を示す平面図とその角部の拡大部分平面図である。
【図３】図２に示す半導体チップの表面保護膜の段差部の構造を示す拡大部分断面図である。
【図４】図３に示す段差部の形成方法における表面保護膜の形成状態の一例を示す部分断面図である。
【図５】図３に示す段差部の形成方法における表面保護膜のエッチング状態の一例を示す部分断面図である。
【図６】図３に示す段差部の形成方法における表面保護膜の再形成状態の一例を示す部分断面図である。
【図７】本発明の実施の形態の半導体装置に組み込まれる変形例の半導体チップの構造を示す平面図とその角部の拡大部分平面図である。
【図８】本発明の実施の形態の半導体装置に組み込まれる変形例の半導体チップの構造を示す平面図とその角部の拡大部分平面図である。
【図９】本発明の実施の形態の変形例の半導体装置の構造を示す断面図である。
【図１０】比較例の半導体装置におけるリフロー時のチップ／レジン界面剥離の発生状態を示す断面図である。
【符号の説明】
１ａ インナリード
１ｂ アウタリード
１ｃ タブ（チップ搭載部）
１ｄ チップ搭載面
２ 半導体チップ
２ａ パッド
２ｂ 主面
２ｃ 裏面
２ｄ パッシベーション膜（表面保護膜）
２ｅ 凹部（段差部）
３ 封止体
４ ワイヤ
５ ＳＯＰ（半導体装置）
６ 半導体ウェハ
７ ダイボンド材
１０ ＳＯＰ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique effective when applied to an improvement in reflow resistance of a resin-sealed semiconductor device having a tab.
[0002]
[Prior art]
Conventionally, in a resin-encapsulated package (semiconductor device), each constituent material has a different coefficient of thermal expansion, so that heating such as reflow generates thermal stress. That is, since the constituent materials of the semiconductor chip, the lead frame, and the package material having different coefficients of thermal expansion are bonded to each other, the constituent materials are restrained, and expansion and contraction cannot be performed freely, thereby generating thermal stress ( For example, see Non-Patent Document 1).
[0003]
[Non-patent document 1]
Susumu Kayama and Kunihiko Naruse (supervised) "Practical Course VLSI Packaging Technology (1)", published by Nikkei BP, May 31, 1993 (pages 206 to 207)
[0004]
[Problems to be solved by the invention]
In a resin-encapsulated semiconductor device, thermal stress concentrates on a tab or an end of a semiconductor chip due to heating during reflow. In particular, in a semiconductor device having a tab, if there is a difference in the volume of the sealing body between the back surface side of the tab and the chip (poor resin balance), the sealing body is warped, and as a result, the semiconductor chip Thermal stress concentrates on the end of the main surface. Further, the thermal stress is mainly concentrated on the corners of the chip end as shown in the P section of the SOP 10 of the comparative example in FIG.
[0005]
At this time, if a passivation film (for example, a tungsten film or the like) 2d (see FIG. 2) having low adhesion to the sealing resin is formed on the main surface 2b of the semiconductor chip 2 as a surface protection film, the semiconductor chip 2 When thermal stress is concentrated on the corners of the edge of the semiconductor chip 2, peeling occurs at the interface between the passivation film 2d and the resin at the edge of the semiconductor chip 2 as shown by the portion Q in FIG.
[0006]
As a result, there arises a problem that the reflow resistance of the semiconductor device is reduced.
[0007]
An object of the present invention is to provide a semiconductor device for improving reflow resistance and a method for manufacturing the same.
[0008]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0010]
The present invention includes a semiconductor chip on which a semiconductor integrated circuit is formed, a sealing body for resin-sealing the semiconductor chip, and a chip mounting portion on which the semiconductor chip is mounted, and a semiconductor chip mounted on a main surface of the semiconductor chip. A step is formed at an end of the formed surface protection film, and the sealing body and the step of the surface protection film are in contact with each other.
[0011]
Further, the present invention provides a step of preparing a semiconductor chip having a step portion formed at an end of a surface protective film on a main surface, a step of mounting the semiconductor chip on a chip mounting section, and a step of resin-sealing the semiconductor chip. And forming a sealing body by resin sealing. The resin sealing is performed so that the stepped portion of the surface protection film of the semiconductor chip and the sealing body come into contact with each other during the resin sealing.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0013]
FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view showing an example of the structure of a semiconductor chip incorporated in the semiconductor device shown in FIG. FIG. 3 is an enlarged partial sectional view showing the structure of the step portion of the surface protection film of the semiconductor chip shown in FIG. 2, and FIG. 4 is an example of the state of formation of the surface protection film in the method of forming the step portion shown in FIG. 5 is a partial sectional view showing an example of an etching state of the surface protection film in the method of forming the step shown in FIG. 3, and FIG. 6 is a sectional view of the surface protection film in the method of forming the step shown in FIG. FIGS. 7 and 8 are a plan view and an enlarged partial plan view of a corner portion of a semiconductor chip according to a modified example incorporated in the semiconductor device according to the embodiment of the present invention. FIG. 9 shows a modification of the embodiment of the present invention. Sectional view showing a structure of a semiconductor device, FIG. 10 is a sectional view showing a state of generation of the chip / resin interfacial separation during reflow of the semiconductor device of the comparative example.
[0014]
The semiconductor device of the present embodiment shown in FIG. 1 is a resin-encapsulated semiconductor package. In the present embodiment, as an example of the semiconductor device, the semiconductor device has a plate-like tab 1c as a chip mounting portion, An SOP (Small Outline Package) 5 in which the semiconductor chip 2 is mounted on the tab 1c will be described.
[0015]
The configuration of the SOP 5 will be described. The semiconductor chip 2 on which the semiconductor integrated circuit is formed, the tab-like tab 1c on which the semiconductor chip 2 is mounted, and the plurality of plate-like inner leads ( Leads 1a, wires 4 for electrically connecting the bonding pads 2a of the semiconductor chip 2 shown in FIG. 2 and the corresponding inner leads 1a, and the semiconductor chip 2, a plurality of wires 4 and the inner leads 1a. It comprises a sealing body 3 to be resin-sealed, and a plurality of outer leads 1b integrally connected to the inner leads 1a and protruding from the sealing body 3 to the outside.
[0016]
The semiconductor chip 2 incorporated in the SOP 5 of the present embodiment has a passivation film (for example, a tungsten film or the like) 2d which is a surface protection film having relatively weak adhesion to the sealing resin (resin). The passivation film 2d and the sealing body 3 are likely to be separated from each other in the vicinity of the end of the main surface 2b of the semiconductor chip 2, particularly at the corners.
[0017]
Therefore, as shown in FIGS. 2 and 3, the semiconductor chip 2 of the SOP 5 has a concave portion (step portion) over the entire periphery of the end portion of the passivation film 2d which is a surface protection film formed on the main surface 2b. 2e is formed. In the present embodiment, in the passivation film 2d of the main surface 2b of the semiconductor chip 2, concave portions 2e, which are step portions of two frame-shaped depressions, are formed side by side in a region between the pad row and the edge. .
[0018]
Due to the formation of the concave portion 2e, the resin of the sealing body 3 enters the concave portion 2e, and the sealing body 3 and the concave portion 2e of the passivation film 2d surely come into contact with each other. Since the contact area between the end portion of the passivation film 2d and the sealing body 3 and the end portion of the passivation film 2d are improved, the adhesion between the two can be improved.
[0019]
Therefore, it is possible to prevent separation at the interface between the passivation film 2d and the sealing resin at the end of the main surface 2b of the semiconductor chip 2. That is, as shown in the SOP 10 of the comparative example of FIG. 10, the formation of the peeling portion Q at the corner P of the chip can be prevented.
[0020]
As a result, the reflow resistance of the SOP 5 can be improved. Further, the reliability of the SOP 5 can be improved.
[0021]
The inner lead 1a, the outer lead 1b, and the tab 1c are, for example, metal thin plates made of a copper alloy or an iron-nickel alloy, and the wire 4 is, for example, a gold wire. Furthermore, the sealing body 3 is formed from, for example, an epoxy-based thermosetting resin.
[0022]
Further, the semiconductor chip 2 is fixed on the chip mounting surface 1d of the tab 1c via a die bonding material 7 such as a silver paste. That is, the back surface 2 c of the semiconductor chip 2 and the chip mounting surface 1 d of the tab 1 c are fixed via the die bonding material 7.
[0023]
Next, a method of forming the recess 2e in the passivation film 2d will be described with reference to FIGS.
[0024]
Note that the passivation film 2d is formed in the state of the semiconductor wafer 6.
[0025]
First, a passivation film 2d shown in FIG. 4 is formed as a surface protection film of the semiconductor wafer 6 on which elements, pads 2a, etc. are formed.
[0026]
Subsequently, the passivation film 2d deposited on the concave portion 2e formation location and the pad 2a is exposed, and after the exposure, etching is performed to remove the passivation film 2d at the step formation location as shown in FIG.
[0027]
After that, as shown in FIG. 6, the passivation film 2d is applied again to form the concave portion 2e.
[0028]
After the formation of the concave portions 2e, dicing is performed to make individual chips.
[0029]
Next, a method of manufacturing the SOP 5 according to the present embodiment will be described.
[0030]
First, a semiconductor chip 2 as shown in FIG. 2 in which a recess 2e as a step is formed at an end of a passivation film 2d on a main surface 2b is prepared.
[0031]
After that, the semiconductor chip 2 is fixed via a die bonding material 7 to a tab 1c which is a chip mounting portion of a lead frame (not shown).
[0032]
Subsequently, the pad 2a of the semiconductor chip 2 is electrically connected to the corresponding inner lead 1a by performing wire bonding.
[0033]
After that, resin molding is performed, and the semiconductor chip 2, the plurality of wires 4, and the inner leads 1a are resin-sealed to form a sealing body 3.
[0034]
At this time, since the sealing resin enters the concave portion 2e of the passivation film 2d of the semiconductor chip 2, the concave portion 2e of the passivation film 2d and the sealing body 3 can be reliably contacted.
[0035]
As a result, the contact area between the sealing body 3 and the end of the passivation film 2d is increased, and the biting force between the sealing body 3 and the end of the passivation film 2d is also improved. be able to.
[0036]
This can prevent the passivation film 2d and the sealing body 3 from peeling off at the end of the main surface 2b of the semiconductor chip 2 and improve the reflow resistance and reliability of the SOP 5.
[0037]
After the resin molding is completed, the leads are cut and formed into individual packages, and the outer leads 1b are bent and formed into a gull wing shape to complete the assembly of the SOP 5 shown in FIG.
[0038]
Next, a modified example of the present embodiment will be described.
[0039]
In the modified example shown in FIG. 7, in the concave portion 2 e formed over the entire outer periphery of the semiconductor chip 2, the concave portion 2 e at the corner is formed more densely than the end near the center. In other words, the density of the concave portions 2e at the corners where stress tends to concentrate is higher than that at the end near the center, whereby the adhesion between the passivation film 2d near the corners and the sealing body 3 can be further increased. .
[0040]
As a result, the reflow resistance and reliability of the SOP 5 can be further improved.
[0041]
In the modification shown in FIG. 8, the shape of the recess 2e is not a frame but a dimple. At this time, similarly to the modification shown in FIG. 7, the density of the dimple-shaped concave portion 2e is formed to be higher at the corners than at the end near the center, and thereby the corners at which stress is likely to concentrate are formed. The densities of the recesses 2e are higher than the ends near the center. As a result, similarly to the modification shown in FIG. 7, resin peeling at corners where stress tends to concentrate can be prevented, and the reflow resistance of the SOP5 can be prevented. Performance and reliability can be further improved.
[0042]
In the modification shown in FIG. 9, the tab 1c has a chip mounting surface 1d having an area smaller than the main surface 2b of the semiconductor chip 2, and the end of the semiconductor chip 2 protrudes from the chip mounting surface 1d. The SOP 5 has a structure mounted on the chip mounting surface 1d and has a so-called small tab structure.
[0043]
In the small tab structure, the entire periphery of the end of the semiconductor chip 2 protrudes from the tab 1c, and when a thermal stress is applied at the time of reflow or the like, the thermal stress applied to the end of the semiconductor chip 2 is further increased, and the corner is formed. The stress concentrated on the surface is further increased. Therefore, in the small tab structure, the resin / passivation film 2d is more likely to be peeled off near the corner of the main surface 2b of the semiconductor chip 2, but in the SOP 5 having the small tab structure shown in FIG. 9, FIGS. By mounting the semiconductor chip 2 in which the concave portion 2e is formed at the end of the passivation film 2d as shown in FIG. 8, it is possible to prevent the separation from the resin at the end of the semiconductor chip 2 and to achieve the small tab structure. Can improve the reflow resistance and reliability of the SOP5.
[0044]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment of the invention, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.
[0045]
For example, in the above-described embodiment, the case where the step formed at the end of the passivation film 2d as the surface protection film of the semiconductor chip 2 is the recess 2e has been described, but the step may be a protrusion. Good. That is, any shape may be used as long as the contact area between the passivation film 2d and the sealing body 3 at the end can be increased.
[0046]
Further, the step portion may not be formed over the entire circumference of the end portion, and may be formed in a state where the end portion is intermittently arranged including the corner portion.
[0047]
The surface protection film (passivation film 2d) on which the step is formed may be a metal material or a resin material as long as the material has low adhesion to the sealing resin. .
[0048]
Further, in the above-described embodiment, the SOP5 is described as an example of the semiconductor device. However, the semiconductor device is not limited to the SOP5, but is a resin-sealed type and is provided at an end of the surface protective film. As long as the semiconductor chip 2 has a stepped portion, a quad flat package (QFP), a quad flat non-leaded package (QFN), a ball grid array (BGA), a pin grid array (PGA), or a land grid (LGA) Other semiconductor devices such as a Grid Array) may be used.
[0049]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0050]
A step is formed at the end of the surface protection film of the semiconductor chip, and the step is in contact with the sealing body, thereby improving the adhesion between the sealing body and the end of the surface protection film. Can be. Accordingly, it is possible to prevent peeling at the interface between the surface protective film and the sealing resin at the end of the chip main surface, and as a result, it is possible to improve the reflow resistance of the semiconductor device.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating an example of a structure of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a plan view showing an example of the structure of a semiconductor chip incorporated in the semiconductor device shown in FIG. 1 and an enlarged partial plan view of a corner thereof.
FIG. 3 is an enlarged partial cross-sectional view showing a structure of a step portion of a surface protection film of the semiconductor chip shown in FIG. 2;
FIG. 4 is a partial cross-sectional view showing an example of a state of forming a surface protective film in the method of forming a step shown in FIG. 3;
FIG. 5 is a partial cross-sectional view showing an example of an etching state of a surface protective film in the method of forming a step shown in FIG. 3;
6 is a partial cross-sectional view showing an example of a state in which a surface protective film is formed again in the method of forming a step shown in FIG. 3;
FIG. 7 is a plan view showing a structure of a semiconductor chip of a modified example incorporated in the semiconductor device of the embodiment of the present invention, and an enlarged partial plan view of a corner thereof.
FIG. 8 is a plan view showing a structure of a semiconductor chip of a modified example incorporated in the semiconductor device of the embodiment of the present invention, and an enlarged partial plan view of a corner thereof.
FIG. 9 is a cross-sectional view illustrating a structure of a semiconductor device according to a modification of the embodiment of the present invention.
FIG. 10 is a cross-sectional view illustrating a state in which chip / resin interface separation occurs during reflow in a semiconductor device of a comparative example.
[Explanation of symbols]
1a Inner lead 1b Outer lead 1c Tab (chip mounting part)
1d Chip mounting surface 2 Semiconductor chip 2a Pad 2b Main surface 2c Back surface 2d Passivation film (surface protection film)
2e recess (step)
3 sealing body 4 wire 5 SOP (semiconductor device)
6 semiconductor wafer 7 die bonding material 10 SOP

Claims (5)

半導体集積回路が形成された半導体チップと、
前記半導体チップを樹脂封止する封止体と、
前記半導体チップが搭載されたチップ搭載部とを有する半導体装置であって、
前記半導体チップの主面上に形成された表面保護膜の端部に段差部が形成され、前記封止体と前記表面保護膜の前記段差部とが接触していることを特徴とする半導体装置。A semiconductor chip on which a semiconductor integrated circuit is formed;
A sealing body for resin-sealing the semiconductor chip,
A semiconductor device having a chip mounting portion on which the semiconductor chip is mounted,
A semiconductor device, wherein a step is formed at an end of a surface protection film formed on a main surface of the semiconductor chip, and the sealing body and the step of the surface protection film are in contact with each other. . 半導体集積回路が形成された半導体チップと、
前記半導体チップを樹脂封止する封止体と、
前記半導体チップが搭載されたチップ搭載部とを有する半導体装置であって、
前記半導体チップの主面上に形成された表面保護膜の端部の全周に亘って段差部が形成され、前記全周に亘って形成された前記段差部において角部端部の方が中央寄り端部より前記段差部が高密に形成され、前記封止体と前記表面保護膜の前記段差部とが接触していることを特徴とする半導体装置。A semiconductor chip on which a semiconductor integrated circuit is formed;
A sealing body for resin-sealing the semiconductor chip,
A semiconductor device having a chip mounting portion on which the semiconductor chip is mounted,
A step portion is formed over the entire periphery of the end portion of the surface protective film formed on the main surface of the semiconductor chip, and the corner end portion of the step portion formed over the entire periphery is closer to the center. A semiconductor device, wherein the step portion is formed densely from a near end portion, and the sealing member is in contact with the step portion of the surface protective film. 半導体集積回路が形成された半導体チップと、
前記半導体チップを樹脂封止する封止体と、
前記半導体チップが搭載された板状のチップ搭載部であるタブと、
前記半導体チップの周囲に配置された複数の板状のリードとを有する半導体装置であって、
前記半導体チップの主面上に形成された表面保護膜の端部に段差部が形成され、前記封止体と前記表面保護膜の前記段差部とが接触していることを特徴とする半導体装置。A semiconductor chip on which a semiconductor integrated circuit is formed;
A sealing body for resin-sealing the semiconductor chip,
A tab which is a plate-shaped chip mounting portion on which the semiconductor chip is mounted,
A semiconductor device having a plurality of plate-shaped leads arranged around the semiconductor chip,
A semiconductor device, wherein a step is formed at an end of a surface protection film formed on a main surface of the semiconductor chip, and the sealing body and the step of the surface protection film are in contact with each other. . 半導体集積回路が形成された半導体チップと、
前記半導体チップを樹脂封止する封止体と、
前記半導体チップの主面より小さな面積のチップ搭載面を有し、前記半導体チップが、その端部が前記チップ搭載面から迫り出して前記チップ搭載面に搭載された板状のチップ搭載部であるタブと、
前記半導体チップの周囲に配置された複数の板状のリードとを有する半導体装置であって、
前記半導体チップの主面上に形成された表面保護膜の端部に段差部が形成され、前記封止体と前記表面保護膜の前記段差部とが接触していることを特徴とする半導体装置。A semiconductor chip on which a semiconductor integrated circuit is formed;
A sealing body for resin-sealing the semiconductor chip,
The semiconductor chip has a chip mounting surface having an area smaller than a main surface of the semiconductor chip, and the semiconductor chip is a plate-shaped chip mounting portion whose end portion protrudes from the chip mounting surface and is mounted on the chip mounting surface. Tabs,
A semiconductor device having a plurality of plate-shaped leads arranged around the semiconductor chip,
A semiconductor device, wherein a step is formed at an end of a surface protection film formed on a main surface of the semiconductor chip, and the sealing body and the step of the surface protection film are in contact with each other. . 主面上の表面保護膜の端部に段差部が形成された半導体チップを準備する工程と、
前記半導体チップをチップ搭載部に搭載する工程と、
前記半導体チップを樹脂封止して封止体を形成する工程とを有する半導体装置の製造方法であって、
前記樹脂封止の際に前記半導体チップの前記表面保護膜の前記段差部と、前記封止体とが接触するように樹脂封止することを特徴とする半導体装置の製造方法。A step of preparing a semiconductor chip having a step formed at an end of the surface protective film on the main surface;
Mounting the semiconductor chip on a chip mounting portion;
Forming a sealed body by resin sealing the semiconductor chip, a method of manufacturing a semiconductor device,
A method of manufacturing a semiconductor device, comprising: performing resin sealing so that the step portion of the surface protection film of the semiconductor chip and the sealing body are in contact with each other during the resin sealing.
JP2002369215A 2002-12-20 2002-12-20 Semiconductor device and manufacturing method therefor Pending JP2004200532A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006318989A (en) * 2005-05-10 2006-11-24 Matsushita Electric Ind Co Ltd Semiconductor device
JP2012518282A (en) * 2009-02-18 2012-08-09 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Semiconductor chip with reinforcement layer
WO2014181766A1 (en) * 2013-05-07 2014-11-13 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device and semiconductor device manufacturing method
JP2021040058A (en) * 2019-09-04 2021-03-11 三菱電機株式会社 Semiconductor device and semiconductor element

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006318989A (en) * 2005-05-10 2006-11-24 Matsushita Electric Ind Co Ltd Semiconductor device
JP4675147B2 (en) * 2005-05-10 2011-04-20 パナソニック株式会社 Semiconductor device
JP2012518282A (en) * 2009-02-18 2012-08-09 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Semiconductor chip with reinforcement layer
WO2014181766A1 (en) * 2013-05-07 2014-11-13 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device and semiconductor device manufacturing method
JP2021040058A (en) * 2019-09-04 2021-03-11 三菱電機株式会社 Semiconductor device and semiconductor element
JP7149907B2 (en) 2019-09-04 2022-10-07 三菱電機株式会社 Semiconductor devices and semiconductor elements

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