JPH0196947A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To remove the generation of a parasitic capacitance between lower layer wirings interrupted by conductive layers formed between two or more interlayer insulating films and between the lower and upper layer wirings by forming the conductive layers between the interlayer insulating films, leading electrodes from the conductive layers and controlling its potential, for example, to a ground level. CONSTITUTION:Source, drain diffused layers 2, 2 and a field oxide film 3 are formed on a silicon substrate 1. A gate electrode 5 is disposed between the layers 2 and 2 on the substrate 1. Further, first wirings 6, such as aluminum wirings or the like are formed on an insulating film 4 formed on a gate electrode 5, and an interlayer insulating film 7 made of a first interlayer insulating film 7' and a second interlayer insulating film 7'' for insulating to second wirings 8 is formed on the wirings 6. A conductive layer 9 disposed at the intermediate of the first wirings 6, 6 and formed, for example, of an aluminum film at the side is formed between the layers 7' and 7''. Further, second wirings 8, such as aluminum wirings or the like are formed on the film 7''. The wirings 8 are electrically connected to the layer 9 through a connecting hole 7a opened in the film 7 to lead electrodes.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Field of Application) The present invention is directed to a device having two or more layers of wiring, and in particular to suppressing wiring capacitance (parasitic capacitance ff1 between wirings) as much as possible. The present invention relates to a semiconductor device that is optimal for use as a high-speed LSI, and a method for manufacturing the same.

(Prior Art) Conventionally, as a semiconductor device as a transistor having, for example, two layers of wiring, an upper layer and a lower layer, a device as shown in FIG. 5 has been generally known.

That is, source/drain diffusion layers 2, 2 and a filled oxide film 3 are formed on the upper surface of the silicon substrate 1, and a gate oxide film is formed on the silicon base 1 between the source/drain diffusion layers 2.2. A gate electrode 5 is arranged therebetween.

Then, an insulating film 4 is formed on the gate electrode 5, and a first (lower layer) wiring 6 such as an Ag wiring is formed on the upper surface of this insulating film 4. the second of
An interlayer insulating film 7 is formed to insulate the (upper layer) wiring 8, and a second layer such as Ag wiring is formed on the upper surface of this interlayer insulating film 7.
(Upper layer) wires 8 were formed, and the lower layer wires 6 and the upper layer wires 8 were electrically connected through connection holes 7a opened in the interlayer insulating layer 7.

(Problems to be Solved by the Invention) However, in the case of the above conventional example, as shown in FIG. Parasitic capacitance C1.

C2 and C3 occur. In recent years, as high integration has progressed, this wiring has become finer, and multilayer wiring structures have been stacked from two layers to three to four layers. There is a problem in that the increase in the number 2 results in an increase in the parasitic capacitance, which becomes a major obstacle to speeding up.

In view of the above, it is an object of the present invention to suppress the parasitic capacitance between wirings in a multilayer wiring structure as much as possible, thereby increasing the speed of an LSI.

[Structure of the invention]

f-stage for solving the unit problem) In order to achieve the above object, the present invention provides a semiconductor device with two or more layers of wiring, in which an arbitrary layer in the interlayer insulating film between the lower layer wiring and the upper layer wiring is provided. A semiconductor device in which a conductive layer is formed at a position, and an electrode is taken out from the conductive layer, and a step of forming a lower layer wiring; a step of forming a first interlayer insulating film on the upper surface of the lower layer wiring; A step of forming a conductive layer on the upper surface of the first interlayer insulating film, a step of removing the conductive layer located above the wiring in the lower layer by an etch-back method, and a step of forming a second interlayer insulating layer on the upper surface of the conductive layer. The gist of this invention is a method for manufacturing a semiconductor device which includes a step of forming a film and a step of forming an upper layer wiring on the upper surface of the second interlayer insulating film.

(Function) By forming a conductive layer between two or more interlayer insulating films, taking out an electrode from this conductive layer, and controlling the potential of this electrode to, for example, ground level,
This is intended to eliminate the generation of parasitic capacitance between the lower layer interconnects and between the lower layer and upper layer interconnects interrupted by this conductive layer.

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which a source/drain diffusion layer 2.2 and a filled oxide film 3 are formed on the upper surface of a silicon substrate 1. A gate electrode 5 is arranged on the silicon substrate 1 between the diffusion layers 2 .

Further, on the upper surface of the insulating film 4 formed on the gate electrode 5,
A first (lower layer) wiring 6 such as the Aj7 wiring is formed, and a first interlayer insulating film 7' is formed on the upper surface of the first wiring 6 to insulate it from the second (upper layer) wiring 8 described below. and a second interlayer insulating film 7', and between the first and second interlayer insulating films 7' and 7', the lower wirings 6, 6 are formed. A conductive layer 9 made of, for example, an aluminum film is formed on the sides of the conductive layer 9, located in the middle of the conductive layer 9.

Further, an upper layer (second) wiring 8 such as an Ag wiring is formed on the upper surface of the second interlayer insulating film 7', and the upper layer wiring 8 and the conductive layer 9 are connected to the interlayer insulating film 7'. Membrane 7
The electrodes are electrically connected to each other through connection holes 7a opened to the electrodes.

By controlling the potential of this electrode to, for example, the ground level, parasitic capacitance ( The parasitic capacitances C2 and C3 shown in FIG. 6 can be removed, thereby making it possible to remove a considerable amount of the total parasitic capacitance.

Next, this manufacturing method will be explained.

First, a source/drain diffusion layer 2.2 and a filled oxide film 3 are formed on the upper surface of a silicon substrate 1 using a conventional method, and a gate electrode 5 and an insulating film 4 are formed on these upper surfaces.
Furthermore, a first (lower layer) layer such as aluminum wiring is formed on the upper surface of this insulating film 4.
The wiring 6 is formed with a film thickness of, for example, about 6000A.

Thereafter, a first interlayer insulating film 7' such as a plasma CVD film is formed on the entire surface with a thickness of about 3,000, for example, on the upper surface, and a conductive layer 9 such as an aluminum layer is further formed on the upper surface.
It is formed on the entire surface with a film thickness of about 0,000.

In this state, as shown in FIG. 2, a resist 10 for etchback is formed on the upper surface of the conductive layer 9.

Then, as shown in FIG. 3, after removing the resist lO and conductive layer 9 above the lower layer wiring 6 by etching back, the first layer ff? I insulating film 7'
Approximately 1,000 people will also be removed from the surface.

Thereafter, as shown in FIG. 4, the remaining resist 10 is removed by plasma etching or the like, and a second interlayer insulating film 7'' such as a plasma CVD film is formed on the upper surface with a thickness of, for example, 300 mm.
Formed on the entire surface with a film thickness of about 0.

After opening a connection hole 7a in the interlayer insulating layer 7 for connecting the lower layer wiring 6 and the upper layer wiring 8 (not shown), a lower wiring layer such as an aluminum wiring is formed and patterned. , apply the lower layer wiring LA8, and connect the above connection hole 7a.
The conductive layer 9 and the lower wiring 8 are connected through the conductive layer 9, and the semiconductor device shown in FIG. 1 from which the electrodes are taken out is manufactured.

〔Effect of the invention〕

Since the present invention has the above-mentioned configuration, by taking out the electrode from the conductive layer and controlling the potential to, for example, the ground level, the conductive layer can connect the lower layer interconnects and the lower layer and upper layer interconnects. Parasitic capacitance can be removed to remove a significant amount of the total parasitic capacitance.

Therefore, it is possible to easily increase the speed of a very large scale integrated circuit (LSI) having multi-layered and fine wiring.

[Brief explanation of the drawing]

1 to 4 show an embodiment of the present invention, FIG. 1 is a cross-sectional view of a semiconductor device according to the present invention, and FIGS. 2 to 4 are cross-sectional views showing this manufacturing method in order of steps. FIG. 5 is a cross-sectional view showing a conventional example, and FIG. 6 is a cross-sectional view showing important parts for explaining the state of occurrence of parasitic capacitance. 5... Gate electrode, 6... Lower layer wiring, 7.7'. 7'... Interlayer insulating film, 7a... Connection hole, 8...
Upper layer wiring, 9... conductive layer. Applicant's agent Mr. Sato -Yuichi IH Figure 2 $3

Claims (1)

[Claims] 1. In a semiconductor device having two or more layers of wiring, a conductive layer is formed at an arbitrary position in an interlayer insulating film between a lower layer wiring and an upper layer wiring, and from this conductive layer A semiconductor device characterized by having electrodes removed. 2. The semiconductor device according to claim 1, wherein the conductive layer is formed between and on the sides of the lower layer wiring. 3. The semiconductor device according to claim 1, wherein the electrode taken out from the conductive layer is connected to an upper layer wiring through a connection hole. 4. A step of forming a lower layer wiring, a step of forming a first interlayer insulating film on the upper surface of this lower layer wiring, a step of forming a conductive layer on the upper surface of this first interlayer insulating film, and a step of forming a conductive layer on the upper surface of this first interlayer insulating film. A step of removing the layer located above the lower layer wiring by an etch-back method, a step of forming a second interlayer insulating film on the upper surface of the layer, and a step of removing the upper layer wiring on the upper surface of the second interlayer insulating film. 1. A method for manufacturing a semiconductor device, comprising the step of forming a semiconductor device. 5. Claims characterized in that after the step of removing the conductive layer above the underlying wiring by the etch-back method, a step of etching back a part of the surface of the first interlayer insulating film is performed. 5. The method for manufacturing a semiconductor device according to item 4.