JPS6194346A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6194346A
JPS6194346A JP21591484A JP21591484A JPS6194346A JP S6194346 A JPS6194346 A JP S6194346A JP 21591484 A JP21591484 A JP 21591484A JP 21591484 A JP21591484 A JP 21591484A JP S6194346 A JPS6194346 A JP S6194346A
Authority
JP
Japan
Prior art keywords
film
etched
stepped sections
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21591484A
Other languages
Japanese (ja)
Inventor
Mamoru Ando
守 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP21591484A priority Critical patent/JPS6194346A/en
Publication of JPS6194346A publication Critical patent/JPS6194346A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent disconnections at stepped sections on processing and the generation of voids, and to improve the degree of integration by etching a first film shaped onto a substrate twice or more, forming two steps of more of stepped sections and shaping second and third films. CONSTITUTION:An impurity, etc. are diffused selectively to the surface of an Si substrate 1 to form a predetermined semiconductor region. An SiO2 film 6 is shaped. A photo-resist 7 is applied, the photo-resist 7 at a position to be etched is removed, and the film 6 is etched only by approximately half thickness of the thickness of the film 6. The film 6 is etched again until the substrate 1 is exposed to shape two stepped sections. A passivation film 2 is formed onto the whole surface, and a film 5 electrically connected to the semiconductor region is shaped onto the film 2. Accordingly, disconnections at stepped sections on processing and the generation of voids are prevented, and the degree of integration can be improved.

Description

【発明の詳細な説明】 0)産業上の利用分野 本発明は熱酸化以外の膜形成において段差を有する半導
体基板上に良好な膜を形成する半導体装置の製造方法に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION 0) Industrial Field of Application The present invention relates to a method for manufacturing a semiconductor device that forms a good film on a semiconductor substrate having a step in film formation other than thermal oxidation.

(ロ)従来の技術 従来より半導体集積回路においてアルミニウム(AI)
電極の段切れや耐圧の低下等が問題となっている。
(b) Conventional technology Aluminum (AI) has traditionally been used in semiconductor integrated circuits.
Problems include disconnection of electrodes and a drop in withstand voltage.

一般には絶縁膜を熱酸化法やCVD法等により形成して
いる。しかし最終工程に近づ(に従い熱酸化法等の高い
処理温度では特性変化等を起すため低い温度で膜を形成
できるCVD法等で絶縁膜を形成している。ところがこ
のCVD法等で半導体集積回路上の絶縁膜を形成しその
上に蒸着等でアルミニウム電極を形成すると段切れや耐
電圧等の特性の低化が問題となっている。
Generally, the insulating film is formed by a thermal oxidation method, a CVD method, or the like. However, as the final process approaches (according to which high processing temperatures such as thermal oxidation methods cause characteristic changes, insulating films are formed using CVD methods that can form films at low temperatures. However, with this CVD method, semiconductor integration When an insulating film is formed on a circuit and an aluminum electrode is formed on the insulating film by vapor deposition or the like, problems arise such as breakage and deterioration of characteristics such as withstand voltage.

この1例としてサイエンスフォーラム社出版のLSIプ
ロセスハ・多ドプックヒ323〜P、 324図−18
(a)および(d)に示されており半導体基板t61)
上のパッシペイシ冒ン膜(62に形成したコンタクト孔
關の縁部(64)にAI膜田がかかる場合であり、シリ
コン基板61)の表面にパッシベイシミン膜として例え
ばS J Ot Jl!’8’Jを熱酸化以外の方法で
形成し、蝕刻法によりコンタクト孔のを5int上に形
成し、その上にAI電極を蒸着等により形成していた。
An example of this is LSI Process Handbook 323-P, 324 Figure-18 published by Science Forum.
Semiconductor substrate t61) shown in (a) and (d)
This is the case where the AI film is applied to the edge (64) of the contact hole formed in 62, and a passivation film is formed on the surface of the above passivation film (silicon substrate 61), for example, S J Ot Jl! '8'J was formed by a method other than thermal oxidation, a contact hole was formed 5 inches above by etching, and an AI electrode was formed thereon by vapor deposition or the like.

また特開昭57−26432号公報(第5図)に示す如
く絶縁膜(財)を蝕刻コンタクト孔183)を形成する
。この上に粘性のある絶縁材(財)例えばポリイミド系
樹脂または5OG(ガラス粉末を無機容剤にとかしたも
の)等を塗布する(第5図(f))。その後粘性のある
絶縁材(財)を蝕刻しコンタクト孔(ハ)の急峻な縁部
をなだらかな形状とする(第5図(ロ))。
Further, as shown in Japanese Unexamined Patent Publication No. 57-26432 (FIG. 5), a contact hole 183) is formed by etching the insulating film. A viscous insulating material such as polyimide resin or 5OG (glass powder dissolved in an inorganic agent) or the like is applied thereon (FIG. 5(f)). After that, the viscous insulating material (material) is etched to make the steep edges of the contact hole (c) into a gentle shape (Fig. 5 (b)).

最後にAI(へ)を除去して形成していた(第2図(ハ
))。
Finally, it was formed by removing AI(c) (FIG. 2(c)).

(ハ)発明が解決しようとする問題点 上述のようにして形成した半導体装置においてSin、
膜鏝が厚いとコンタクト孔關を形成した際S io、膜
鏝の断面がオーバーハング状態となり、そのためSin
、膜(6eの縁部の4)ではAI膜(へ)が薄くなるた
め断線が生じやすい。また到達する原子のShadow
ing効果よりコンタクト孔關の段差側面の膜は平坦部
にくらべ密度が低く、湿式のエツチングにおいてはエツ
チング速度が大きいため加工時の段切れやVoidを生
じ膜自体の特性を悪化させる。実際のデバイスに於ても
静電破壊箇所は膜の平坦部[F]ηではなく縁部(財)
に集中している。
(c) Problems to be solved by the invention In the semiconductor device formed as described above, Sin,
If the membrane trowel is thick, when forming the contact hole, the cross section of the membrane trowel will be in an overhanging state, resulting in
In the film (4 at the edge of 6e), the AI film (to) is thinner, so disconnection is likely to occur. The shadow of the atom that also arrives
Due to the ing effect, the density of the film on the side surface of the step of the contact hole is lower than that of the flat part, and in wet etching, the etching speed is high, resulting in step breaks and voids during processing, deteriorating the properties of the film itself. In actual devices, the electrostatic breakdown point is not at the flat part [F]η of the film but at the edge.
is concentrated on.

また粘性のある絶縁材(財)を第5図の如く形成しコン
タクト孔※の急峻な縁部□をなだらかに形成する方法に
おいてはS iO,膜eηの膜厚が大きくなるほど第5
図(ハ)に示すWが広くなり高集積度が不可能となる。
In addition, in the method of forming a viscous insulating material (material) as shown in Fig. 5 and forming the steep edge □ of the contact hole* smoothly, the thickness of the SiO film eη increases,
W shown in FIG. 3(c) becomes wide, making it impossible to achieve a high degree of integration.

に)問題を解決するための手段 本発明はAI膜[F]9の断線を防止し特性を向上させ
かつ集積度を向上させる半導体装置の製造方法を提供し
ようとするものであり、半導体基板(1)上の表面に形
成される第1の膜(6)を選択的に蝕刻し再度少なくと
も1回以上蝕刻することで第1の膜(6)の段差を2段
以上形成することで解決しようとするものである。
The present invention aims to provide a method for manufacturing a semiconductor device that prevents disconnection of the AI film [F] 9, improves its characteristics, and improves the degree of integration. 1) The problem can be solved by selectively etching the first film (6) formed on the upper surface and etching it again at least once to form two or more steps in the first film (6). That is.

(ホ)作用 半導体基板(1)上の表面に形成される第1の膜(6)
を少なくとも2回以上蝕刻することで段差は少なくとも
2個以上形成される。従りてこの膜(6)の厚さは従来
の膜(6)の厚さより薄くなりShadowi ng現
象を減少させることが可能となる。その結果従来の保護
すべき領域内の欠陥部分を無くすことが可能となる。ま
たオーバーハングも形成しに(くなる。
(e) First film (6) formed on the surface of the working semiconductor substrate (1)
By etching at least twice, at least two steps are formed. Therefore, the thickness of this film (6) is thinner than that of the conventional film (6), making it possible to reduce the shadowing phenomenon. As a result, it becomes possible to eliminate defective parts within the area to be protected, which was conventional. It also prevents overhangs from forming.

(へ)実施例 以下に本発明に係る半導体装置の一実施例を図面を参照
しながら説明する。
(F) Embodiment An embodiment of the semiconductor device according to the present invention will be described below with reference to the drawings.

第1図は半導体装置の製造方法を示し第1工程は第1図
0)の如(Si半導体基板(1)の表面に不純物の選択
拡散を行ない所定の半導体領域を形成する。その後S 
io、膜(6)をCVD法等で形成し、蝕刻で段差を設
けるために全体にホトレジスト(力を塗布する。更に蝕
刻されるべき所定の場所のホト。
FIG. 1 shows a method for manufacturing a semiconductor device, and the first step is as shown in FIG.
io, a film (6) is formed by a CVD method or the like, and a photoresist is applied to the entire surface to form a step by etching.

レジスト(力を除去する。Resist (remove force).

第2工程は第1図(ロ)の如く前工程で形成した半導体
基板(1)を所定の方法で蝕刻する。従来は半導体基板
(1)が露出するまで蝕刻していたが、ここでは第1の
膜(6)の厚さの約1/2の厚さの分だけ蝕刻する。
In the second step, as shown in FIG. 1(b), the semiconductor substrate (1) formed in the previous step is etched by a predetermined method. Conventionally, etching was performed until the semiconductor substrate (1) was exposed, but here, etching is performed by approximately 1/2 of the thickness of the first film (6).

第3工程は第1図(ハ)の如く約1/2の厚さの分だけ
蝕刻した第1の膜(6)を半導体基板(1)が露出する
まで再度蝕刻する。この時点で段差が2ケ所形成される
。そして前記半導体基板(1)全体を覆うようにパッシ
ベイション膜(2)を形成する。さらに第1工程で形成
した半導体領域と電気的に接続されかつ第2の膜(2)
上に形成される第3の膜(5)を形成する。
In the third step, as shown in FIG. 1(C), the first film (6), which has been etched by about 1/2 of its thickness, is etched again until the semiconductor substrate (1) is exposed. At this point, two steps are formed. A passivation film (2) is then formed to cover the entire semiconductor substrate (1). Furthermore, a second film (2) is electrically connected to the semiconductor region formed in the first step.
A third film (5) is formed on top.

ここで第2工穐と第3工程は本発明の特徴とする所であ
り第1の膜(6)を少なくとも2回以上蝕刻し段差の数
を少な(とも2個以上にするとShadowing現象
として影響を与える膜の高さが低(なりShadowi
ng現象は減少するうそのため膜の密度は段差側面と平
坦部でほぼ均一となり加工時の段切れやVoidの発生
を防止する。以上の結果デバイスに於いてAIのマイグ
レーションなどによる静電破壊が防止できる。また第5
図の如(コンタクト孔の急峻な縁部−をなだらかに形成
する必要がないために高集積が可能となる。
Here, the second process and the third process are the characteristics of the present invention, and the first film (6) is etched at least twice to reduce the number of steps (if the number of steps is 2 or more, shadowing phenomenon may occur). The height of the film that gives the shadow is low (Shadowi
Since the NG phenomenon is reduced, the density of the film becomes almost uniform on the side surfaces of the step and the flat portion, thereby preventing step breaks and voids from occurring during processing. As a result of the above, electrostatic damage caused by AI migration can be prevented in the device. Also the fifth
As shown in the figure, since there is no need to form the steep edges of the contact hole smoothly, high integration is possible.

(ト)発明の効果 本発明は以上の説明からも明らかな如く半導体基板(1
)上の第1の膜(6)を少なくとも2度以上蝕刻し、第
1の膜に少なくとも2段以上の段差を形成する。その結
果第2の膜(2)、第3の膜(5)等を形成する際Sh
adowing現象が減り加工時の段切れやVoidの
発生が防止できる。そのためAIのマイグレーション等
の原因による静電破壊が防止可能となる。
(g) Effects of the invention As is clear from the above description, the present invention provides a semiconductor substrate (1
) is etched at least twice to form at least two or more steps in the first film. As a result, when forming the second film (2), third film (5), etc., Sh
The adowing phenomenon is reduced, and the generation of step breaks and voids during machining can be prevented. Therefore, electrostatic damage caused by AI migration or the like can be prevented.

またコンタクト孔(3)の急峻な縁部(4)をなだらか
にするため粘性の絶縁材を塗布する必要がなく高集積が
可能となる。
In addition, since the steep edge (4) of the contact hole (3) is smoothed, there is no need to apply a viscous insulating material, allowing for high integration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(イ)乃至第1図(ハ)は本発明の一実施例を示
す半導体装置の製造方法を説明する断面図、第2図は本
発明の一実施例である半導体装置の拡大された断面図、
第3図は従来の半導体装置の拡大された断面図、第4図
(イ)乃至第4図(ハ)および第5図ビ)乃至第5図(
ハ)は従来の半導体装置を説明する断面図である。 主な図番の説明 (1)は半導体基板、 (2)は第2の膜、 (3)は
コンタクト孔、 (4)は縁部、 (5)は第3の膜、
 (6)は第1の膜、 (力はホトレジストである。 出願人 三洋電機株式会社 外1名 代理人 弁理士 佐 野 靜 夫 第1図(イ) 第 1 図 (D) 第 1 図(l−) 第2図 第3図 第 4 図(ロ) 第4図(ハ)
1(a) to 1(c) are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an enlarged view of a semiconductor device according to an embodiment of the present invention. cross-sectional view,
FIG. 3 is an enlarged cross-sectional view of a conventional semiconductor device, FIGS. 4(A) to 4(C) and FIGS.
C) is a sectional view illustrating a conventional semiconductor device. Explanation of the main drawing numbers: (1) is the semiconductor substrate, (2) is the second film, (3) is the contact hole, (4) is the edge, (5) is the third film,
(6) is the first film; -) Figure 2 Figure 3 Figure 4 (B) Figure 4 (C)

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板上の表面に形成される第1の膜を選択
的に蝕刻し前記半導体基板の全面を覆うように第2の膜
を形成し前記半導体基板内の所定の領域と電気的に接続
されかつ第2の膜上に第3の膜を形成する半導体装置の
製造方法において、前記第1の膜を2段以上に形成する
ことを特徴とした半導体装置の製造方法。
(1) A first film formed on the surface of the semiconductor substrate is selectively etched to form a second film so as to cover the entire surface of the semiconductor substrate, and the second film is electrically connected to a predetermined region within the semiconductor substrate. 1. A method of manufacturing a semiconductor device in which a third film is formed on a second film connected to the second film, the first film being formed in two or more stages.
JP21591484A 1984-10-15 1984-10-15 Manufacture of semiconductor device Pending JPS6194346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21591484A JPS6194346A (en) 1984-10-15 1984-10-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21591484A JPS6194346A (en) 1984-10-15 1984-10-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6194346A true JPS6194346A (en) 1986-05-13

Family

ID=16680340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21591484A Pending JPS6194346A (en) 1984-10-15 1984-10-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6194346A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8097329B2 (en) 2006-06-30 2012-01-17 Casio Computer Co., Ltd. Thin film device having thin film elements and thin film pattern on thin film elements, and method of fabricating the same
WO2016021318A1 (en) * 2014-08-07 2016-02-11 シャープ株式会社 Active matrix substrate, liquid crystal panel and method for producing active matrix substrate
WO2016021320A1 (en) * 2014-08-07 2016-02-11 シャープ株式会社 Active matrix substrate and method for producing same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8097329B2 (en) 2006-06-30 2012-01-17 Casio Computer Co., Ltd. Thin film device having thin film elements and thin film pattern on thin film elements, and method of fabricating the same
WO2016021318A1 (en) * 2014-08-07 2016-02-11 シャープ株式会社 Active matrix substrate, liquid crystal panel and method for producing active matrix substrate
WO2016021320A1 (en) * 2014-08-07 2016-02-11 シャープ株式会社 Active matrix substrate and method for producing same
JPWO2016021318A1 (en) * 2014-08-07 2017-04-27 シャープ株式会社 Active matrix substrate and liquid crystal panel
JPWO2016021320A1 (en) * 2014-08-07 2017-04-27 シャープ株式会社 Active matrix substrate

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