JPH0383340A - Al multilayer interconnection structure of semiconductor element - Google Patents
Al multilayer interconnection structure of semiconductor elementInfo
- Publication number
- JPH0383340A JPH0383340A JP21868289A JP21868289A JPH0383340A JP H0383340 A JPH0383340 A JP H0383340A JP 21868289 A JP21868289 A JP 21868289A JP 21868289 A JP21868289 A JP 21868289A JP H0383340 A JPH0383340 A JP H0383340A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- layer
- insulating film
- pressure cvd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 34
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 11
- 238000009413 insulation Methods 0.000 claims description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 21
- 238000000034 method Methods 0.000 abstract description 8
- 239000011800 void material Substances 0.000 abstract description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000012528 membrane Substances 0.000 description 4
- 230000008602 contraction Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- CWAFVXWRGIEBPL-UHFFFAOYSA-N ethoxysilane Chemical compound CCO[SiH3] CWAFVXWRGIEBPL-UHFFFAOYSA-N 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体素子のＭ多層配線構造に係り、特に眉
間絶縁膜部分に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an M multilayer wiring structure of a semiconductor device, and particularly relates to the glabella insulating film portion.
（従来の技術）
半導体素子（ＩＣ，ＬＳＩ）においては、配線の自由度
が増し、パターン設計が容易になるなどの利点から、多
層配線構造が採用される傾向にある。この多層配線構造
においては、金属配線層間に眉間絶縁膜を形成する必要
があるが、現在、金属配線材料としてはＭ系合金が主に
用いられているため、眉間絶縁膜は、４５０℃以下の低
温で生成しなければならない、つまり、眉間絶縁膜の形
成時には既に下ＮｆｉＪ配線が形成されており、これを
保護する目的から４５０°Ｃ以下の低温で層間絶縁膜を
生成する必要がある。(Prior Art) In semiconductor devices (ICs, LSIs), there is a tendency for multilayer wiring structures to be adopted because of the advantages of increasing the degree of freedom in wiring and facilitating pattern design. In this multilayer wiring structure, it is necessary to form a glabellar insulating film between the metal wiring layers, but since M-based alloys are currently mainly used as metal wiring materials, the glabellar insulating film can be formed at temperatures below 450°C. The interlayer insulating film must be generated at a low temperature, that is, the lower NfiJ wiring has already been formed when the glabella insulating film is formed, and in order to protect this, the interlayer insulating film must be generated at a low temperature of 450° C. or lower.
このため、層間絶縁膜材質としては、常圧ＣＶＤ酸化膜
（ＡＰ−３ｉｎ、 ＡＰ−ＰＳＧ、ＡＰ−ＢＰＳＧ等、
ＡＰはＡｔｍｏｓｐｈｅｒｅ Ｐｒｅｓｓｕｒｅ （
常圧）の略）あるいはプラズマＣＶＤ酸化膜（Ｐ［！−
５ｉＯ等、ＰＥはＰｌａｓｍａＥｎｈａｎｃｅｄ （プ
ラズマ塩ｔ２）の略）が主に使用されている。また、最
近は、低温形成が可能な上に、形成と同時に平坦膜が得
られるため、常圧ＴＥＯ３酸化膜（ＡＰ−ＴＥ０１ 、
Ｔ Ｅ ＯＳはテトラ・エチル・オキシ・シランを意味
する）、プラズマＣＶＤ酸化膜（ＰＨ−↑［！Ｏ３）が
注目され、使用されている。Therefore, as the interlayer insulation film material, atmospheric pressure CVD oxide film (AP-3in, AP-PSG, AP-BPSG, etc.) is used.
AP is Atmosphere Pressure (
normal pressure)) or plasma CVD oxide film (P[!-
PE such as 5iO is mainly used as PE (Plasma Enhanced (abbreviation for plasma salt t2)). Recently, atmospheric pressure TEO3 oxide film (AP-TE01,
T E OS means tetra ethyl oxy silane) and plasma CVD oxide film (PH-↑[!O3) are attracting attention and being used.
（発明が解決しようとする課題）
しかるに、層間絶縁膜として常圧ＣＶＤ酸化膜あるいは
常圧ＴＥＯ３酸化膜などの常圧ＣＶＤ系絶縁膜を用いる
と、その上に上ＩｉＩＭ配線を形成し、その上にパッシ
ベーション膜としてプラズマＣＶＤ５ＩＮ膜を形成した
時に、前記上層Ｍ配線に「Ｍボイド」と呼ばれるＭ欠損
不良が多発する問題点があった。ここで、「Ｍボイド」
とは第２図に示すように、Ｍ配線パターンｌの一部が符
号２で示すように欠落する現象で、パッシベーション膜
なとのＭ配線被覆膜の膜ストレスによりＭが高温クリー
プすることが原因だと言われている。そして、ｒｐ）ボ
イドＪが存在すると、その付近の電流密度が大きくなり
、エレクトロマイグレーシランによる断線不良を引き起
したりするため好ましくない。(Problem to be solved by the invention) However, when a normal pressure CVD insulating film such as a normal pressure CVD oxide film or a normal pressure TEO3 oxide film is used as an interlayer insulating film, an upper IiIM wiring is formed on it, and When a plasma CVD 5IN film was formed as a passivation film in 1995, there was a problem in that M void defects called "M voids" frequently occurred in the upper layer M wiring. Here, "M void"
As shown in Fig. 2, this is a phenomenon in which a part of the M wiring pattern l is missing as shown by the symbol 2, and M may creep at high temperatures due to film stress on the M wiring coating film such as a passivation film. It is said that this is the cause. If rp) void J exists, the current density in the vicinity increases, which is undesirable because it may cause disconnection due to electromigration silane.
さて、上述のように、層間絶縁膜として常圧ＣＶＤ系絶
！！膜を用いた場合、その上に上層Ｍ配線を形威し、そ
の上にパッシベーション膜としてプラズマＣＶＤＳｉＮ
Ｍを形威した時に前記上層Ｍ配線にＭボイドが発生する
わけであるが、その原因が以下に述べることであること
を本発明者は実験により確かめた。Now, as mentioned above, atmospheric pressure CVD is not suitable for interlayer insulating films! ! If a film is used, an upper layer M wiring is formed on it, and a plasma CVDSiN film is formed on it as a passivation film.
When M is formed, M voids are generated in the upper layer M wiring, and the inventor has confirmed through experiments that the cause thereof is as described below.
つまり、第３図（ａ）に示すように常圧ＣＶＤ系絶縁１
１！１１上にＭ配線１２が形威されている場合、この上
にパッシベーション膜としてプラズマＣＶＤ５ｉＮＷＪ
を形成すると、次のような現象が起きる。In other words, as shown in FIG. 3(a), the normal pressure CVD insulation 1
1! When the M wiring 12 is formed on the 11, a plasma CVD 5iNWJ is applied as a passivation film on the M wiring 12.
When formed, the following phenomena occur.
すなわち、常圧ＣＶＤ系絶縁膜１１は、加熱すると水分
を放出して収縮する性質を持ち、プラズマＣＶＤ５ｉＮ
膜の生成温度（３５０〜４００°Ｃ）では、この水分放
出が起き、常圧ＣＶＤ系絶縁膜１１はどんどん収縮しよ
うとする。ところが、プラズマＣＶＤ５＋Ｎｇは水分を
ほとんど透過させないため、該プラズマＣＶＤ５ｉＮ膜
の厚さがある程度以上になると、常圧ＣＶＤ系絶縁膜１
１からの水分放出がストップし、膜収縮が起きなくなる
。ところが、第３図伽）に示すように、Ｍ配線１２の側
壁部においてはプラズマＣＶＤ５ｉＮｌｌｉ１３のＩＩ
Ｉ賞が良くないために、この部分からは水分（）ｌｚｏ
）がある程度透過してしまう、そのため、Ｍ配線１２近
傍の常圧ＣｖＤｗＡ縁膜１１だけに、第３図（ｂ）に矢
印で示すように水分放出による膜収縮が生しる。このた
め、プラズマＣＶＤ５ｉＮｌ！１３の持つ圧縮応力の作
用に、下地常圧ＣＶＤ系絶縁膜１１の上述したような局
部的な膜収縮の作用が加わって、Ｍ配線１２内に大きな
引張り応力が発生して、多数の大きなＭボイドが発生し
てしまう。That is, the atmospheric pressure CVD insulating film 11 has the property of releasing moisture and shrinking when heated, and the plasma CVD 5iN
At the film formation temperature (350 to 400° C.), this water release occurs and the normal pressure CVD insulating film 11 tends to shrink more and more. However, since plasma CVD5+Ng hardly allows moisture to pass through, if the thickness of the plasma CVD5iN film exceeds a certain level, the atmospheric pressure CVD insulating film 1
Water release from 1 stops, and membrane contraction no longer occurs. However, as shown in FIG.
Since the I prize is not good, moisture () lzo from this part
) is permeated to some extent, so that only the atmospheric pressure CvDwA edge film 11 near the M wiring 12 undergoes film contraction due to moisture release, as shown by the arrow in FIG. 3(b). For this reason, plasma CVD5iNl! The above-mentioned local film contraction of the base atmospheric pressure CVD insulating film 11 is added to the compressive stress of the M wiring 13, and a large tensile stress is generated within the M wiring 12, resulting in a large number of large M A void will occur.
この発明は上記の点に鑑みなされたもので、眉間絶縁膜
として常圧ＣＶＤ系絶縁膜を用いた場合における、パッ
シベーション膜（ＳｉＮ膜）性成時の、上層Ｍ＆！線上
のＭボイドの発生を防止できる半導体素子のＭ多層配線
構造を提供することを目的とするや
（課題を解決するための手段）
この発明は、眉間絶縁膜として常圧ＣＶＤ系絶縁膜が用
いられ、その上に上層Ｍ配線が形威され、その上にパッ
シベーション膜として５ｉＮＩｌｌが形威される半導体
素子のＭ多層配線構造において、前記常圧ＣＶＤ系絶縁
膜上の全面をＳｉＮ膜で覆い、その上に上ＮＭ配線を形
威し、その上にパッシベーション膜としてのＳｉＮ膜を
形成するようにしたものである。This invention has been made in view of the above points, and when an atmospheric pressure CVD insulating film is used as the glabellar insulating film, the upper layer M&! It is an object of the present invention to provide an M multilayer wiring structure of a semiconductor device that can prevent the occurrence of M voids on lines (means for solving the problem). In the M multilayer wiring structure of a semiconductor device, in which an upper layer M wiring is formed on top of the upper layer M wiring, and a 5iNIll is formed as a passivation film thereon, the entire surface of the atmospheric pressure CVD insulating film is covered with a SiN film, An upper NM wiring is formed thereon, and an SiN film is formed thereon as a passivation film.
（作 用）
上記この発明のＭ多層配線構造においては、眉間絶縁膜
としての常圧ＣＶＤ系絶縁膜上の全面が、パッシベーシ
ョン膜と同様なＳｉＮ膜（水分を遮断するｌＩりであら
かじめ覆われている。したがって、製造時、最終工程で
パッシベーション膜（ＳｉＮ膜）を形成した時に、その
ＩＩ！質が上ＩＷＡＩ配線の側壁部で良くなく、この部
分では、眉間絶縁膜（常圧ＣＶＤ系絶縁膜）からの局部
的な水分放出が起る恐れがあっても、この水分放出は、
常圧ＣＶＤ系絶縁膜上の全面にあらかしめ形成されてい
るＳｉＮ膜で防止される。すなわち、この発明の構造と
すれば、パッシベーション膜生成時に、常圧ＣＶＤ系絶
縁膜からの局部的な水分放出がなく、その水分放出に伴
う常圧ＣＶＤ系絶縁膜の局部的な膜収縮が防止される。(Function) In the above-mentioned M multilayer wiring structure of the present invention, the entire surface of the atmospheric pressure CVD insulating film as the glabellar insulating film is covered in advance with a SiN film (Il film that blocks moisture) similar to the passivation film. Therefore, when a passivation film (SiN film) is formed in the final process during manufacturing, its II! ), this water release is
This is prevented by the SiN film that is formed over the entire surface of the atmospheric pressure CVD insulating film. That is, with the structure of the present invention, there is no local release of moisture from the atmospheric pressure CVD insulating film during the generation of the passivation film, and local shrinkage of the atmospheric pressure CVD insulating film due to the moisture release is prevented. be done.
したがって、パッシベーション膜生成時の上層Ｍ配線上
でのＭボイドの発生がなくなる。Therefore, the generation of M voids on the upper layer M wiring during the generation of the passivation film is eliminated.
（実施例）
以下この発明の一実施例を図面の簡単な説明する、第１
図はこの発明のＭ多層配線構造の一実施例を示す断面図
である。この図において、２１は半導体基板にＩＣ回路
を作り込み、その上を絶縁膜で覆った下地層である。こ
の下地Ｊｌｉ２１上に１００％ＭまたはＭ系合金からな
る第１層Ｍ配線２２が形威される。さらにその第１層Ｍ
配線２２を覆って下地層２１上の全面には、眉間絶縁膜
としテノ常圧ＣＶＤ系絶縁膜２３例えばＡＰ−ＰＳＧｌ
ｌｉ 。(Embodiment) Below, an embodiment of the present invention will be briefly explained with reference to the drawings.
The figure is a sectional view showing an embodiment of the M multilayer wiring structure of the present invention. In this figure, reference numeral 21 denotes a base layer on which an IC circuit is formed on a semiconductor substrate and covered with an insulating film. A first layer M wiring 22 made of 100% M or M-based alloy is formed on this base Jli21. Furthermore, the first layer M
The entire surface of the base layer 21 covering the wiring 22 is coated with an atmospheric pressure CVD insulating film 23, for example, AP-PSGl, as an insulating film between the eyebrows.
li.
ＡＰ−３ｔＯ□膜、 ＡＰ−ＢＰＳＧ膜、ＡＰ−ＴＥ０
１膜 が５０００人〜１ｆａＷ−に形威される。そして
、この常圧ＣＶＤ系絶縁膜２３上には、該絶縁膜２３上
の全面を覆ってプラズマＣＶＤ５ｉＮ膜２４が約５００
Å以上の厚さに形威される。そして、このプラズマＣＶ
Ｄ５ｉＮ膜２４上に、第１層と同一材質の第２層Ｍ配線
２５が形威され、さらにこの第２層Ｍ配線２５を覆って
パッシベーション膜としてのプラズマＣＶＤ５ｉＮ膜２
６が前記ＳｉＮ膜２膜上４上面に５０００Å以上の厚さ
に形成される。AP-3tO□ membrane, AP-BPSG membrane, AP-TE0
One membrane is affected by 5,000 people to 1 faW-. Then, on this atmospheric pressure CVD type insulating film 23, a plasma CVD 5iN film 24 with a thickness of about 500 nm is formed covering the entire surface of the insulating film 23.
It has a thickness of Å or more. And this plasma CV
A second layer M wiring 25 made of the same material as the first layer is formed on the D5iN film 24, and a plasma CVD 5iN film 2 is formed as a passivation film to cover the second layer M wiring 25.
6 is formed on the upper surface of the SiN film 2 to a thickness of 5000 Å or more.
このようなＭ多層配線構造は次のように製造される。ま
ず下地層２１上に通常のスパッタ蒸着法およびホトリソ
・エツチング技術によって第１層Ｍ配線２２を形威した
後、それらの上に、常圧ＣＶＤ法により４５０°Ｃ以下
の低温で常圧ＣＶＤ系絶縁＠２３を５０００人〜Ｉｎ厚
に形威する。その後、その常圧ＣＶＤ系絶縁膜２３上の
全面にプラズマＣＶＤ法によりプラズマＣＶＤ５ｉＮ膜
２４を約５００Å以上の厚さに均一に生成した後、その
プラズマＣＶＤ５ｉＮ膜２４上に第１層と同様な方法で
第２層Ｍ配線２５を形成する。最後に、この第２１ｉＡ
／配線２５とプラズマＣＶＤ５ｉＮ膜２４上の全面に、
バッジベージジン膜としてのプラズマＣＶＤ５ｉＮ膜２
６をプラ：Ｘ ’？ ＣＶ Ｄ法により５０００Å以上
の厚さに形成する。この時、プラズマＣＶＤ５ｉＮ膜２
６は、第２層Ｍ配線２５の側壁部においては膜質が良く
なく、この部分では、常圧ＣＶＤ系絶縁膜２３からの局
部的な水分放出が起る恐れがあるが、この方法（この構
造）によれば、常圧ＣＶＤ系絶縁膜２３上の全面にあら
かじめプラズマＣＶＤ５ｉＮ膜２４が均一に形威されて
いるので、このプラズマＣＶＤ５ｉＮ膜２４により局部
的な水分放出が防止される。したがって、局部的な水分
放出に伴う常圧ＣＶＤ系絶縁膜２３の局部的な膜収縮も
なく、その結果として第２ＮＡＺ配線２５上でのＭボイ
ドの発生も防止される。Such an M multilayer wiring structure is manufactured as follows. First, the first layer M wiring 22 is formed on the base layer 21 by ordinary sputter deposition method and photolithography/etching technique, and then the first layer M wiring 22 is formed on the base layer 21 by normal pressure CVD method at a low temperature of 450°C or less. Form the insulation@23 to a thickness of 5,000 ~ In. Thereafter, a plasma CVD 5iN film 24 with a thickness of about 500 Å or more is uniformly formed on the entire surface of the atmospheric pressure CVD insulating film 23 by the plasma CVD method, and then a plasma CVD 5iN film 24 is formed on the plasma CVD 5iN film 24 using the same method as the first layer. Then, the second layer M wiring 25 is formed. Finally, this 21st iA
/The entire surface of the wiring 25 and the plasma CVD 5iN film 24,
Plasma CVD 5iN film 2 as a badge beige film
Pla 6:X'? It is formed to a thickness of 5000 Å or more by CVD method. At this time, plasma CVD 5iN film 2
6, the film quality is not good on the side wall part of the second layer M wiring 25, and there is a possibility that local moisture release from the atmospheric pressure CVD type insulating film 23 may occur in this part. ), since the plasma CVD 5iN film 24 is uniformly formed on the entire surface of the atmospheric pressure CVD insulating film 23 in advance, the plasma CVD 5iN film 24 prevents local water release. Therefore, there is no local film shrinkage of the normal pressure CVD insulating film 23 due to local moisture release, and as a result, the generation of M voids on the second NAZ wiring 25 is also prevented.
なお、上記一実施例では、プラズマＣＶＤ５ｉＮ膜２６
単層でバッジベージジン膜を構成したが、前記プラズマ
ＣＶＤ５ｉＮ膜２６の下にＰＳＧ膜を設けてバッジベー
ジ３ン膜を２Ｎ構造としてもよい、この２層構造におい
ても、従来同様にしてＭボイドの問題点があり、この発
明によればそれを解決できる。ただし、バッジベージジ
ン膜がＰＳＧＳ単膜の場合は、この発明は不要である。Note that in the above embodiment, the plasma CVD 5iN film 26
Although the Badge Beige film is made up of a single layer, it is also possible to provide a PSG film under the plasma CVD 5iN film 26 to make the Badge Beige film 2N structure. In this two-layer structure, M voids can be solved in the same manner as in the conventional method. There are problems, and this invention can solve them. However, this invention is not necessary if the Badge Beige film is a single PSGS film.
それは、ＰＳＧ膜の場合は、膜質の良し悪しに関係なく
全面で常圧ＣＶＤ系絶縁膜（層間絶縁膜）からの水分の
放出が行われるからである。全面で水分の放出が行われ
れば、眉間絶縁膜の局部的な膜収縮が起らず、延いては
第２層Ｍ配線上にＭボイドが生じないのである。この発
明は、パッシベーション膜の少なくとも一部がＳｉＮ膜
（水分を遮断するＦｉ）であって、ｆｉ Ｓ ｉ Ｎ
’Ｉｌｌが上ＭＡＩ配線の側壁部でばｌ！質が悪く、そ
の部分では層間絶縁膜（常圧ＣＶＤ系絶縁膜）からの水
分放出が起る場合に必要となるのである。This is because, in the case of a PSG film, moisture is released from the atmospheric pressure CVD insulating film (interlayer insulating film) over the entire surface, regardless of the quality of the film. If moisture is released over the entire surface, local shrinkage of the glabellar insulating film will not occur, and as a result, no M voids will occur on the second layer M wiring. In the present invention, at least a part of the passivation film is a SiN film (Fi that blocks moisture), and
'Ill is the side wall of the upper MAI wiring! This is necessary when the quality is poor and moisture is released from the interlayer insulating film (atmospheric pressure CVD type insulating film) in that area.
（発明の効果）
以上詳細に説明したようにこの発明によれば、層間絶縁
膜として常圧ＣＶＤ系絶縁膜を用い、バッジベージ１ン
膜としてＳｉＮ膜を用いたＭ多層配線構造において、層
間絶縁膜上の全面を５ｉＮｌｉで覆い、その上に上ＮＭ
配線を形成し、その上にバッジベージ１ン膜としてのＳ
ｉＮ膜を形成するようにしたので、製造時、最終工程で
バッジベージジン膜（ＳｉＮ膜）を形威した時に、その
膜質が上層Ｍ配線の側壁部で良くなくても、前記層間絶
縁膜上の全面にあらかじめ形威しであるＳｉＮ膜によっ
て、眉間絶縁膜からの局部的な水分放出、それに伴う眉
間絶縁膜の局部的な膜収縮を防止でき、延いては上層Ｍ
配線上のＭボイドの発生を防止できる。したがって、信
頼性の高いＭ多層配線構造を得ることができる。(Effects of the Invention) As described in detail above, according to the present invention, in an M multilayer wiring structure in which a normal pressure CVD insulating film is used as an interlayer insulating film and a SiN film is used as a badge-base film, the interlayer insulating film Cover the entire surface of the top with 5iNli, and then apply the top NM on top.
After wiring is formed, S as a badge page 1 film is formed on it
Since an iN film is formed, when a SiN film (SiN film) is formed in the final process during manufacturing, even if the quality of the film is not good on the sidewalls of the upper layer M wiring, it can be applied on the interlayer insulating film. The SiN film, which is pre-formed on the entire surface of the glabella, can prevent local water release from the glabella insulating film and local film shrinkage of the glabella insulating film, which in turn can prevent the upper layer M.
The occurrence of M voids on the wiring can be prevented. Therefore, a highly reliable M multilayer wiring structure can be obtained.
第１図はこの発明の半導体素子のＭ多層配線構造の一実
施例を示す断面図、第２図はＭボイドを説明するための
斜視図、第３図はＭボイドの発生理由を説明するための
断面図である。
２１・・・下地層、２２・・・第１層Ｍ配線、２３・・
・常圧ＣＶＤ系絶縁膜、２４ ・・・プラズマＣＶＤ５
ｉＮｔｌ！、２５・・・第２層Ｍ配線、２６・・・プラ
ズマＣＶＤ５ｉＮ膜。
２５η噌１引配班
本舒咽の一艮嚢屑ｌ
第
図FIG. 1 is a cross-sectional view showing an embodiment of the M multilayer wiring structure of a semiconductor device of the present invention, FIG. 2 is a perspective view for explaining M voids, and FIG. 3 is for explaining the reason for the occurrence of M voids. FIG. 21... Base layer, 22... First layer M wiring, 23...
・Atmospheric pressure CVD insulating film, 24...Plasma CVD5
iNtl! , 25... Second layer M wiring, 26... Plasma CVD5iN film. 25η 1 delivery group, 1 bag of sacs, 1 diagram.
Claims (1)
の下層Ａｌ配線上に形成された層間絶縁膜としての常圧
ＣＶＤ系絶縁膜と、 （ｃ）この常圧ＣＶＤ系絶縁膜上の全面に形成されたＳ
ｉＮ膜と、 （ｄ）このＳｉＮ膜上に形成された上層Ａｌ配線と、（
ｅ）この上層Ａｌ配線上に形成されたパッシベーション
膜としてのＳｉＮ膜とを具備してなる半導体素子のＡｌ
多層配線構造。[Claims] (a) a lower layer Al wiring formed on the base layer; (b) a normal pressure CVD insulating film as an interlayer insulation film formed on the lower layer Al wiring; (c) this S formed on the entire surface of the atmospheric pressure CVD insulating film
iN film, (d) upper layer Al wiring formed on this SiN film, (
e) Al of a semiconductor element comprising a SiN film as a passivation film formed on this upper layer Al wiring.
Multilayer wiring structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21868289A JP2820281B2 (en) | 1989-08-28 | 1989-08-28 | A1 Multilayer wiring structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21868289A JP2820281B2 (en) | 1989-08-28 | 1989-08-28 | A1 Multilayer wiring structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0383340A true JPH0383340A (en) | 1991-04-09 |
| JP2820281B2 JP2820281B2 (en) | 1998-11-05 |
Family
ID=16723768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21868289A Expired - Lifetime JP2820281B2 (en) | 1989-08-28 | 1989-08-28 | A1 Multilayer wiring structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2820281B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009523962A (en) * | 2006-01-23 | 2009-06-25 | ロータス カーズ リミテッド | Two-cycle internal combustion engine with variable compression ratio and exhaust port shutter |
| US9929042B2 (en) | 2015-06-16 | 2018-03-27 | Renesas Electronics Corporation | Semiconductor device having a discontinued part between a first insulating film and a second insulating film |
-
1989
- 1989-08-28 JP JP21868289A patent/JP2820281B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009523962A (en) * | 2006-01-23 | 2009-06-25 | ロータス カーズ リミテッド | Two-cycle internal combustion engine with variable compression ratio and exhaust port shutter |
| US8225754B2 (en) | 2006-01-23 | 2012-07-24 | Lotus Cars Limited | Two-stroke internal combustion engine with variable compression ration and an exhaust port shutter |
| US9929042B2 (en) | 2015-06-16 | 2018-03-27 | Renesas Electronics Corporation | Semiconductor device having a discontinued part between a first insulating film and a second insulating film |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2820281B2 (en) | 1998-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5470793A (en) | Method of via formation for the multilevel interconnect integrated circuits | |
| JPH08501904A (en) | Chip interconnect with breathable etch stop layer | |
| US5716888A (en) | Stress released VLSI structure by void formation | |
| JPH0383340A (en) | Al multilayer interconnection structure of semiconductor element | |
| JPH04127454A (en) | Semiconductor device | |
| KR100477821B1 (en) | Metal wiring formation method of semiconductor device | |
| JPH02186634A (en) | Manufacture of integrated circuit device | |
| JPH065544A (en) | Manufacture of semiconductor device | |
| JPS63164344A (en) | Semiconductor device | |
| JPH04196251A (en) | Semiconductor device | |
| JPH10233395A (en) | Wiring of semiconductor device and its manufacture | |
| JPS5966125A (en) | Manufacture of semiconductor device | |
| JPH03268425A (en) | Manufacture of semiconductor device | |
| JPS63289935A (en) | Manufacturing method of semiconductor device | |
| JPH0691079B2 (en) | Method for manufacturing semiconductor device | |
| JPH07176531A (en) | Wiring structure and forming method thereof | |
| JPS641056B2 (en) | ||
| JPH02117154A (en) | Manufacture of semiconductor device | |
| JPS60180143A (en) | Semiconductor device | |
| JPH0324729A (en) | Manufacture of semiconductor device | |
| JPS60142544A (en) | Manufacture of semiconductor device | |
| JPH11214513A (en) | Wiring structure of integrated circuit, and wiring formation method | |
| JPS62291948A (en) | Metal thin film miring and manufacture thereof | |
| JPH04348054A (en) | Manufacture of semiconductor device | |
| JPS63111644A (en) | Manufacture of semiconductor device |