JPS60142544A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent generation of an unsatisfactory short-circuit between the upper and the lower wirings by a method wherein the surface of the lower metal wiring is plasma-oxidized. CONSTITUTION:An SiO2 film is coated on the Si substrate 1 whereon each element is formed, and lower Al wirings 3a and 3b are formed. A highly densed Al2O3 films 7a and 7b are formed by performing a plasma oxidation on the surface of the lower Al wirings 3a and 3b. An SiO2 film 4 is formed as an interlayer insulating film. A through hole 5 is provided, and the surface of the lower layer Al wiring 3b is exposed. An Al layer is vapor-deposited, and an upper layer Al wiring 6 is formed. A sintering is performed as a heat treatment, and the contact resistance between the lower layer Al wiring 3b and the upper wiring 6 is reduced. Pertaining to the Al2O3 films 7a and 7b, the generation of Al hillock of the lower Al wiring 7a can be suppressed when final sintering is performed, thereby enabling to prevent the generation of an unsatisfactory short- circuit between the lower Al wiring 3a and the upper layer Al wiring 6.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device (hereinafter referred to as XG), particularly a high-density XG having multilayer wiring.

Conventional configuration and its problems In recent years, ICs are becoming increasingly highly integrated.

Efforts are being made to miniaturize and increase the density of elements and wiring, and to increase the number of layers of wiring. In particular, even if the fine wiring is multi-layered, -IC
It is desired to develop a manufacturing method for multilayer interconnection that improves the yield without reducing the reliability of 0 The conventional method for manufacturing multilayer interconnection will be explained using FIG. 1 0 In FIG. 1, 21 is Si substrate.

2 is the 5io2 film - 3a and 3b are the lower layers)ll wiring.

4 is a G V D-8i02 film, and 6 is a through hole for connection.

6 is an upper layer An wiring. First, a 5i02 film 2 is coated on a Si substrate 1 on which each element has already been formed.

After the A4 layer is deposited on the Si substrate 1, predetermined lower layer interconnections 3a and sbl are formed using photoetching technology (FIG. 1). Then - cvn method or plasma C
A SiO2 film 4 is formed to cover the Si base@1 by the VD method. However, as the wiring becomes finer due to the higher density of ±C, the lower layer jJ wires 3a and 3b become wires with a larger aspect ratio, and the steps of the 8102 film 4 at the stepped portions of the lower layer jJ wires 3a and 3b are inevitably reduced. Kabarekji (
(hereinafter referred to as coverage) and film quality deteriorates (Fig. 1 B).
). Then, a predetermined through hole 6 for connection with the lower layer A7J wiring 3b is opened in the 5i02 film 4 using photoetching technology (FIG. 1C). Next, add A4 to this 81Ki 1
After depositing the Zh layer, a predetermined upper layer jJ wiring 6 is formed using photoetching technology (FIG. 1D). Then, in order to reduce the contact resistance between the lower layer i wiring 3b and the upper layer A4 wiring 6 in the connection through hole 6, this Si substrate 1 is subjected to so-called sintering as a heat treatment, and the IC is completed (FIG. 1E).

In ICs manufactured in this way, +
The reaction between the 5i02 film 4 and the lower layer Al wirings 3a and 3b (not shown), especially the deterioration of the coverage and film quality of the 5i02 film 4 at the stepped portion of the lower layer aluminum wiring 3a, leads to The leakage current increases and the interlayer breakdown voltage of the +5i02 film 4 deteriorates.

Also, as shown in Figure 1 α), during the final sintering, hillocks (protrusions) were formed on the surface of the lower layer JJ wiring 3a.
a occurs, resulting in an interlayer short-circuit between the lower layer A/wiring 3a and the upper layer jJ wiring 6.

As described above, the conventional methods have the above-mentioned problems and are difficult to apply to high-density ICs.

Purpose of the Invention In view of the above conventional problems, the present invention prevents deterioration of interlayer breakdown voltage of one interlayer insulating film and short-circuit defects between lower layer wiring and upper layer wiring in ICs equipped with multilayer wiring, and improves fine wiring. SUMMARY OF THE INVENTION The present invention provides a process of forming a lower metal wiring on a semiconductor substrate, and plasma oxidizing the surface of the lower metal wiring. A high-density IC is fabricated using the following steps: forming an interlayer insulating film on this substrate, forming connection through holes in the glabellar insulating film, and further forming upper layer metal wiring.
It is something that makes it possible to manufacture.

DESCRIPTION OF EMBODIMENTS One embodiment i+lJ of the present invention will be described with reference to FIG. In Fig. 2, the same components as in Fig. 1 are given the same numbers, 1 is the Si substrate, 2 is the 5I02 film-3a and 3b are the lower layer JJ wiring, 4 is the CVN-5IO2 film, and 6 is the connection through hole. , 6 is the upper layer AI wiring, 7a and 7
b is a 11205 film. An 8102 film 2 is coated on an 81 substrate 1 on which capacitive elements (not shown) have already been formed, and A/ (aluminum) is deposited as a lower layer wiring on this Si substrate 1 by sputtering. After depositing the layers, photoetching techniques are used to remove the predetermined lower J wiring 3a and sbi
form (figure 2 person). Then, this 81-base machine 1 was heated in an oxygen atmosphere and at a temperature of about 100 to 300 below the melting point of A/.
Plasma treatment at low temperature of °C.

The surfaces of the lower layer interconnections 3a and 3b are coated with dense k120s (alumina) films 7a and 7b at a low temperature by plasma oxidation (FIG. 2B). and.

A Si5io2 film 4 is formed as an interlayer insulating film on this Si substrate 1 by plasma CVD or CVD. Here, as in the conventional case, since the lower layer uneven wirings 3a and 3b have a large aspect ratio, the coverage and film quality of the 5i02 film 4 at the step portion thereof are deteriorated (FIG. 2C).

Next, a predetermined through water hole 6 for connection to the lower layer AIl wiring 3b is opened in the 5i02 film 4 using a photoetching technique (FIG. 2D). Then, this Si substrate 1 is sputter-etched in an argon atmosphere to form a lower layer Al wiring 3.
The opening portion of the connection through hole 6 of the mu β205 film 7b coated on the surface of the through hole 6 is removed.
Expose the lower layer A7J wiring sbi in the opening (Fig. 2E)
). Thereafter, an A1 layer containing upper layer wiring is deposited on this Si substrate 1 by a sputtering method, and then a predetermined lower layer A7 wiring 6 is formed using a photoetching technique. Then, the lower layer kl wiring 3b and the upper layer wiring 6 at the connection through hole 6
This Sia! The IC of this embodiment is completed by applying so-called sintering to the plate 1 as a heat treatment (FIG. 2F).

In the multilayer wiring of the IC manufactured in this way, the structure shown in Fig. 2 (F
), the surfaces of the lower layer Al wirings 3a and 3b are coated with dense 11203 films 7a and 7b, so during the final sintering.

5102 membrane 4 and lower layer AI! The reaction with the wirings 3a and 3b can be prevented, and -5 at the stepped portion of the lower layer A7 wiring 3a.
Even if the coverage and film quality of i0211$4 deteriorate, it is practically Ajl! Since it has a two-layer structure with the 2o3 film 7a, the interlayer leakage current does not increase and deterioration of the interlayer breakdown voltage of the 18102 film 4 can be prevented. Furthermore, lower layer AI! A7!2o3 films 7a and 7b on the surfaces of wirings 3a and 3b
This is because the coating is formed at low temperatures.

During the final sintering, Al on the surface of the lower layer A4 wiring 7a is removed.
The occurrence of hillocks can be suppressed, and interlayer short-circuit defects between the lower layer 1 wiring 3a and the upper layer A7 wiring 6 can be prevented.

Note that in this embodiment, the 11205 films 7a and 7b were formed by a plasma oxidation method.

This may be formed by other low temperature oxidation methods such as plasma anodization. Also, the interlayer insulating film is 510211ii!
4, but it goes without saying that this effect can also be obtained with a single film such as psGll or Si3N4 film.

Effects of the Invention By forming a 1205 film by Zuma oxidation at a low temperature, this Az2O3 film prevents the reaction between the interlayer insulating film and the lower layer JJ wiring, thereby preventing deterioration of the interlayer breakdown voltage of the single-layer isolation film. .In addition, the 11203 film is used for JJ of the lower layer AA wiring.
Since it suppresses the occurrence of hillocks, it has the effect of preventing interlayer failures between the lower layer A4 wiring and the upper layer uneven wiring, so it is possible to realize a high density of fine wiring in an IC with two multilayer wiring. .

[Brief explanation of drawings]

Figures 1) to (E) are schematic cross-sectional views of the manufacturing process of a conventional IC, and Figures 2) to (F) are schematic cross-sectional views of the manufacturing process of an IC according to an embodiment of the present invention. 1...Semiconductor substrate, 32L and 3b...
...Lower layer A7 wiring, 4...Interlayer insulating film, 5...
...Through hole for connection, 6...Upper layer A/wiring-7a and 7b...A71203 film.

Claims (4)

[Claims] (1) A step of forming a lower metal wiring on a semiconductor substrate, a step of oxidizing the surface of the lower metal wiring at a low temperature, a step of providing an interlayer insulating film on the semiconductor substrate and the lower metal wiring, and a step of forming an interlayer insulating film on the semiconductor substrate and the lower metal wiring; A method for manufacturing a semiconductor device 0 characterized by including the steps of: opening a connection through hole in an insulating film; and forming an upper layer metal wiring on the interlayer insulating film. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the metal wiring is made of aluminum or an aluminum alloy. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the low-temperature oxidation of the surface of the metal wiring uses a plasma oxidation method. (4) The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is made of a silicon oxide film formed by a CVD method or a plasma oxidation method.