JPS599964A - Formation of electrode and wiring of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a TiW layer from reducing in width, and to prevent wirings from peeling off by a method wherein the TiW thin layer, an Al wiring layer, the TiW thin layer are stacked to form an Al-TiW alloy layer, and selective etching is performed by applying a resist mask. CONSTITUTION:A window is opened in an SiO2 film 2 as usual, the TiW thin film 3 to come in contact with a diffusion layer, the Al layer 4, the TiW thin film 5 are stacked, and the Al layer is sintered to form the Al-TiW alloy layer 8 at the interface. The Al layer 4 and the alloy layer 8 are etched using the resists 6a-6c as the mask, the TiW film 3 is etched according to plasma etching of Freon in succession, and the resists are removed. According to this method, side etching to be generated when the TiW thin layer 3c to constitute the especially narrow width wirings is to be formed can be suppressed, while the layer 3c can be prevented from formation in narrow width, and peeling off of the Al wiring layer 4c can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming electrodes and interconnections of a semiconductor device.

In semiconductor integrated circuit devices (ICs), silicon (S
l) Transistor, dimate, resistor, on the main surface of the board.
Elements such as capacitors are formed and these elements are interconnected with a metal layer made of a patent characterized by aluminum (At) i or A/.

In recent years, there has been an increasing demand for high-density integration of ICs.
As the number of elements in the circuit increases and the circuit configuration becomes more complex, the wiring method has become a major problem. If a single-layer wiring method is used, the chip size of the IC will increase by one inch, which will become a major obstacle in terms of manufacturing yield and manufacturing cost. To avoid this, it is necessary to use a multilayer wiring system.

When using a multilayer wiring system, an At wiring layer is usually used, but when the first At wiring layer is formed by selective etching and then sintered, hillocks occur in the first At wiring layer. These hillocks may cause cracks or pinholes in the interlayer insulating film, resulting in a short circuit at a portion where the first At wiring layer and the second Jlkt wiring layer intersect with each other. Hillocks generated during heat treatment of the At wiring layer are caused by the p,
titanium tungsten (T) on the surface of the wiring layer in advance.
iW) Thin layer or nickel chromium (NiOr) WJ
Layer 'i: Although it can be suppressed by forming it, p
Platinum silicide layer TiW applied to shallow n-junction devices
Regarding the At wiring layer formed simultaneously with the -At structure electrode, there are problems as described below.

Figures 1 (A) to (D) show the conventional platinum wrinkle side - TiW.
-A is a cross-sectional view showing the main stages of the method for forming electrodes and wiring in the structure.

First, as shown in FIG. 1(A), the main surface of an n-type S1 substrate (1) on which a p-type impurity expansion region (1a) and an n-type impurity diffusion region (], b) are selectively formed. A part insulating film (2) is formed on top, and then a p-type impurity diffusion region (1a) is formed.
) and the n-type impurity diffusion region (1b), a window (2a) and a window (zb) for forming an electrode are formed in the portion of the insulating film (2) on each surface by using a well-known photolithography technique.

Next, impurity diffusion regions (l) in windows (2a) and (2,b)
After forming a platinum silicide layer (not shown) from the surfaces of a) and (]-b) to the surface of the insulating film (2), a thin layer is formed on the surface of the platinum silicide layer. (3), then an At layer (4) is formed on the surface of the Tj, W thin layer (3), and further a TiW thin layer (5) is formed on the surface of the At layer (4).

Next, as shown in FIG. 1(B), a TiW thin layer f corresponding to the p-type impurity diffusion region (1a) and the n-type impurity diffusion region (1b) in the window (2a) and window (2b), respectively.
A resist film (6a) and a resist film (6b) for etching masks are selectively formed on the surface of fi+, and a resist film (6b) is formed on the surface of the TiW thin layer (6).
selectively forming a resist film (6C) for an etching mask in required portions other than the forming regions 6a) and (6b);
Next, resist films (6a), (6b), (6c)
Using the mask as a mask, the resist film (6a) of the TiW thin layer (5),
(6b), remove the part other than directly under (6C) to expose the surface of 1/1 layer (4) of this part, and resist film (6a).

(6b), TiW thin N (5a) directly below (6c),
Leave (5b) and (5c). Afterwards, this Ti
AtNl by plasma etching on the W thin layer (6)
Since the exposed surface of layer 4) has changed in quality, this A1 layer (4)
), resist films (6a), (6b),
(6c) is used as a mask to clean the exposed surface of this person (41). Next, as shown in FIG. 1(C), the resist film (6a),
Using (6b) and (6c) as masks, selective etching was performed on the exposed parts of AtNi4) to form a TiW thin layer (5).
Underneath a), an At electrode layer (4a) for forming the electrode of the p-type impurity diffusion region (1a) is left, and a TiW thin layer (5b) is left.
Underneath is At for the electrode structure of the n-type impurity diffusion region (1b).
The electrode layer (4b) is left, and at the same time, the At wiring /* (40) is left under the Tj, W thin layer (5c). Next, the resist films (6a), (6b), (6c) are coated with a TiW thin layer (5
After removing from the surfaces of a), (5b), and (5c), the At% polar layer (4a)
At the interface with the iW thin layer (3) and the TiW thin layer (5a), an At-TiW alloy layer (7a) and an At-TiW alloy layer (8a) are formed, respectively, and an At electrode layer (4b) is formed.
) and the A7-TiW alloy layer (7b) and the At-TiW thin layer (3) and the TiW thin layer (5b).
Form the W alloy layer (8b), and simultaneously form the TiW thin layer (3) and TiW thin layer (5c) of the At wiring layer (4C).
At-TiW alloy layer (7C) and A4-
A TiW alloy layer (8C) is formed respectively. These At-TiW alloy layers ('7a), (7b), (7c
) and At-TiW alloy layers (8a), (8b),
(8c) is AtJfi (4a) during subsequent heat treatment.

It works to suppress hillocks that occur in (4b) and (4c). Next, as shown in FIG. 1(D), A4M (411) was etched by plasma etching using Freon.
, (4b), (4C) except for the lower part of 'I'iW thin layer (3) and TiW thin IVr (5a), (5b), (
5c) are simultaneously removed, and these layers (4a) and
(4b), Tj, W thin layer (3a) under (4c),
(3b).

(3C), the work of this conventional method is completed, and the TiW thin J* (3a) and the At electrode layer (4a)
The electrode of the p-type impurity diffusion region (la) is composed of the At-TiW alloy layer ('7a) and (sa), and the TiW
An electrode of an n-type impurity diffusion region (1b) whose constituent elements are a thin layer (3b), an At electrode layer (4b), an ht-Ttw alloy layer (7b), (sb), and a TiW thin layer (3C).
and At wiring layer (4C) and ht-'r1w alloy layer (zc
), (sc) as constituent elements is obtained.

In this conventional method, the At layers (4a), (4b), (4) are formed without using an etching resist film.
c) TiW thin layer (3) other than the bottom part and TiW thin layer (
5a), (5b), and (50) are simultaneously removed by Freon plasma etching, so TiW*
Jt! Once (5a), (5b), and (5c) are removed, the mask for Freon plasma becomes A
, /S layer (4a), (4b), (4c). In this case, in addition to the thin wiring layer (4C), p is thin, and the TiW thin layer (3
C) becomes thinner than the Al wiring layer (4C) by side etching with Freon plasma, so A,
/- There was a drawback that the wiring layer (4C) peeled off from the surface of the insulating film (2) or became one.

The present invention has been made in view of the above-mentioned drawbacks, and provides a method for forming electrodes and wiring for a semiconductor device in which peeling of a wiring metal layer that is formed at the same time as an electrode for a selective diffusion region of a semiconductor substrate is reduced. The purpose is to provide.

FIGS. 2A to 2D are cross-sectional views showing the main stages of a method for forming electrodes and wiring of a platinum silicide-TiW-At structure according to an embodiment of the present invention.

In the figure, the same reference numerals as those in the conventional example shown in FIG. 1 indicate equivalent parts.

First, as shown in FIG. 2(A), after forming it in a state similar to that of the conventional example shown in FIG. 1(A),
Fi, tf members (4) were sintered, A17 vehicles (4)
TiW thin layer (3) and T1. V/@ layer (At-TiW alloy layer (7) and At-Ti
A W alloy layer (8) is formed respectively. Next, Figure 2 (B
), the T1W# layer (5) is removed from the surface of the AA-T1w alloy layer (8) with hydrogen peroxide solution (H20□) at a temperature of 50 to 80 DEG C., and then sputter etching is performed. Next, the window (2) of the At-TiW alloy layer (8) is
a) and p-type impurity diffusion region (1a) within window (2b)
and a resist film (6a) and a resist film (6a) on the surface of the portion corresponding to the n-type impurity diffusion region (lb)
6b) is selectively formed, and at the same time, a resist film (6C) is selectively formed on the surface of the At-TiW alloy layer (8) from 81 to 81, which is to become a wiring metal layer. Next, the second
As shown in Figure (0), resist films (6a), (6b
), (6C) as a mask, these resist films (6a), (6b), (6c) were etched.
) under At layer (4) and Al-TiW alloy layer i7
1. The parts other than the part (s) are removed from the surface of the TiW thin layer (3), and the p-type impurity diffusion region (1a) '+41.' is formed under the resist film (6a). At layer for pole construction, pole layer (4a) and A4-TiW alloy J@ (7a),
(8a) and under the resist film (6b) is an At electrode layer (4) for forming the electrode of the n-type impurity diffusion region (1b).
b) Leaving the At-TiW alloy layers (Vb), (sb), and at the same time under the resist film (6c) p, ! for At wiring structure. Wiring layer (4c) and A-TiW alloy layer (7c).

Leave (8C). Next, as shown in FIG. 21(D),
Using the resist films (6a), (6b), and (6c) as masks, the TiW thin layer (3) under these resist films (6g, ), (6b), and (6c) was etched by Freon plasma etching. Insulating film (2) for other parts
Ti is removed from the surface of the A, e-TiW alloy layer (7a) for the electrode structure of the p-type impurity diffusion region (la,).
While leaving the W thin layer (3a), Δ? -TiW alloy layer ('
7b), leave a thin TiW ffi (3b) for forming the electrode #r of the n-type impurity diffusion region (cb), and at the same time
A TiW thin layer (3c) for At wiring structure is left under the iw alloy layer (7c). Next, resist films (6a), (6
1)), (60) as At-TiW alloy layer (8a),
Table m in (8b) and (8c); When removed from above, the work of the method of this example is completed. In the method of this example, the TiW thin 7ii# (3c ), At wiring layer (4c)
Since both the At-TiW alloy layers (70) and (8c) are formed by selective etching using the resist film (6c) as a mask, it is possible to suppress side etching when forming the TiW thin layer (3C). So, T
In order to prevent the iW thin layer (3C) from becoming thinner than in the conventional example shown in Fig. 1, the kt wiring Jm (
40) peeling can be reduced.

Although AtNfI (4) was used in this example,
This is not necessarily limited to an At layer, and other alloy layers containing At as a base layer such as an aluminum-silicon alloy layer may also be used. In addition, in this embodiment, both the 'I' iW thin layer (3) and the 'TiW thin layer (5), or any one of these TiW thin layers + 31, (5), the N1Ur'74 layer, etc. The metal layer that can form the alloy layer for suppressing the occurrence of hillocks in the pond also has the effects of this embodiment and N1.

As explained hereinabove, in the electrode of the semiconductor device of the present invention and the JL formation method described in the previous section, the selective diffusion region is formed on the main surface of the semiconductor substrate having the selective diffusion region in the first part. An insulating film provided with a window for electrode formation is formed, and At'! is applied over the surface of the insulating film from the surface of the selective diffusion region within the window. A first metal layer capable of forming an alloy layer 1 for suppressing hillock generation, which suppresses the formation of hillocks in an alloy containing A7-'i or an alloy containing At as a main component, between the alloy containing A7-'i or an alloy containing Al as a main component; A second metal layer made of At''! or an alloy containing At as a main component and a third metal layer capable of forming an alloy layer for suppressing hillock generation similar to the above alloy layer for suppressing hillock generation are sequentially formed. , after heat treating these first, second and third metal layers, removing the third metal layer,
First and second etching masks are formed on the surface of the portion of the second metal layer corresponding to the selective diffusion region within the window and on the surface of the portion that is to become the wiring metal layer, respectively.
The first of these: ? The first and second resist films below the first and second resist films are etched by selective etching using the first and second resist films as masks.
Select each part of the metal layer in the tortoise-marked diffusion region.

Since the electrode and wiring metal layer is used, even if the width of the wiring metal layer is particularly narrow, the first metal layer constituting the wiring metal layer will not become thinner due to side etching during selective etching. This makes it possible to reduce peeling of the wiring metal layer.

[Brief explanation of the drawings] Figures 1 (A) to (D) show conventional platinum silicide-TiW
FIGS. 2A to 2D are cross-sectional views showing the main stages of the method for forming electrodes and interconnects with a -At structure. FIGS. FIG. 3 is a cross-sectional view showing the main stages of the forming method. In the figure, (1) is 81 substrates, (la) and (1b
) are p-type impurity diffusion region and n-type impurity diffusion region (selective diffusion region), (2) is an insulating film, (2a) and (2b) are windows, and (3) is a TiW thin layer (first metal layer). )
, (4) is an At layer (second metal layer), (4a) and (
4C) is an At electrode layer, (4C) is an HT wiring layer, (5) is a TiW thin layer (third metal layer), (6a) and (6b)
(6C) is a resist film (first resist film), and (6C) is a resist film (second resist film). Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - (1 other person) Figure 1 Procedural Amendment (Voluntary) 9, Blasphemy 1, 1'f'l Indication 11゛Gan-Sho 57-119
363 No. 3, Relationship with Toma 1 Juru 1 which does i+li+l・119 Author 5, Detailed description of the invention column and Brief description of drawings column 6 of the specification subject to amendment, Contents of the amendment (1 ) On page 4, lines 14 to 17 of the specification, it says "Next, TiW thin N (3) is formed in the windows (2a) and (2b)," [ Next, windows (2a), (2b
After forming a platinum silicide layer (not shown) on the platinum silicide layer, a TiW thin layer (3) is formed from the platinum silicide layer to the surface of the insulating film (2).'' (2) Ibid., page 5, lines 16 to 17, [this At layer (
4)-----Resist film (6a), (6b), (6
c) was used as a mask.''
. After removing (6b) and (6c).'' (3) Same, page 5, line 20 [Resist film (6a). (6b), (ac) J is a thin TiW layer (5
a), (5b). (bc) Correct it as J. (4) ``Resist film (
6al, (6b), (6Q) --- After removing one, the phrase "" is deleted. (5) Similarly, on page 13, line 16, replace J(ac)J with 1(+b)J. that's all

Claims (1)

[Claims] +1) A first step of forming an insulating film on the main surface of the semiconductor substrate in which a selective diffusion region is formed on the main surface, forming a window on the surface of the selective diffusion region of the insulating film, and forming a window on the surface of the selective diffusion region. a second step of exposing a required portion of the surface of the selective diffusion region within the window, between the surface of the selective diffusion region within the window and the surface of the insulating film with aluminum or an aluminum-based alloy; a third step of forming a first metal layer capable of forming a hillock generation suppressing alloy layer for suppressing hillock formation in the aluminum or an alloy containing aluminum as a main component, on the surface of the first metal layer; a fourth step of forming a second metal layer made of aluminum or an alloy containing aluminum as a main component; a hillock generation suppressing alloy similar to the hillock generation suppressing alloy layer on the surface of the second metal layer; Formable third layer
a fifth step of forming the metal layer of step 1 above; a sixth step of removing the third metal layer after heat treating the second and third metal layers, on the surface of the portion of the second metal layer corresponding to the selective diffusion region within the window; A seventh step of selectively forming first and second resist films for etching masks on the surface of the portion to become the wiring metal layer, and using the first and second resist films as masks. By selective etching, the first and second
A method for forming electrodes and interconnects in a semiconductor device, comprising an eighth step of forming portions of the first and second metal layers under the resist film as electrodes and interconnect metal layers for the selective diffusion region, respectively.