JPS6350042A - Multilayer interconnection and electrode film structure - Google Patents
Multilayer interconnection and electrode film structureInfo
- Publication number
- JPS6350042A JPS6350042A JP19422786A JP19422786A JPS6350042A JP S6350042 A JPS6350042 A JP S6350042A JP 19422786 A JP19422786 A JP 19422786A JP 19422786 A JP19422786 A JP 19422786A JP S6350042 A JPS6350042 A JP S6350042A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- wiring
- layer
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 39
- 239000011229 interlayer Substances 0.000 claims description 12
- 239000010410 layer Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 16
- 239000000126 substance Substances 0.000 abstract description 11
- 238000010438 heat treatment Methods 0.000 abstract description 9
- 230000001590 oxidative effect Effects 0.000 abstract description 8
- 238000005260 corrosion Methods 0.000 abstract description 7
- 230000007797 corrosion Effects 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910008479 TiSi2 Inorganic materials 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体集積回路装置などにおける多層配線
Φ電極膜構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer wiring Φ electrode film structure in a semiconductor integrated circuit device or the like.
従来例でのこの種の半導体装置として、こ＼でて、１９
７９年のＩＥＥＥ（Ｔｈｅ Ｉｎ５ｔｉｔｕｔｅ ｏｆ
Ｅｌｅｃｔｒｉｃａｌａｎｄ Ｅｌｅｃｔｒｏｎｉｃ
ｓ Ｅｎｇｉｎｅｅｒｓ） Ｖｏｌ、ＥＩ］−２Ｂ Ｐ
２Ｏ３に発表されたポリサイド構造を有する半導体装置
の製造フローを第２図（ａ）ないしくｆ）に示す。As a conventional example of this type of semiconductor device, there are 19
1979 IEEE
Electricaland Electronic
s Engineers) Vol, EI]-2B P
The manufacturing flow of a semiconductor device having a polycide structure published in 2003 is shown in FIGS. 2(a) to 2(f).
すなわち、これらの第２図において、まず、例えばシリ
コン半導体基板１上には、例えば熱酸化膜などの絶縁膜
２を形成させ（同図（ａ））、その上にＣＶＤ法などに
よって多結晶シリコン膜３を形成させ、かつ場合によっ
ては、リンなどの不純物をドープする（同図（ｂ））。That is, in these FIGS. 2, first, for example, an insulating film 2 such as a thermal oxide film is formed on a silicon semiconductor substrate 1 (FIG. 2(a)), and then polycrystalline silicon is deposited thereon by CVD or the like. A film 3 is formed and, depending on the case, doped with an impurity such as phosphorus (FIG. 3(b)).
ついで、その上にスパッタリング法、ＣＶＤ法などによ
って、下層となる金属膜４を形成させ（同図（Ｃ））、
また、写真製版とエツチング法などを用いて、これらの
金属膜４と多結晶シリコン膜３．そして必要に応じては
、絶縁膜２を順次選択的にエツチング除去する（同図（
ｄ））。Next, a metal film 4 as a lower layer is formed thereon by a sputtering method, a CVD method, etc. (FIG. 4(C)).
Furthermore, these metal films 4 and polycrystalline silicon films 3. Then, if necessary, the insulating film 2 is sequentially and selectively etched away (see Fig.
d)).
その後、一般的に金属膜４の抵抗値を、その物質の固有
抵抗値に近付けるために、１０００℃に近い温度で熱処
理をなしたのち、この金属膜４を含む上部に、層間での
電気的絶縁を意図して、 ＣＶＤ法などにより酸化シリ
コンなどの層間絶縁膜６を形成する（同図（ｅ））。After that, in order to bring the resistance value of the metal film 4 closer to the specific resistance value of the material, heat treatment is generally performed at a temperature close to 1000°C, and then the upper part including the metal film 4 is For insulation purposes, an interlayer insulating film 6 made of silicon oxide or the like is formed by CVD or the like (FIG. 4(e)).
最後に、写真製版とエツチング法などにより、層間絶縁
膜６の所望部分にコンタクト穴７を開孔した上で、さら
に、スパッタリング法、ＣＶＤ法などによって、この層
間絶縁膜６上に上層となる配線膜８を形成させ、コンタ
クト穴７を通して、この」二層の配線膜８を下層の金属
膜４に電気的に接続させるのである（同図（ｆ））。Finally, contact holes 7 are formed in desired portions of the interlayer insulating film 6 by photolithography and etching, and then upper layer wiring is formed on the interlayer insulating film 6 by sputtering, CVD, etc. A film 8 is formed, and this two-layer wiring film 8 is electrically connected to the underlying metal film 4 through the contact hole 7 (FIG. 4(f)).
しかして、このような従来例による多層配線・電極膜構
造、こ−ではポリサイド構造の場合、最−に層の導体膜
が金属膜であって、これが化学的耐蝕性とか酸化処理に
対する安定性に劣るときは、その製造時に次のような困
難さが伴なうことになる。However, in the case of such a conventional multilayer wiring/electrode film structure, in this case a polycide structure, the conductor film of the first layer is a metal film, which has poor chemical corrosion resistance and stability against oxidation treatment. If it is inferior, the following difficulties will be encountered during manufacturing.
すなわち９例えば熱処理に際しては、基板表面の汚染物
質を除去するために熱酸化雰囲気中で前処理を行なうが
、このとき、酪に対する耐蝕性がなければ、その処理中
に金属膜４がエツチング除去されるか、あるいは第３図
（ａ）に示すように膜厚が減少され、その配線抵抗が所
期の期待される抵抗値よりも高い値となって、素子特性
に影響する。For example, in heat treatment, pretreatment is performed in a thermal oxidation atmosphere to remove contaminants from the surface of the substrate, but at this time, if the metal film 4 is not resistant to corrosion, the metal film 4 may be etched away during the treatment. Or, as shown in FIG. 3(a), the film thickness is reduced, and the wiring resistance becomes higher than the expected resistance value, which affects the device characteristics.
また、前記熱酸以外にも、通常、フッ酸系薬品を用いた
Ｓ ＋ ０２のエツチングを行なうが、例えばコンタク
ト穴７の開孔時、またはその後の配線膜８を形成するま
でにフッ酸系薬品中に入れた場合。In addition to the above-mentioned hot acid, S + 02 etching is usually performed using a hydrofluoric acid-based chemical. When placed in medicine.
金属膜４の種類によっては、コンタクト穴７を通して金
属膜４が、例えば第３図（ｂ）に見られるようにエツチ
ングされ、その程度が著るしいと、サイドエツチングが
進行する結果、同様に配線抵抗に影響を与える惧れが生
ずる。Depending on the type of metal film 4, the metal film 4 may be etched through the contact hole 7, as shown in FIG. There is a risk that this will affect resistance.
さらに、酸化処理に対する安定性についても、例えば金
属膜４が、チタンとシリコンの合金であるチタンシリサ
イド（ＴｉＳ＋２）の場合にあっては、９００〜１００
０℃程度の温度で酸化処理すると、そのＴｉＳｉ２が分
解せずに表面にＳ ＋ ０２が形成されることになる。Furthermore, regarding the stability against oxidation treatment, for example, when the metal film 4 is made of titanium silicide (TiS+2), which is an alloy of titanium and silicon, the stability against oxidation treatment is 900 to 100.
When the oxidation treatment is performed at a temperature of about 0° C., S + 02 is formed on the surface without decomposing the TiSi2.
そしてこの場合、Ｓ ｉＯ２の形成にあずかるＳｉは、
ＴｉＳｉ２の下の多結晶シリコン膜３からの拡散によっ
て供給されるが、このとき、Ｓｉの拡散供給能力が低下
するような低温領域９例えば８００℃以下で酸化させる
と、ＴｉＳｉ２が分解して、Ｔｉの酸化層が形成される
ために、多層配線膜の抵抗上昇を招くことになる。In this case, the Si that participates in the formation of SiO2 is
It is supplied by diffusion from the polycrystalline silicon film 3 under TiSi2. At this time, if it is oxidized at a low temperature region 9, for example, below 800°C, where the Si diffusion supply ability is reduced, TiSi2 decomposes and Ti Since an oxide layer is formed, the resistance of the multilayer wiring film increases.
このように従来例での多層配線・電極膜構造においては
、酸化性雰囲気中での熱処理時に、金属膜が酸化され、
酸化物を生じて配線膜の抵抗が増したり、あるいはフッ
酸などの薬品処理時に、金属膜がエツチングされたりす
ると云う問題点があった。In this way, in the conventional multilayer wiring/electrode film structure, the metal film is oxidized during heat treatment in an oxidizing atmosphere.
There are problems in that the resistance of the wiring film increases due to the formation of oxides, or that the metal film is etched during treatment with chemicals such as hydrofluoric acid.
この発明は従来のこのような問題点を解消するためにな
されたものであり、その目的とするところは、酸化性雰
囲気中での熱処理時に、配線膜の抵抗を損なう惧れがな
く、また、フッ酸などの薬品に対する耐蝕性に優れた。This invention was made to solve these conventional problems, and its purpose is to eliminate the possibility of damaging the resistance of the wiring film during heat treatment in an oxidizing atmosphere, and to Excellent corrosion resistance against chemicals such as hydrofluoric acid.
この種の多層配線・電極膜構造を得ることである。The aim is to obtain this kind of multilayer wiring/electrode film structure.
前記目的を達成するために、この発明に係る多層配線・
電極膜構造は、下層の金属膜上に多結晶シリコン膜を形
成させ、この多結晶シリコン膜を介して、金属膜に上層
の配線膜を接続させたものである。In order to achieve the above object, the multilayer wiring and
The electrode film structure is such that a polycrystalline silicon film is formed on a lower metal film, and an upper wiring film is connected to the metal film via this polycrystalline silicon film.
すなわち、この発明では、下層の金属膜上に形成された
多結晶シリコン膜が、酸化性雰囲気中での熱処理時には
、金属酸化物形成の防１Ｆ膜として作用し、また、フッ
酸などの薬品による処理中での、金属膜のエツチングに
対する保護膜として作用する。That is, in this invention, the polycrystalline silicon film formed on the underlying metal film acts as a 1F film to prevent metal oxide formation during heat treatment in an oxidizing atmosphere, and also acts as a 1F film to prevent the formation of metal oxides due to chemicals such as hydrofluoric acid. It acts as a protective layer against etching of the metal film during processing.
以下、この発明に係る多層配線・電極膜構造の一実施例
につき、第１図（ａ）ないしくｆ）を参照して詳細に説
明する。Hereinafter, one embodiment of the multilayer wiring/electrode film structure according to the present invention will be described in detail with reference to FIGS. 1(a) to 1(f).
これらの第１図（ａ）ないしくｆ）はこの実施例構造の
概要を製造工程順に示すそれぞれ断面図であり、前記第
２図従来例と同一符号は同一または相当部分を表わして
いる。These FIGS. 1(a) to 1(f) are sectional views showing the outline of the structure of this embodiment in the order of manufacturing steps, and the same reference numerals as in the conventional example shown in FIG. 2 represent the same or corresponding parts.
第１図（ａ）ないしくｃ）までの工程は前記従来例の場
合と同様であり、その後、前記下層の金属膜４」−にス
パッタリング法、ＣＶＤ法などによって、後述する金属
酸化物形成の防止膜、およびエツチングに対する保護膜
としての多結晶シリコン膜５を形成する（同図（ｄ））
が、こへでこの多結晶シリコン膜５には、熱拡散または
イオン注入法などによって、リン、砒素、ボロンなどの
不純物を添加しても良い。The steps up to FIG. 1(a) to c) are the same as in the conventional example, and then a metal oxide is formed on the lower metal film 4'' by sputtering, CVD, etc., as described later. A polycrystalline silicon film 5 is formed as a preventive film and a protective film against etching (FIG. 4(d)).
However, impurities such as phosphorus, arsenic, and boron may be added to this polycrystalline silicon film 5 by thermal diffusion or ion implantation.
続いて、写真製版とエツチング法などを用い、これらの
多結晶シリコン膜５．金属膜４．多結晶シリコン膜３．
そして必要に応じては、絶縁膜２を順次選択的にエツチ
ング除去しく同図（ｅ））、さらに、層間絶縁膜６を形
成した」二で、前記と同様に写真製版とエツチング法な
どにより、層間絶縁膜６の所望部分にコンタクト穴７を
開孔させ、かつスパッタリング法、ｃｖｎ法などにより
、上層の配線膜８を形成させて、多結晶シリコン膜５．
ひいては下層の金属膜４との電気的接続をとるのである
（同図（ｆ））。Subsequently, using photolithography and etching methods, these polycrystalline silicon films 5. Metal film 4. Polycrystalline silicon film 3.
Then, if necessary, the insulating film 2 was sequentially and selectively etched away (FIG. 2(e)), and an interlayer insulating film 6 was further formed. A contact hole 7 is opened in a desired portion of the interlayer insulating film 6, and an upper wiring film 8 is formed by a sputtering method, a CVN method, etc., and a polycrystalline silicon film 5.
As a result, electrical connection is established with the underlying metal film 4 (FIG. 4(f)).
すなわち、この実施例構造での要点は、下層の金属膜４
上にあって、さらに多結晶シリコン膜５を形成させ、か
つこの多結晶シリコン膜５を介して、同金属膜４に」−
層の配線膜８を接続させることである。That is, the main point in this embodiment structure is that the lower metal film 4
Further, a polycrystalline silicon film 5 is formed on the metal film 4, and a polycrystalline silicon film 5 is formed on the same metal film 4 through this polycrystalline silicon film 5.
This is to connect the wiring films 8 of the layers.
従って、この実施例構造の場合、前記従来例構造で問題
となっていた。酸化性雰囲気中での熱処理に関しては、
直接９表面に露出される多結晶シリコン膜５が酸化に寄
与するために、下層の金属膜４を安定的に保持できる。Therefore, in the case of the structure of this embodiment, there was a problem with the conventional structure. Regarding heat treatment in an oxidizing atmosphere,
Since the polycrystalline silicon film 5 directly exposed on the surface 9 contributes to oxidation, the underlying metal film 4 can be stably held.
また、耐蝕性に関して多結晶シリコン膜５は、酸系薬品
のうち、フッ酸と硝酸の混合液に溶けることを除き、通
常でのＬＳＩプロセスで使用する範囲の同種薬品に対し
て不溶であり、下層の金属膜４の保護膜として十分に作
用する。こ＼で前記下層の金属膜４については、その側
面が保護されていないが、膜厚に比較して膜幅が十分に
大きいために、長時間に亘る薬品処理をなさずに、パラ
メータの最適化を図ることで、膜幅の減少を問題のない
程度の範囲に抑え得るのである。Regarding corrosion resistance, the polycrystalline silicon film 5 is insoluble in the same kind of acid-based chemicals that are used in normal LSI processes, except for the one that is soluble in a mixture of hydrofluoric acid and nitric acid. It sufficiently acts as a protective film for the underlying metal film 4. Although the side surfaces of the lower metal film 4 are not protected, the film width is sufficiently large compared to the film thickness, so the parameters can be optimized without long-term chemical treatment. By achieving this, it is possible to suppress the reduction in film width to a non-problematic range.
なお、前記実施例においては、」二部側から多結晶シリ
コン膜、金属膜、多結晶シリコン膜の３層構造について
述べたが、最下部の多結晶シリコン膜のない２層構造に
も適用でき、また、基板１上にこの多層配！！ｅ電極膜
構造を直接形成する場合にも同様の作用、効果が得られ
る。そしてまた、こ〜では配線として述べたが、例えば
ゲート電極膜とした場合も全く同様である。In the above embodiments, a three-layer structure consisting of a polycrystalline silicon film, a metal film, and a polycrystalline silicon film was described from the second part side, but the present invention can also be applied to a two-layer structure without the bottom polycrystalline silicon film. , Also, this multilayer arrangement on the board 1! ! Similar actions and effects can be obtained when the e-electrode film structure is directly formed. Further, although the wiring has been described here, the same applies to the case of using a gate electrode film, for example.
以上詳述したように、この発明によるときは、半導体基
板上、または基板面の絶縁膜上に、少なくとも金属膜１
層間絶縁膜、配線膜を、順次選択的に形成する多層配線
・電極膜構造において、下層の金属膜上に多結晶シリコ
ン膜を形成させ、上層の配線膜を層間絶縁膜のコンタク
ト穴から、多結晶シリコン膜を介して、下層の金属膜に
接続させるようにしたので、下層の金属膜」−に形成さ
せた多結晶シリコン膜が、酸化性雰囲気中での熱処理に
際し、金属酸化物形成の防止膜となって、金属膜の抵抗
を損なうような慣れを全く解消でき、また、フッ酸など
の薬品による処理の際には、耐エツチング性保護膜とな
って、この薬品に対する耐蝕性を十分に向上できるもの
で、結果的に、酸化処理、薬品処理などに対し極めて安
定な電極。As described in detail above, according to the present invention, at least one metal film is formed on the semiconductor substrate or on the insulating film on the substrate surface.
In a multilayer wiring/electrode film structure in which an interlayer insulating film and a wiring film are sequentially and selectively formed, a polycrystalline silicon film is formed on a lower metal film, and the upper wiring film is formed through contact holes in the interlayer insulating film. Since it is connected to the underlying metal film through the crystalline silicon film, the polycrystalline silicon film formed on the underlying metal film can prevent the formation of metal oxides during heat treatment in an oxidizing atmosphere. It forms a film that completely eliminates the habit of damaging the resistance of metal films, and when treated with chemicals such as hydrofluoric acid, it becomes an etching-resistant protective film that provides sufficient corrosion resistance against these chemicals. As a result, the electrode is extremely stable against oxidation treatment, chemical treatment, etc.
配線構造が得られるのであり、しかも構造的にも頗る簡
単で容易に実施し得るなどの優れた特長を有するもので
ある。A wiring structure can be obtained, and it has excellent features such as being structurally extremely simple and easy to implement.
第１図（ａ）ないしくｆ）はこの発明に係る多層配線・
電極膜構造の一実施例による概要を製造工程順に示すそ
れぞれ断面図であり、また第２図（ａ）ないしくｆ）は
同」二従来例による多層配線・電極膜構造の概要を製造
工程順に示すそれぞれ断面図、第３図（ａ）および（ｂ
）は同一］二従来例構造の問題点を説明するそれぞれ断
面図である。
ｌ・・・・シリコン半導体基板、２・・・・熱酸化膜な
どの絶縁膜、４・・・・下層の金属膜、５・・・・多結
晶シリコン膜、６・・・・層間絶縁膜、７・・・・コン
タクト穴、８・・・・上層の配線膜。
第１図
（ｄ）
（ｆ）
第２図
（ｂ）
（Ｃ）
（ｄ）
第２図
（ｅ）
（ｆ）
第３図
（Ｑ）
（ｂ）
手続補正書（！％）
う斥ゆ乙跣・霞石１葭糾Ｌ
３、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号名
称 （６０１）三菱電機株式会社代表者志岐守哉
４、代理人
５、補正の対象
（１）明細書の特許請求の範囲の欄
（２）明細書の発明の詳細な説明の欄
６、補正の内容
（１）明細書の特許請求の範囲を別紙のとおり補正する
。
（２）同書２頁１４行の「下層となる」を削除する。
（３）同書３頁１９行の「熱酸化雰囲気中で」を「高温
の酸の中で」と補正する。
（４）同書４頁３行の「減少され、その配線抵抗が所期
の期待される」を「減少し、その配線抵抗が所期の」と
補正する。
以 」−
特許請求の範囲
（１）半導体基板上に直接またはた して、少なくと
も金属膜９層間絶縁膜、配線膜を順次選択的に形成する
多層配線・電極膜構造であって、前記下層の金属膜上に
多結晶シリコン膜を形成させると共に、前記層間絶縁膜
のコンタクト穴から、前記上層の配線膜を、前記多結晶
シリコン膜を介して、下層の金属膜に接続させたことを
特徴とする多層配線・電極膜構造。
（２）多結晶シリコン膜中に、砒素、ボロンなどの不純
物を添加したことを特徴とする特許請求の範囲第１項に
記載の多層配線・電極膜構造。Figures 1(a) to 1f) show the multilayer wiring according to the present invention.
FIGS. 2(a) to 2(f) are cross-sectional views showing an outline of an embodiment of an electrode film structure in the order of manufacturing steps, and FIGS. 3(a) and (b), respectively.
) are the same] are sectional views illustrating the problems of the two conventional structures. l...Silicon semiconductor substrate, 2...Insulating film such as thermal oxide film, 4...Lower metal film, 5...Polycrystalline silicon film, 6...Interlayer insulating film , 7... Contact hole, 8... Upper layer wiring film. Figure 1 (d) (f) Figure 2 (b) (C) (d) Figure 2 (e) (f) Figure 3 (Q) (b) Procedural amendment (!%) Relation to the person making the amendment case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Moriya Shiki 4, representative of Mitsubishi Electric Corporation Agent 5, subject of amendment (1) Claims column of the specification (2) Detailed explanation of the invention column 6 of the specification, contents of amendment (1) Submit the claims of the specification on a separate sheet. Correct accordingly. (2) Delete "become a lower layer" on page 2, line 14 of the same book. (3) "In a thermal oxidizing atmosphere" on page 3, line 19 of the same book is corrected to "in a high-temperature acid." (4) In the same book, page 4, line 3, ``Decreased, and the wiring resistance is the expected value'' is corrected to ``Decreased, and the wiring resistance is the expected value.'' - Claims (1) A multilayer wiring/electrode film structure in which at least nine metal films, an interlayer insulating film, and a wiring film are sequentially and selectively formed directly or on a semiconductor substrate, wherein the lower layer A polycrystalline silicon film is formed on the metal film, and the upper wiring film is connected to the lower metal film through the polycrystalline silicon film through the contact hole of the interlayer insulating film. Multilayer wiring/electrode film structure. (2) The multilayer wiring/electrode film structure according to claim 1, wherein impurities such as arsenic and boron are added to the polycrystalline silicon film.
Claims (2)
膜上に、少なくとも金属膜、層間絶縁膜、配線膜を、順
次選択的に形成する多層配線・電極膜構造であつて、前
記下層の金属膜上に多結晶シリコン膜を形成させると共
に、前記層間絶縁膜のコンタクト穴から、前記上層の配
線膜を、前記多結晶シリコン膜を介して、下層の金属膜
に接続させたことを特徴とする多層配線・電極膜構造。(1) A multilayer wiring/electrode film structure in which at least a metal film, an interlayer insulating film, and a wiring film are sequentially and selectively formed directly on a semiconductor substrate or on an insulating film on the surface of the semiconductor substrate, wherein the lower layer A polycrystalline silicon film is formed on the metal film, and the upper wiring film is connected to the lower metal film through the polycrystalline silicon film through the contact hole of the interlayer insulating film. Multilayer wiring/electrode film structure.
物を添加したことを特徴とする特許請求の範囲第１項に
記載の多層配線・電極膜構造。(2) The multilayer wiring/electrode film structure according to claim 1, wherein impurities such as arsenic and boron are added to the polycrystalline silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19422786A JPS6350042A (en) | 1986-08-19 | 1986-08-19 | Multilayer interconnection and electrode film structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19422786A JPS6350042A (en) | 1986-08-19 | 1986-08-19 | Multilayer interconnection and electrode film structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6350042A true JPS6350042A (en) | 1988-03-02 |
Family
ID=16321072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19422786A Pending JPS6350042A (en) | 1986-08-19 | 1986-08-19 | Multilayer interconnection and electrode film structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6350042A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03200330A (en) * | 1989-12-27 | 1991-09-02 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| US5543362A (en) * | 1995-03-28 | 1996-08-06 | Motorola, Inc. | Process for fabricating refractory-metal silicide layers in a semiconductor device |
| US5661081A (en) * | 1994-09-30 | 1997-08-26 | United Microelectronics Corporation | Method of bonding an aluminum wire to an intergrated circuit bond pad |
| US6187664B1 (en) * | 1995-06-05 | 2001-02-13 | Taiwan Semiconductor Manufacturing Company | Method for forming a barrier metallization layer |
-
1986
- 1986-08-19 JP JP19422786A patent/JPS6350042A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03200330A (en) * | 1989-12-27 | 1991-09-02 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| US5661081A (en) * | 1994-09-30 | 1997-08-26 | United Microelectronics Corporation | Method of bonding an aluminum wire to an intergrated circuit bond pad |
| US5734200A (en) * | 1994-09-30 | 1998-03-31 | United Microelectronics Corporation | Polycide bonding pad structure |
| US5543362A (en) * | 1995-03-28 | 1996-08-06 | Motorola, Inc. | Process for fabricating refractory-metal silicide layers in a semiconductor device |
| US6187664B1 (en) * | 1995-06-05 | 2001-02-13 | Taiwan Semiconductor Manufacturing Company | Method for forming a barrier metallization layer |
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