JPH01123434A - Semiconductor device with wiring layer - Google Patents
Semiconductor device with wiring layerInfo
- Publication number
- JPH01123434A JPH01123434A JP28161887A JP28161887A JPH01123434A JP H01123434 A JPH01123434 A JP H01123434A JP 28161887 A JP28161887 A JP 28161887A JP 28161887 A JP28161887 A JP 28161887A JP H01123434 A JPH01123434 A JP H01123434A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring layer
- semiconductor device
- layer
- insulating wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 9
- 239000004642 Polyimide Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分前］
この発明は、゛配線層を有する半導体装置に関し、特に
大規模集積回路装置（以下、ＬＳＩと称する。DETAILED DESCRIPTION OF THE INVENTION [Before Industrial Use] The present invention relates to a semiconductor device having a wiring layer, and particularly to a large-scale integrated circuit device (hereinafter referred to as LSI).
）における配線、たとえば、接地（アース）ラインや電
源ライン用の配線の構造に関するものである。), for example, the structure of wiring for ground lines and power lines.
［従来の技術］
第２Ａ図は、たとえば、Ｆ、Ｅ、Ｂａｒｂｅｒ他著、”
５ｐｅｃｉａｌ Ａｐｐｌｉｃａｔｉ。[Prior Art] FIG. 2A shows, for example, F. E. Barber et al.
5special Applicati.
ｎ Ｍｅｍｏｒｉｅｓ” １９８５ ＩＥＥＥ
Ｉｎｔｅｒｎａｔｉｏｎａｌ ５ｏｌｉｄ−３ｔａｔ
ｅ Ｃ１ｒｃｕｉｔｓ Ｃｏｎｆｅｒｅｎｃｅ。n Memories” 1985 IEEE
International 5solid-3tat
e C1rcuits Conference.
ｐ４４〜４５，３０２ （写真）において示される拡大
チップ写真で明らかにされている従来のＬＳＩの配線構
造を示す部分平面図、第２Ｂ図は第２Ａ図における■Ｂ
−ｎＢ線に沿った部分断面図である。Figure 2B is a partial plan view showing the wiring structure of a conventional LSI as revealed in the enlarged chip photograph shown in p44-45, 302 (photo).
It is a partial sectional view along the -nB line.
図について、従来の配線の構造について説明する。シリ
コン等の半導体基板１には、簡単化するために図には示
されていないが、トランジスタ、キャパシタ、抵抗等の
回路要素が形成されている。A conventional wiring structure will be explained with reference to the figure. Although not shown in the figure for simplicity, circuit elements such as transistors, capacitors, and resistors are formed on the semiconductor substrate 1 made of silicon or the like.
これらの回路要素の相互間の信号伝達や回路動作に必要
な電流を電源から供給するために、配線を行なう必要が
ある。そこで、配線の下地として絶縁層２が、たとえば
、シリコン酸化膜やシリコン窒化膜で形成される。この
絶縁層２には所定の位置に下地とのコンタクト孔（図示
せず）が開口される。その後こコンタクト孔を通じて下
地に接続するように、アルミニウム合金（Ａｌｌ−８ｉ
合金。Wiring is required to supply current necessary for signal transmission between these circuit elements and circuit operation from a power supply. Therefore, the insulating layer 2 is formed of, for example, a silicon oxide film or a silicon nitride film as a base for the wiring. A contact hole (not shown) with the underlying layer is opened at a predetermined position in this insulating layer 2. Thereafter, an aluminum alloy (All-8i
alloy.
Ａｍ−５ｉ−Ｃｕ合金等）やタングステン、モリブデン
等からなる金属薄膜の配線層４．６が絶縁層２の表面上
に形成される。このような配線層の形成は、スパッタリ
ング法や化学的気相成長法（ＣＶＤ法）によって全表面
に導電膜を形成した後に、フォトリソグラフィ法（光露
光技術）を用いて容易に行なわれる。配線層の幅は、許
容可能な配線抵抗と最大電流密度の値から決定される。A wiring layer 4.6 of a metal thin film made of Am-5i-Cu alloy, etc.), tungsten, molybdenum, etc. is formed on the surface of the insulating layer 2. Formation of such a wiring layer is easily performed using a photolithography method (light exposure technique) after forming a conductive film on the entire surface by a sputtering method or a chemical vapor deposition method (CVD method). The width of the wiring layer is determined from the allowable wiring resistance and maximum current density values.
通常、接地ラインや電源供給ラインには、配線層６のよ
うに、通常の信号線として用いられる配線層４の幅に対
して５〜１０倍の幅を有する幅広の配線層が使用されて
いる。Usually, a wide wiring layer, such as the wiring layer 6, which is 5 to 10 times as wide as the width of the wiring layer 4 used as a normal signal line is used for the ground line and the power supply line. .
［発明が解決しようとする問題点コ
従来のＬＳＩにおける配線は以上のように構成されてい
るので、限られたＬＳＩチップの平面領域のうち、かな
り多くの領域が接地ラインや電源供給ラインのような線
幅の広い配線を形成するために占有されなければならな
いという問題点があった。その結果、１チツプあたりの
面積が大きくなり、１枚のウェハあたりの作製チップ数
が少なくなるので、１チツプあたりの製造コストが高く
なるなどの問題点が生じていた。[Problems to be Solved by the Invention] Since the wiring in conventional LSIs is configured as described above, a considerable portion of the limited planar area of the LSI chip is used for grounding lines, power supply lines, etc. There is a problem in that it must be occupied in order to form wiring with a wide line width. As a result, the area per chip increases and the number of chips manufactured per wafer decreases, resulting in problems such as an increase in manufacturing cost per chip.
そこで、この発明は、上記のような問題点を解消するた
めになされたもので、従来の配線と同程度以上の配線幅
を有し、しかも従来の数分の１以下のチップ占有面積で
済む配線層を有する半導体装置を提供することを目的と
する。Therefore, this invention was made to solve the above-mentioned problems, and has a wiring width comparable to or more than that of conventional wiring, yet occupies a chip area less than a fraction of that of conventional wiring. An object of the present invention is to provide a semiconductor device having a wiring layer.
［問題点を解決するための手段］
この発明に従った配線層を有する半導体装置は、半導体
基板の表面上に絶縁層が形成され、この絶縁層の上には
半導体基板の表面とほぼ直交する平面に沿うように絶縁
壁が形成されている。配線層は、絶縁層の上に形成され
た第１の配線層と、絶縁壁の側壁部に形成された第２の
配線層とからなっている。[Means for Solving the Problems] In a semiconductor device having a wiring layer according to the present invention, an insulating layer is formed on the surface of a semiconductor substrate, and on this insulating layer there is a layer that is substantially orthogonal to the surface of the semiconductor substrate. An insulating wall is formed along the plane. The wiring layer includes a first wiring layer formed on the insulating layer and a second wiring layer formed on the side wall of the insulating wall.
［作用］
この発明における配線層は、半導体基板表面とほぼ直交
する平面に沿う絶縁壁の側壁部にも形成されている。そ
のため、予め、必要な配線幅に相当する高さを持った絶
縁壁を形成し、その側壁部に線幅の広い配線を形成する
ことができる。したがって、半導体装置の平面領域には
絶縁壁と配線層との幅に相当する表面積が占有されるだ
けで線幅の広い配線が形成され得る。[Function] The wiring layer in the present invention is also formed on the side wall portion of the insulating wall along a plane substantially perpendicular to the surface of the semiconductor substrate. Therefore, it is possible to form an insulating wall in advance with a height corresponding to the required wiring width, and to form wiring with a wide line width on the side wall portion of the insulating wall. Therefore, wiring with a wide line width can be formed only by occupying a surface area corresponding to the width of the insulating wall and the wiring layer in a planar region of the semiconductor device.
［発明の実施例コ 以下、この発明の一実施例を図について説明する。[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.
第１Ａ図はこの発明に従った配線層を有する半導体装置
を示す部分平面図、第１Ｂ図は第１Ａ図におけるＩＢ−
ＩＢ線に沿った部分断面図である。FIG. 1A is a partial plan view showing a semiconductor device having a wiring layer according to the present invention, and FIG. 1B is an IB-
FIG. 3 is a partial cross-sectional view taken along line IB.
この配線層の形成方法を説明する。まず、従来法と同様
に、ＬＳＩの回路構成に必要なトランジスタ、キャパシ
タ、抵抗等の回路要素を形成する（図示せず）。半導体
基板１上には絶縁層２が形成され、下地層との間にコン
タクト孔（図示せず）が形成される。この段階までは、
従来法と同様である。A method for forming this wiring layer will be explained. First, as in the conventional method, circuit elements such as transistors, capacitors, and resistors necessary for the circuit configuration of the LSI are formed (not shown). An insulating layer 2 is formed on a semiconductor substrate 1, and a contact hole (not shown) is formed between the insulating layer 2 and the underlying layer. Until this stage,
It is the same as the conventional method.
その後、線幅の広い配線を行なうべき位置に絶縁壁３を
形成する。絶縁壁３の材質としては、プラズマ化学的気
相成長法（プラズマＣＶＤ法）等によって作製された酸
化シリコン膜や窒化シリコン膜でもよい。しかしながら
、絶縁壁３は５μｍ以上の高さが必要となる場合が多い
ので、回転塗布により形成されるポリイミド系の高分子
化合物からなる膜が最も望ましい。After that, an insulating wall 3 is formed at a position where a wide line width wiring is to be performed. The material of the insulating wall 3 may be a silicon oxide film or a silicon nitride film produced by plasma chemical vapor deposition (plasma CVD) or the like. However, since the insulating wall 3 is often required to have a height of 5 μm or more, a film made of a polyimide-based polymer compound formed by spin coating is most desirable.
この絶縁壁３を形成する方法は以下のような工程で行な
われる。まず、目的とする配線の所定の線幅に相当する
高さになるまでポリイミドを塗布する。その後、２００
℃以上の温度で、ポリイミド塗布膜の揮発成分を除き、
固めるためにキュア処理を施す。次に、クロムやアルミ
ニウム等からなる薄膜をその上に形成する。そして、通
常のフォトリソグラフィ法によって絶縁壁の幅に相当す
る位置のみにその金属薄膜を残す。その後、全面に異方
性プラズマエツチング処理（Ｒｅａｃｔｉｖｅ Ｉｏ
ｎ Ｅｔｃｈｉｎｇ）を施すと、金属薄膜でマスクさ
れた部分のみにポリイミドが絶縁壁となって残る。この
とき、プラズマエツチング処理のエツチングガスとして
は、ポリイミドの場合には酸素ガスを主成分とするもの
が有効である。The method for forming the insulating wall 3 is performed in the following steps. First, polyimide is applied to a height corresponding to a predetermined line width of the intended wiring. After that, 200
Remove the volatile components of the polyimide coating film at a temperature of ℃ or higher,
Apply curing treatment to harden. Next, a thin film made of chromium, aluminum, etc. is formed thereon. Then, the metal thin film is left only at a position corresponding to the width of the insulating wall using a normal photolithography method. After that, the entire surface was subjected to anisotropic plasma etching treatment (Reactive Io
When N Etching is performed, polyimide remains as an insulating wall only in the portion masked by the metal thin film. At this time, as the etching gas for the plasma etching process, in the case of polyimide, a gas containing oxygen gas as a main component is effective.
その後、全面にアルミニウム合金等の配線材料からなる
膜をスパッタリング法あるいは化学的気相成長法によっ
て形成する。従来法と同様にフォトリソグラフィ法を用
いてこの膜にエツチング処理を施すことにより、配線パ
ターンにしたがった配線層が形成される。その結果、線
幅の狭い配線層４が形成されると同時に、絶縁壁３の側
壁部にも配線層５が形成される。この絶縁壁３の両側壁
部に形成された２本の配線層５が線幅の広い配線として
使用される。Thereafter, a film made of a wiring material such as aluminum alloy is formed over the entire surface by sputtering or chemical vapor deposition. By etching this film using photolithography as in the conventional method, a wiring layer is formed in accordance with the wiring pattern. As a result, a wiring layer 4 having a narrow line width is formed, and at the same time, a wiring layer 5 is also formed on the side wall portion of the insulating wall 3. Two wiring layers 5 formed on both side walls of this insulating wall 3 are used as wide wiring.
なお、上記実施例では線幅の広い配線層が２本の場合の
みについて示したが、２本以上であっても全く同じ工程
数で形成することができることは言うまでもない。また
、配線材料も特にアルミニウム合金に限定されるもので
はなく、多結晶シリコン、タングステンやモリブデン等
の高融点金属および各種金属シリサイドも配線材料とし
て適用することができる。In the above embodiment, only two wiring layers with wide line widths are shown, but it goes without saying that two or more wiring layers can be formed using exactly the same number of steps. Furthermore, the wiring material is not particularly limited to aluminum alloy, and polycrystalline silicon, high melting point metals such as tungsten and molybdenum, and various metal silicides can also be used as the wiring material.
［発明の効果コ
以上のように、この発明によれば配線層を絶縁壁の側壁
部分にも形成するようにしたので、半導体装置の平面領
域において小さい占有面積で線幅の広い配線を形成する
ことができ、チップ面積を大幅に縮小できるという効果
がある。[Effects of the Invention] As described above, according to the present invention, the wiring layer is also formed on the side wall portion of the insulating wall, so that wiring with a wide line width can be formed in a small occupied area in the planar area of the semiconductor device. This has the effect of significantly reducing the chip area.
第１Ａ図、第１Ｂ図はこの発明の一実施例による半導体
装置の配線構造を示す部分平面図、および部分断面図、
第２Ａ図、第２Ｂ図は従来の半導体装置の配線構造を示
す部分平面図および部分断面図である。
図において、１は半導体基板、２は絶縁層、３は絶縁壁
、４，５．６は配線層である。
なお、各図中、同一符号は同一または相当部分を示す。1A and 1B are a partial plan view and a partial sectional view showing the wiring structure of a semiconductor device according to an embodiment of the present invention,
FIGS. 2A and 2B are a partial plan view and a partial sectional view showing the wiring structure of a conventional semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is an insulating layer, 3 is an insulating wall, and 4, 5.6 are wiring layers. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (4)
あって、 前記半導体基板の表面上に形成された絶縁層と、前記絶
縁層の上で、前記半導体基板の表面とほぼ直交する平面
に沿うように形成された絶縁壁と、前記絶縁層の上に形
成された第１の配線層と、前記絶縁壁の側壁部に形成さ
れた第２の配線層とを備えた配線層を有する半導体装置
。(1) A semiconductor device having a wiring layer above a semiconductor substrate, comprising: an insulating layer formed on a surface of the semiconductor substrate; A semiconductor having a wiring layer including an insulating wall formed along the insulating wall, a first wiring layer formed on the insulating layer, and a second wiring layer formed on a side wall of the insulating wall. Device.
る、特許請求の範囲第１項に記載の配線層を有する半導
体装置。(2) A semiconductor device having a wiring layer according to claim 1, wherein the insulating wall is made of a polyimide-based polymer compound.
ルミニウム合金からなる、特許請求の範囲第１項または
第２項に記載の配線層を有する半導体装置。(3) A semiconductor device having a wiring layer according to claim 1 or 2, wherein the first wiring layer and the second wiring layer are made of an aluminum alloy.
融点金属からなる、特許請求の範囲第１項または第２項
に記載の配線層を有する半導体装置。(4) A semiconductor device having a wiring layer according to claim 1 or 2, wherein the first wiring layer and the second wiring layer are made of a high melting point metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28161887A JPH01123434A (en) | 1987-11-06 | 1987-11-06 | Semiconductor device with wiring layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28161887A JPH01123434A (en) | 1987-11-06 | 1987-11-06 | Semiconductor device with wiring layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01123434A true JPH01123434A (en) | 1989-05-16 |
Family
ID=17641640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28161887A Pending JPH01123434A (en) | 1987-11-06 | 1987-11-06 | Semiconductor device with wiring layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01123434A (en) |
-
1987
- 1987-11-06 JP JP28161887A patent/JPH01123434A/en active Pending
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