KR890004875B1 - Manufacture of electrode on semiconductor body - Google Patents

Manufacture of electrode on semiconductor body Download PDF

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KR890004875B1
KR890004875B1 KR1019870005960A KR870005960A KR890004875B1 KR 890004875 B1 KR890004875 B1 KR 890004875B1 KR 1019870005960 A KR1019870005960 A KR 1019870005960A KR 870005960 A KR870005960 A KR 870005960A KR 890004875 B1 KR890004875 B1 KR 890004875B1
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South Korea
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metal layer
layer
forming
aluminum metal
aluminum
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KR1019870005960A
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Korean (ko)
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KR890001173A (en
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안용철
송창룡
박문진
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삼성전자 주식회사
강진구
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The manufacturing method of the semiconductor multi layer interconnection for preventing the short has the following steps: (a) depositing metal layer (3) with chemical stability to prevent hillock of Aluminium metal layer (2) formed on a oxide layer (1) ; (b) forming a pattern by etching the metal layer (2,3) ; (c) depositing LTO (low temperature oxide layer) (4) to imsulate ; (d) forming a contact window (5) by etching the LTO (4) and metal layer (3) ; (e) forming a second metal interconnection pattern by using the second Al metal layer (6).

Description

반도체 다층배선 장치의 제조방법Manufacturing method of semiconductor multilayer wiring apparatus

제1(a)도-제1(e)도는 본 발명에 따른 제조공정도.1 (a) to 1 (e) is a manufacturing process diagram according to the present invention.

본 발명은 반도체 장치중 다층배선 장치의 제조방법에 관한 것으로 특히 다층 배선간의 단락방지를 위한 반도체 다층배선 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring apparatus among semiconductor devices, and more particularly, to a method for manufacturing a semiconductor multilayer wiring apparatus for preventing short circuits between multilayer wirings.

최근 반도체 기술분야에 있어서는 VLSI(Very Large Scale Integration)급 소자로 고집적화 되어가는 경향으로 배선(Interconnection Layer)의 길이는 증가하고 선폭(Line-width)은 좁아짐에 따라 배선의 저항이 증가하고 배선 저항증가로 인해 반도체 장치의 동작속도가 떨어지는 큰 문제점이 있었다. 또한 통상적으로 빈도체 장치의배선에 쓰이는 알루미늄은 알루미늄 온도에 대한 특성을 개선하기 위하여 1% 실리콘이 포함된 알루미늄을 많이 사용하고 있다. 이 실리콘이 포함된 알루미늄은 소정 온도에서 많은 힐록(Hillok)을 발생하게 된다.In recent years, semiconductor technology has become increasingly integrated into VLSI (Very Large Scale Integration) devices. As the length of the interconnection layer increases and the line-width narrows, the resistance of the wiring increases and the wiring resistance increases. Due to this, there was a big problem that the operation speed of the semiconductor device is lowered. In addition, the aluminum commonly used in the wiring of the frequency device uses a lot of aluminum containing 1% silicon to improve the characteristics of the aluminum temperature. This silicon-containing aluminum generates a lot of hilok at a predetermined temperature.

상기 반도체 장치의 동작속도 개선을 위해서 현재 반도체 기술분야에서는 다층배선 구조를 이용하고 있다. 그러나 다층배선 구조의 반도체 장치에서는 제1알루미늄 금속층의 힐록발생으로 인해 제1알루미늄 금속층과 제2알루미늄 금속층이 단락(Short)되는 현상이 발생하여 반도체 장치의 신뢰성을 저하시키고 있다.In order to improve the operation speed of the semiconductor device, the semiconductor technology field currently uses a multilayer wiring structure. However, in a semiconductor device having a multi-layered wiring structure, shortening occurs between the first aluminum metal layer and the second aluminum metal layer due to the hillock generation of the first aluminum metal layer, thereby reducing the reliability of the semiconductor device.

따라서 본 발명의 목적은 반도체 장치에서 하부 알루미늄 금속층의 힐록 발생을억제하여 알루미늄 금속층간의 단락을 방지할 수 있는 높은 다층배선 구조 반도체 장치의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device having a high multilayer wiring structure that can prevent a short circuit between aluminum metal layers by suppressing the hillock generation of the lower aluminum metal layer in the semiconductor device.

상기와 같은 본 발명의 목적을 달성하기 위한 본 발명은 반도체기판 상부에 형성된 제1알루미늄 금속층 상부에 내화성이 강한 중간 금속층을 도포하고 금속층의 패턴을 형성한후 절연막을 도포하고 상기 금속층과 하기 제2알루미늄 금속층과의 접촉부위를 형성하기 위해서 소정부위의 절연막을 에칭해내고 저항이 높은 중간 금곡층은 절연막이 에칭된 부위만 에칭해 낸후 제2알루미늄 금속층을 형성하여 제1알루미늄 금속층과 접촉되게 함을 특징으로 한다.The present invention for achieving the object of the present invention as described above is coated with a fire-resistant intermediate metal layer on the upper first aluminum metal layer formed on the semiconductor substrate, after forming a pattern of the metal layer to apply an insulating film and the metal layer and the following second layer In order to form a contact area with the aluminum metal layer, the insulating film of the predetermined portion is etched and the middle gold grain layer having high resistance is etched only in the portion where the insulating film is etched, and then the second aluminum metal layer is formed to be in contact with the first aluminum metal layer. It features.

이하 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail.

제1(a)도-제1(e)도는 본 발명에 따른 제조공정도를 나타낸 도면이다.1 (a) to 1 (e) is a view showing a manufacturing process according to the present invention.

도면중 반도체 기판부분과 반도체 기판에 형성된 소자부분은 생략하였지만 제1알루미늄 금속층과 접속되는 부분은 필요한 부위에서 절연막을 통해 창을 형성하고 접속함은 이미 잘 알려진 사실임을 유의하여야 한다.In the drawings, the semiconductor substrate portion and the element portion formed on the semiconductor substrate are omitted, but it should be noted that the portion connected to the first aluminum metal layer is already well known to form and connect a window through an insulating film at a necessary portion.

제1(a)도는 제1저온 산화막(1)의 상부에 제1알루미늄 금속층(2)과 중간금속층(3)을 형성하는 공정으로서, 제1저온 산화막(1)의 상부에 500㎚의 제1알루미늄 금속층(2)과 100㎚의 중간금속층(3)을 도포한다.FIG. 1 (a) shows a process of forming the first aluminum metal layer 2 and the intermediate metal layer 3 on the first low temperature oxide film 1, the first being 500 nm on the first low temperature oxide film 1 An aluminum metal layer 2 and an intermediate metal layer 3 of 100 nm are applied.

이 고정에서 내화성 금속인 티탄(Ti)이나 텅스텐(W)같은 중간금속층을 형성함으로써, 이후 고온처리공정시 제1알루미늄 금속층에서 발생될 수 있는 힐록을 최대한 줄이게 된다.In this fixing, by forming an intermediate metal layer such as titanium (Ti) or tungsten (W) as refractory metals, the hillocks generated in the first aluminum metal layer during the high temperature treatment process can be minimized.

그후 제1(b)도에 도시된 바와같이 상기 금속층(2)(3)의 패턴을 형성하고나서제1(c)도에 도시된 바와같이 제2저온 산화막(4)을 도포한후 평탄화를 실시한다.Thereafter, as shown in FIG. 1 (b), the pattern of the metal layers 2 and 3 is formed, and then the second low temperature oxide film 4 is applied as shown in FIG. Conduct.

제1(d)도는 제1알루미늄 금속층과 제2알루미늄 금속층의 접촉부 형성을 위한에칭공정을 나타낸 도면으로서, 제1알루미늄 금속층과 제2알루미늄 금속층의 접촉부위의 제2저온 산화막(4)과 중간금속층(3)을 FR 스퍼터링 에칭(Radio Frequency Sputtering Etching)방법으로 에칭을 실시하여 접촉창(5)을 형성한다.FIG. 1 (d) illustrates an etching process for forming a contact portion between the first aluminum metal layer and the second aluminum metal layer, wherein the second low temperature oxide film 4 and the intermediate metal layer at the contact portion between the first aluminum metal layer and the second aluminum metal layer. (3) is etched by FR Sputtering Etching to form a contact window 5.

중간 금속층(3)은 내화성 금속이어서 제1알루미늄 금속층의 힐록을 줄이는 역할을 하지만 저항성이 높기 때문에 제2알루미늄 금속층과 접촉부위만 중간 금속층을 제거해 주게되면 힐록방지와 더불어 접촉부의 저항 문제도 해결이 되게된다.The intermediate metal layer 3 is a refractory metal, which serves to reduce the hillock of the first aluminum metal layer. However, since the intermediate metal layer 3 removes the intermediate metal layer only from the second aluminum metal layer and the contact portion, the problem of resistance to the contact portion is also solved. do.

제1(e)도는 상기 저온 산화막(4) 상부에 접촉상(5)을 통해 제1알루미늄 금속층과 접촉되는 제2알루미늄 금속층을 800㎚ 정도 도포하는 것이다.In FIG. 1 (e), the second aluminum metal layer which is in contact with the first aluminum metal layer through the contact phase 5 on the low temperature oxide film 4 is coated with about 800 nm.

상술한 바와같은 본 발명은 제1알루미늄 금속층 상부에 내화성 금속인 중간금속층을 도포하여 이후의 고온 처리공정에서 생길수 있는 힐록을 최소한으로 한다.The present invention as described above is applied to the middle metal layer of the refractory metal on the first aluminum metal layer to minimize the hillock that can occur in the subsequent high temperature treatment process.

또한 본 발명은 제1알루미늄 금속층과 중간 금속층으로 이루어지는 제1금속층과 제2알루미늄 금속층의 접촉부에서 저항성이 높은 중간금속층을 에칭해 냄으로써 제1금속층과 제2금속층간의 접촉저항의 손상을 줄일수 있는 이점이 있다.In addition, the present invention can reduce the damage of the contact resistance between the first metal layer and the second metal layer by etching the highly resistant intermediate metal layer at the contact portion of the first metal layer and the second aluminum metal layer consisting of the first aluminum metal layer and the intermediate metal layer. There is an advantage.

Claims (1)

다층배선 구조를 가진 반도체 장치의 제조방법에 있어서, 반도체 기판상의 제1저온 절연산화막층(1)상에 상기 반도체 기판에 형성된 소자의 소정부분과 접촉을 하기위한 제1알루미늄 금속층(2) 도포하고 그 상부에 상기 알루미늄 금속층(2)의 힐록 발생을 방지하기 위한 내화성의 중간금속층을 도포하는 제1공정과, 사진 식각공정을 이용하여 상기 금속층(2)(3)에 에칭을 실시하여 제1금속배선 패턴을 형성하는 제2공정과, 전면에 금속물질층간의 절연을 목적으로 하는 저온 산화막(4)을 도포하는 제3공정과, 소정부위의 저온 산화막(4)과 중간금속층(3)을 같이 에칭하여 금속층간의 접촉을위한 접촉창(5)을 형성하는 제4공정과, 전면에 제2알루미늄 금속층(6)을 도포하여 제2금속배선 패턴을 형성하는 제5공정을 구비하여 상기 공정들의 연속으로 다층의 배선층을 형성함을 특징으로 하는 반도체 장치의 제조방법.In the method of manufacturing a semiconductor device having a multi-layered wiring structure, a first aluminum metal layer (2) is coated on a first low temperature insulating oxide layer (1) on a semiconductor substrate to make contact with a predetermined portion of an element formed on the semiconductor substrate. The metal layer 2 and 3 are etched using a first step of applying a fire-resistant intermediate metal layer on the upper portion of the aluminum metal layer 2 to prevent the occurrence of heellock and a photolithography process. The second step of forming the wiring pattern, the third step of applying the low temperature oxide film 4 for the purpose of insulation between the metal material layers on the entire surface, and the low temperature oxide film 4 and the intermediate metal layer 3 of the predetermined portion together And a fourth process of etching to form a contact window 5 for contact between the metal layers, and a fifth process of applying a second aluminum metal layer 6 to the entire surface to form a second metal wiring pattern. Multi-layer wiring layer in a row Forming a semiconductor device, characterized in that for forming.
KR1019870005960A 1987-06-12 1987-06-12 Manufacture of electrode on semiconductor body KR890004875B1 (en)

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KR1019870005960A KR890004875B1 (en) 1987-06-12 1987-06-12 Manufacture of electrode on semiconductor body

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KR1019870005960A KR890004875B1 (en) 1987-06-12 1987-06-12 Manufacture of electrode on semiconductor body

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KR890004875B1 true KR890004875B1 (en) 1989-11-30

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