JPH0684901A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To form an interlayer insulation film having an uniform film thickness to flat and reduce capacitance between wirings by a method wherein a SOG film is selectively formed on the insulation film formed on a lower layer wiring to use this SOG film as a mask for heat-treating. CONSTITUTION:Lower layer wirings 4 to 7 are formed on a semiconductor substrate 1, and on the entire surface of the semiconductor substrate 1 formed with the lower layer wirings 4 to 7, a BPSG film 9 is formed as an insulation film having reflow characteristics through a CVD oxide film 8. On a desired part on the BPSG film 9, a film 10 composed of a glass solution dissolved selectively in an organic solvent is formed. A heat treatment is performed by using the film 10 as a mask and an upper layer wiring 12 connecting to the lower layers 4 to 7 is formed. Thus, it is possible to prevent a reduction in a film thickness of an insulation film formed on the lower layer wiring. Accordingly, irrespective of density of lower layer wiring patterns, an interlayer insulation film can uniformly be flatted and capacitance between the wirings can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a semiconductor device having a wiring pattern in which a distance between adjacent wirings is narrow and a wiring pattern in which a distance between adjacent wirings is relatively wide. The present invention relates to a method for manufacturing a semiconductor device having improved planarization of an interlayer insulating film.

[0002]

2. Description of the Related Art Conventionally, LSI (Large Scale Integration)
With the higher integration and higher speed of ated circuits), device miniaturization (scale down) is rapidly progressing. In the conventional LSI, device miniaturization is achieved by positively advancing two-dimensional integration, that is, reducing the planar dimension.

However, in the conventional LSI described above, in order to prevent the parasitic resistance of the wiring itself and the parasitic capacitance between the lower layer wiring, the upper layer wiring, and the interlayer from increasing, the vertical dimension that hinders high performance is positive. Tended not to shrink. Therefore, there is a problem that the aspect ratio of the wiring is increased and the step coverage of the upper wiring formed via the interlayer insulating film is reduced.

Therefore, in order to achieve the flattening of the interlayer insulating film, for example, a glass solution (Sp
in on Glass; hereinafter referred to as “SOG”) is applied by spin coating and heat treatment, and AC Adams et al.
trochem.Soc., 128, p171 (1981) ”, PSG (Phosho-Sil) containing a relatively high concentration of phosphorus.
A flattening method in which icate Glass) is subjected to high temperature heat treatment and reflowed, W. Kern et al., “Solid State Tech., 28, p171 (198
5) ”, BPSG (Boron-Phospha
A flattening method in which rus-Silicate Glass) is heat-treated at high temperature and reflowed is known.

[0005]

However, in the above-described flattening method, the entire surface of the wafer is uniformly flattened regardless of the pattern of the lower layer wiring formed under the interlayer insulating film. Therefore, for example, an interlayer insulating film formed on a wiring whose pattern is rough (a wiring pattern in which the distance between adjacent wirings is wide) and whose wiring length is relatively long has a dense pattern (adjacent wiring). There is a problem that the film thickness is smaller than that of the interlayer insulating film formed on the wiring which is a wiring pattern having a small distance between the wirings. That is,
There is a problem that the flattening rate is different between the dense and rough portions of the lower layer wiring pattern. Therefore, there is a problem that the inter-wiring capacitance becomes large in the portion where the film thickness of the interlayer insulating film is small.

An object of the present invention is to solve such a problem. An interlayer insulating film having a uniform film thickness is formed regardless of the density of the lower layer wiring pattern to improve the flatness. An object of the present invention is to provide a method for manufacturing a semiconductor device that reduces the capacitance between wirings.

[0007]

To achieve this object, the present invention provides a first method for forming a lower layer wiring on a semiconductor substrate.
A second step of forming an insulating film having a reflow property on the entire surface of the semiconductor substrate on which the lower layer wiring is formed,
A third step of forming a film made of a glass solution selectively dissolved in an organic solvent on a desired portion on the reflowable insulating film, and a heat treatment using the film made of the glass solution dissolved in the organic solvent as a mask. The present invention provides a method for manufacturing a semiconductor device, which includes a fourth step to be performed and a fifth step to form an upper layer wiring connected to the lower layer wiring and / or the semiconductor substrate.

[0008]

According to the method of manufacturing the semiconductor device of the present invention,
A desired portion on the reflowable insulating film formed on the lower layer wiring, that is, when the insulating film is reflowed, the film thickness is reduced and an increase in parasitic capacitance becomes a problem. By selectively forming an SOG film on the insulating film and then performing heat treatment using this SOG film as a mask,
Only the insulating film corresponding to the portion other than the portion where the SOG film is formed can be reflowed. That is, the SOG
Reflow does not occur in the insulating film corresponding to the portion masked by the film even when the heat treatment is performed, and the film thickness at the time of forming the insulating film can be left as it is. Therefore, for example, it is possible to prevent the film thickness of the insulating film formed on a wiring having a rough pattern and a relatively long wiring length from decreasing. Further, since the insulating film formed on the wiring having a dense pattern is reflowed, it is possible to achieve flatness. Therefore, priority is given to increasing the film thickness of the interlayer insulating film formed on the lower layer wiring, which is particularly affected by the wiring capacitance, and the interlayer insulating film formed on the portion where the step coverage of the upper layer wiring is desired to be flat. Can be prioritized.

When the distance between adjacent wirings of the wiring pattern is 5 μm or more, it is desirable that the wiring has a rough pattern and an SOG film is formed on the insulating film.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment according to the present invention will be described with reference to the drawings. 1 to 4 are partial cross-sectional views showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention. In the step shown in FIG. 1, after the oxide film 2 is formed on the semiconductor substrate 1 by a known method, a polycrystalline silicon film having a film thickness of about 500 nm is formed on the oxide film 2. Next, the polycrystalline silicon film is patterned to form lower layer wirings 4 to 7. Here, the patterning is
When the wiring width is about 0.5 to 1 μm, the distance between the lower layer wiring 4 and the lower layer wiring 5 and the distance between the lower layer wiring 5 and the lower layer wiring 6 are about 1 to 3 μm. The distance to the wiring 7 is set to about 6 to 10 μm, the lower wirings 4 to 6 are wiring groups having a dense pattern, and the lower wiring 7 is a wiring having a rough pattern (isolated pattern).

Next, in the step shown in FIG. 2, a CVD (Chemical Vapor Depth) is applied to the semiconductor substrate 1 obtained in the step shown in FIG.
of the CVD oxide film 8 having a film thickness of about 100 nm on the oxide film 2 and on the surfaces of the lower layer wirings 4 to 7.
Deposit at 0 ° C. Then, a BPSG film 9 having a thickness of about 800 nm is deposited at 430 ° C. on the CVD oxide film 8 as an insulating film having a reflow property.

Next, in the step shown in FIG. 3, SOG is spin-coated on the BPSG film 9 obtained in the step shown in FIG. 2 to form an SOG film having a flat surface converted thickness of about 80 nm. Next, the SOG film was baked in a nitrogen atmosphere at 80 ° C. for 10 minutes, 200 ° C. for 10 minutes, and 750 ° C. for 30 minutes, and then the SOG film was selectively etched to roughen the pattern. The SOG film 10 is formed only in the vicinity of the wiring (lower wiring 7). Next, the SOG
Using the film 10 as a mask, the BPSG film 9 is heat-treated at 950 ° C. for 20 minutes in a nitrogen atmosphere to obtain the BPSG film 9
To reflow. At this time, the BPSG film 9 corresponding to the portion masked by the SOG film 10 does not undergo reflow even if the heat treatment is performed, and the film thickness at the time of forming the BPSG film 9 can be left as it is. Therefore, a thick BPSG film is formed in this portion, and the parasitic capacitance can be reduced. On the other hand, the SOG film 10 is not formed (a wiring group having a dense pattern (lower wiring 4 to
6) The BPSG film (formed above) is reflowed so that planarization is achieved.

Next, in the step shown in FIG. 4, the BPSG is
The film 9 and the CVD oxide film 8 are selectively removed, and the lower wiring 4
To 7, the contact hole 11, the BPSG film 9, and the CV
The D oxide film 8 and the oxide film 2 are selectively removed, and a contact hole 11 connected to the semiconductor substrate 1 is opened. Then, the inner surface of the contact hole 11 and BPSG are formed by a sputtering method.
After depositing an aluminum film on the film 9 and the SOG film 8, the aluminum film is patterned to form the upper wiring 12.

Further, by repeating the steps shown in FIG. 2 and subsequent steps, it is possible to deal with a multi-layer wiring structure having three or more wiring layers. Then, desired steps are performed to complete the semiconductor device. In this embodiment, a wiring group with a dense pattern has a distance between adjacent wiring films of about 1 to 3 μm, and a wiring having a rough pattern with a distance of 6 to 10 μm between adjacent wiring films. However, the present invention is not limited to this, and a wiring group in which the distance between adjacent wiring films is less than 5 μm is a dense wiring group, a wiring group in which the distance between adjacent wiring films is 5 μm or more is a rough wiring group, It is preferable that

In this embodiment, the SOG film 10 is formed on the BPSG film 9 at a portion corresponding to the vicinity of the wiring having a rough pattern. However, the SOG film 10 is not limited to this, and the pattern is dense. Even in the case of wiring, if the step coverage of the upper layer wiring formed thereon does not matter, the SOG film 10 may be formed also on the BPSG film 9 corresponding to this portion.

Then, in this embodiment, after the BPSG film 9 is reflowed using the SOG film 10 as a mask, the SO
Although the upper layer wiring 12 is formed without removing the G film 10, the present invention is not limited to this, and the upper layer wiring 12 may be formed after removing the SOG film 10 if desired. Further, in this embodiment, the BPSG film 9 is used as the insulating film having the reflow property, but the present invention is not limited to this, and the same effect can be obtained by using another insulating film having the reflow property such as the PSG film. be able to.

Further, before the SOG film is applied or after the BPSG film 9 is reflowed, the SOG film 1 is formed.
To remove 0, after removing the SOG film 10, or
After opening the contact hole 11, perform a relatively light heat treatment,
The BPSG film 9 may be lightly reflowed.

[0018]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a desired portion on the reflowable insulating film formed on the lower wiring, that is, the reflow of the insulating film is caused. By selectively forming an SOG film on the insulating film formed on the lower layer wiring in which an increase in parasitic capacitance due to a decrease in film thickness is caused, and then performing heat treatment using this SOG film as a mask, the SOG film is formed. It is possible to reflow only the insulating film corresponding to the portion other than the portion where the is formed. Therefore, it is possible to prevent the film thickness of the insulating film formed on the lower layer wiring from being reduced, which causes a problem of increasing the parasitic capacitance due to the film thickness reduction due to the reflow of the insulating film,
Since the other part is reflowed, the planarization can be achieved. Therefore, priority is given to increasing the film thickness of the interlayer insulating film formed on the lower layer wiring, which is particularly affected by the wiring capacitance, and the interlayer insulating film formed on the portion where the step coverage of the upper layer wiring is desired to be flat. Can be prioritized. As a result, regardless of the density of the lower layer wiring pattern, an interlayer insulating film having a uniform film thickness can be formed, planarization can be improved, and wiring capacitance can be reduced.
A highly integrated semiconductor device with high integration can be provided.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

[Symbols] 1 semiconductor substrate 2 oxide film 4 lower layer wiring 5 lower layer wiring 6 lower layer wiring 7 lower layer wiring 8 CVD oxide film 9 BPSG film 10 SOG film 11 contact hole 12 upper layer wiring

Claims (1)

[Claims] 1. A first wiring for forming a lower layer wiring on a semiconductor substrate
A second step of forming an insulating film having a reflow property on the entire surface of the semiconductor substrate on which the lower layer wiring is formed,
A third step of forming a film made of a glass solution selectively dissolved in an organic solvent on a desired portion on the reflowable insulating film, and a heat treatment using the film made of the glass solution dissolved in the organic solvent as a mask. A method of manufacturing a semiconductor device, comprising: a fourth step to be performed; and a fifth step of forming an upper layer wiring connected to the lower layer wiring and / or the semiconductor substrate.