JPH0226054A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0226054A JPH0226054A JP17597488A JP17597488A JPH0226054A JP H0226054 A JPH0226054 A JP H0226054A JP 17597488 A JP17597488 A JP 17597488A JP 17597488 A JP17597488 A JP 17597488A JP H0226054 A JPH0226054 A JP H0226054A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- insulation film
- heat treatment
- film
- coated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000010438 heat treatment Methods 0.000 claims abstract description 32
- 238000000576 coating method Methods 0.000 claims abstract description 19
- 239000011248 coating agent Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 13
- 239000002904 solvent Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 abstract 17
- 239000010410 layer Substances 0.000 description 27
- 239000011229 interlayer Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000001035 drying Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000006068 polycondensation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- -1 silanol compound Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、多層配線構造を得るに好適な半導体装置の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device suitable for obtaining a multilayer wiring structure.
従来の技術
デバイスの高集積化、高速化を図るため、多層配線構造
を備えたものが増えている。多層配線構造を実現するに
は、上層配線と下層配線の間に、電気的絶縁と、下層配
線の凹凸を抑制するための平坦化とが可能な眉間絶縁膜
を設けることが必要である。In order to achieve higher integration and higher speed of conventional technology devices, an increasing number of devices are equipped with multilayer wiring structures. In order to realize a multilayer wiring structure, it is necessary to provide a glabella insulating film that can provide electrical insulation and flattening to suppress unevenness of the lower layer wiring between the upper layer wiring and the lower layer wiring.
従来の多層配線構造を実現するにあたり、層間絶縁膜と
して塗布方式により形成する絶縁膜を採用した従来の半
導体装置の製造方法を第２図（ａ）〜（ｃ）の工程図を
参照して説明する。なお、第２図はアルミニウム（ＡＭ
）の二層配線の製造工程を示しており、簡明化のため半
導体素子領域と平坦化領域は示していない。In realizing a conventional multilayer wiring structure, a conventional method for manufacturing a semiconductor device using an insulating film formed by a coating method as an interlayer insulating film will be explained with reference to the process diagrams in FIGS. 2(a) to (c). do. In addition, Figure 2 shows aluminum (AM
) shows the manufacturing process of the two-layer wiring, and the semiconductor element region and planarization region are not shown for the sake of simplicity.
この製造方法では、まず、半導体基板１の中に作り込ま
れた半導体素子（図中には示されていない）を相互接続
するために、Ａ１合金膜などからなる膜厚０．８μｍの
導体膜をスパッタリングなどで形成し、さらに５所定の
レジストパターン２を形成したのち、ドライエツチング
をほどこして下層配線３を形成する〔第２図（ａ）〕。In this manufacturing method, first, in order to interconnect semiconductor elements (not shown in the figure) fabricated in the semiconductor substrate 1, a conductive film of 0.8 μm thick made of an A1 alloy film or the like is prepared. is formed by sputtering or the like, five predetermined resist patterns 2 are formed, and then dry etching is performed to form the lower layer wiring 3 [FIG. 2(a)].
この後、レジストパターン２を除去し、４５０℃程度の
熱処理を３０分間はどこすことによって、半導体素子の
特性を安定化させる。そののち、ヒロックと称される下
層配線３の突起などにより生じる層間絶縁膜の電気的耐
圧の劣化を防止するため、プラズマＣＶＤ法による酸化
シリコン膜などを、ＣＶＤ層間絶縁膜４として０．５μ
ｍの厚さに堆積する。Thereafter, the resist pattern 2 is removed and heat treatment is performed at about 450° C. for 30 minutes to stabilize the characteristics of the semiconductor element. After that, in order to prevent deterioration of the electrical withstand voltage of the interlayer insulating film caused by protrusions of the lower wiring 3 called hillocks, a silicon oxide film or the like formed by plasma CVD is used as the CVD interlayer insulating film 4 with a thickness of 0.5 μm.
Deposited to a thickness of m.
次に、下層配線３によって生じた半導体基板１の表面の
凹凸を平坦にするため、（下層配線上の膜厚が０．１μ
ｍの）第一の塗布絶縁膜５を回転塗布し、塗布絶縁膜中
の溶剤を除くため２００℃の熱乾燥処理を３０分間はど
ほどこす。さらに、半導体基板１の平坦度を向上するた
め、第二の塗布絶縁膜６（第一と同じ程度の膜厚）を回
転塗布し、第一の塗布絶縁膜と同様な２００℃程度の熱
乾燥処理を行う。そして、第１と第２の塗布絶縁膜５，
６の重縮合を生じさせるため、引き続き、４５０℃の熱
処理を３０分間はどこす〔第２図（ｂ）〕。Next, in order to flatten the unevenness on the surface of the semiconductor substrate 1 caused by the lower layer wiring 3, (the film thickness on the lower layer wiring is 0.1μ
The first coated insulating film 5 (m) is spin-coated and subjected to heat drying treatment at 200° C. for 30 minutes to remove the solvent in the coated insulating film. Furthermore, in order to improve the flatness of the semiconductor substrate 1, a second coated insulating film 6 (approximately the same thickness as the first coated insulating film) is spin-coated, and then heat-dried at about 200°C similar to the first coated insulating film. Perform processing. Then, the first and second coated insulating films 5,
In order to cause polycondensation of No. 6, heat treatment at 450° C. is subsequently performed for 30 minutes [Figure 2 (b)].
最後に、下層配線３の上に形成されたＣＶＤ層間絶縁膜
４と第一、二の塗布絶縁膜５，６にスルーホール７を開
孔し、上層配線８を第２図（ａ）と同様な工程を経て形
成する〔第２図（Ｃ）〕。Finally, a through hole 7 is opened in the CVD interlayer insulating film 4 formed on the lower layer wiring 3 and the first and second coated insulating films 5 and 6, and the upper layer wiring 8 is formed in the same manner as in FIG. 2(a). It is formed through several steps [Figure 2 (C)].
以上の工程を経て半導体基板１上に二層配線が形成され
る。A two-layer wiring is formed on the semiconductor substrate 1 through the above steps.
発明が解決しようとする課題
しかしながら、配線の微細化にともない隣り合う下層配
線３間のスペースが狭くなると、配線の段差形状をなだ
らかにする塗布絶縁膜５，６の形成とステップカバレー
ジが比較的良好なスパッタ蒸着法とを用いても１段差部
に均一な厚さの導体膜を形成することが困難となり、上
層配線８の信頼性の低下を招く。なお、下層配線３の段
差形状は、下層配線３の膜厚を薄くすること、あるいは
、塗布絶縁膜５，６を厚くすることによって緩和される
。しかし、前者の対策をほどこすと配線抵抗の増加なら
びにストレス、エレクトロマイグレーションなどによる
信頼性の低下を招く。一方、後者の対策をほどこすと、
第二の塗布絶縁膜６の熱処理で第一や第二の塗布絶縁膜
５，６にクラックが発生する。このような問題を含む従
来の製造方法では、配線パターンの微細化に限界がある
。Problems to be Solved by the Invention However, as wiring becomes finer, the space between adjacent lower layer wirings 3 becomes narrower, and the formation of coated insulating films 5 and 6 that smooth out the step shape of the wiring and the step coverage become relatively good. Even if a conventional sputter deposition method is used, it is difficult to form a conductor film with a uniform thickness in a single step portion, leading to a decrease in the reliability of the upper layer wiring 8. Note that the step shape of the lower layer wiring 3 can be alleviated by reducing the thickness of the lower layer wiring 3 or by increasing the thickness of the coated insulating films 5 and 6. However, taking the former measure increases wiring resistance and reduces reliability due to stress, electromigration, etc. On the other hand, if we apply the latter measure,
The heat treatment of the second coated insulating film 6 causes cracks to occur in the first and second coated insulating films 5 and 6. Conventional manufacturing methods that involve such problems have a limit to miniaturization of wiring patterns.
そこで本発明は、塗布絶縁膜にクラックを発生させるこ
となしに、半導体基板表面の導体配線の凹凸を抑制でき
るようにして上記の問題点を解決することを目的とする
。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems by suppressing the unevenness of conductor wiring on the surface of a semiconductor substrate without causing cracks in the coated insulating film.
課題を解決するための手段
上記目的を達成するため本発明の半導体装置の製造方法
は、半導体素子が作り込まれた半導体基板上に導体膜を
形成したのちに同導体膜上に所定のレジストパターンを
形成する工程と、同レジストパターンをマスクにして前
記導体膜にドライエツチングをほどこし導体膜パターン
を形成する工程と、前記半導体基板および前記導体膜パ
ターン上に絶縁膜を形成する工程と、同絶縁膜上に第一
の塗布絶縁膜を塗布する工程と、同工程で塗布した塗布
絶縁膜の溶剤を除去する工程と、前記第一の塗布絶縁膜
に第一の熱処理をほどこす工程と、同第一の塗布絶縁膜
上に第二の塗布絶縁膜を塗布する工程と、同第二の塗布
絶縁膜の溶剤を除去する工程と、同第二の塗布絶縁膜に
第二の熱処理をほどこす工程とを経て前記半導体基板の
表面の凹凸を平坦にするものである。Means for Solving the Problems In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes forming a conductor film on a semiconductor substrate in which a semiconductor element is built, and then forming a predetermined resist pattern on the conductor film. a step of dry etching the conductor film using the resist pattern as a mask to form a conductor film pattern; a step of forming an insulating film on the semiconductor substrate and the conductor film pattern; A step of applying a first applied insulating film on the film, a step of removing the solvent of the applied insulating film applied in the same step, and a step of applying a first heat treatment to the first applied insulating film, A step of applying a second coated insulating film on the first coated insulating film, a step of removing the solvent of the second coated insulating film, and a second heat treatment on the second coated insulating film. The unevenness on the surface of the semiconductor substrate is made flat through the steps.
また、本発明の半導体装置の製造方法は、第一の塗布絶
縁膜の熱処理の温度を、第二の塗布絶縁膜の熱処理の温
度以上とするものである。Further, in the method for manufacturing a semiconductor device of the present invention, the temperature of the heat treatment of the first coated insulating film is set to be higher than the temperature of the heat treatment of the second coated insulating film.
作用
このような第一の熱処理の工程の導入により、第二の熱
処理で塗布絶縁膜に生じる応力が抑えられ、クラックの
発生がなく、しかも厚い塗布絶縁膜が形成される。Effect: By introducing the first heat treatment step, the stress generated in the coated insulating film during the second heat treatment is suppressed, and a thick coated insulating film is formed without cracking.
この第一の熱処理の工程を第二の熱処理の工程よりも低
い温度でほどこすと効果が低下し、クラツクが発生しや
すくなるため、この第一の熱処理の工程は、第二の熱処
理の工程の温度以上の温度で行うのが適当である。If this first heat treatment step is performed at a lower temperature than the second heat treatment step, the effect will be reduced and cracks will be more likely to occur. It is appropriate to carry out the process at a temperature higher than .
実施例
本発明にかかる半導体装置の製造方法の一実施例を第１
図（ａ）〜（Ｃ）の工程順図を参照して説明する。なお
、簡明化のために図中にはＡ９Ｊ二層配１ｗ！部分のみ
を示し、半導体素子領域や平坦化領域は示していない。Embodiment A first embodiment of the method for manufacturing a semiconductor device according to the present invention is described below.
The process will be explained with reference to process diagrams shown in FIGS. (a) to (C). For the sake of clarity, A9J double-layer 1w! Only a portion is shown, and a semiconductor element region and a planarization region are not shown.
本発明の製造方法でも、まず半導体基板１の中に作り込
まれた半導体素子領域（図示されていない）を相互接続
するために、ＡＩＱ、合金膜からなる膜厚０．８μｍの
導体膜をスパッタ蒸着で形成し。In the manufacturing method of the present invention, first, in order to interconnect the semiconductor element regions (not shown) formed in the semiconductor substrate 1, a 0.8 μm thick conductive film made of AIQ and alloy film is sputtered. Formed by vapor deposition.
さらに、所定のレジストパターン２を形成したのち、ド
ライエツチングをほどこして下層配線３を形成する〔第
１図（ａ）〕。Furthermore, after forming a predetermined resist pattern 2, dry etching is performed to form a lower layer wiring 3 [FIG. 1(a)].
この後、レジストパターン２を除去し、４５０℃程度の
熱処理を３０分間はどこして、半導体素子の特性を安定
させたのち、プラズマＣＶＤ法による酸化シリコン膜な
どをＣＶＤ層間絶縁膜４として０．５μｍの厚さに堆積
する。Thereafter, the resist pattern 2 is removed, heat treatment is performed at about 450° C. for 30 minutes to stabilize the characteristics of the semiconductor element, and then a silicon oxide film or the like formed by plasma CVD method is used as a CVD interlayer insulating film 4 with a temperature of 0.95°C. Deposit to a thickness of 5 μm.
次に、下層配線３によって生じた半導体基板１の表面の
凹凸を平坦にするため、（下層配線上の膜厚が０．２μ
ｍの）第一の塗布絶縁膜５を回転塗布し、塗布絶縁膜５
中の溶剤を除くため２００℃の熱乾燥処理を３０分間は
ど行う。そして、第一の塗布絶縁膜５の重縮合を生じさ
せるため第一の熱処理を４５０℃で３０分間はどこす。Next, in order to flatten the unevenness on the surface of the semiconductor substrate 1 caused by the lower layer wiring 3, (the film thickness on the lower layer wiring is 0.2μ
The first applied insulating film 5 (m) is spin-coated, and the applied insulating film 5 is
In order to remove the solvent inside, heat drying treatment at 200° C. is performed for 30 minutes. Then, a first heat treatment is performed at 450° C. for 30 minutes to cause polycondensation of the first coated insulating film 5.
さらに、半導体基板１の平坦度を向上するため、第二の
塗布絶縁膜６（第一と同じ程度の膜厚）を回転塗布し、
第一の塗布絶縁膜と同様に２００℃の熱乾燥処理を３０
分間はど行ったのちに、第二の熱処理を４５０℃で３０
分間はどこす。Furthermore, in order to improve the flatness of the semiconductor substrate 1, a second coated insulating film 6 (approximately the same thickness as the first coated film) is spin coated.
Heat drying at 200℃ for 30 minutes in the same way as the first coated insulating film.
After that, a second heat treatment was performed at 450℃ for 30 minutes.
Where are the minutes?
この第一の熱処理を導入することにより、第二の熱処理
のときに生じる塗布絶縁膜の応力を抑えることができる
。したがってクラックが発生することなく厚い塗布絶縁
膜を形成することができる。By introducing this first heat treatment, stress in the coated insulating film that occurs during the second heat treatment can be suppressed. Therefore, a thick coated insulating film can be formed without cracking.
この第一の熱処理を第二の熱処理より低い温度（たとえ
ば３５０℃）でほどこすと効果がなくなり、クラックが
発生するため、第二の熱処理温度以上の温度で行うのが
適当である。If this first heat treatment is performed at a lower temperature than the second heat treatment (for example, 350° C.), the effect will be lost and cracks will occur, so it is appropriate to perform the first heat treatment at a temperature higher than the second heat treatment temperature.
次に、従来の技術に関連して記載したように。Next, as described in relation to the prior art.
周知の方法でＡＭ二層配線構造を形成する。すなわち、
下層配線３の上に形成されたＣＶＤ層間絶縁膜４と第一
、この塗布絶縁膜５，６とにスルーホール７を開孔し、
上層配線８を第１図（ａ）と同様な工程を経て形成する
〔第１図（Ｃ）〕。An AM two-layer wiring structure is formed by a well-known method. That is,
A through hole 7 is opened in the CVD interlayer insulating film 4 formed on the lower wiring 3 and the first coated insulating film 5, 6.
The upper layer wiring 8 is formed through the same steps as in FIG. 1(a) [FIG. 1(C)].
以上の工程を経て本発明の製造方法による二層配線構造
が形成される。Through the above steps, a two-layer wiring structure is formed by the manufacturing method of the present invention.
以上の実施例による多層配線構造では、塗布絶縁膜５，
６の厚膜化により上層配線のステップカバレージは大幅
に改善され配線の不良を防止することができる。In the multilayer wiring structure according to the above embodiment, the applied insulating film 5,
The step coverage of the upper layer wiring is greatly improved by thickening the film of No. 6, and it is possible to prevent wiring defects.
なお、本実施例では二層構造の塗布絶縁膜について説明
したが同様に三層以上の構造を有する塗布絶縁膜にも実
施すれば、さらに上層配線のステップカバレージを向上
させることができる。塗布絶縁膜５，６は、シラノール
化合物を含む有機溶剤の塗布と、その後の熱処理によっ
て形成されるものである。Although this embodiment describes a coated insulating film having a two-layer structure, the step coverage of the upper layer wiring can be further improved by applying the same method to a coated insulating film having a three-layer structure or more. The coated insulating films 5 and 6 are formed by coating an organic solvent containing a silanol compound and subsequent heat treatment.
また、配線についても、アルミニウム合金膜に限られる
ものではなく、たとえば、アルミニウム膜、多結晶シリ
コン膜、シリサイド膜もしくは高融点金属膜などであれ
ばよい。Further, the wiring is not limited to an aluminum alloy film, and may be any material such as an aluminum film, a polycrystalline silicon film, a silicide film, or a high melting point metal film.
発明の詳細
な説明したように、本発明の半導体装置の製造方法によ
れば、第二の塗布配線膜の熱処理時に塗布絶縁膜にクラ
ックが生じるのを防止できるため、塗布絶縁膜を厚くす
ることが可能になって上層配線の断線を防止することが
でき、半導体装置の信頼性を向上させる効果が奏される
。As described in detail of the invention, according to the method for manufacturing a semiconductor device of the present invention, it is possible to prevent cracks from occurring in the coated insulating film during heat treatment of the second coated wiring film. This makes it possible to prevent disconnection of the upper layer interconnection, and has the effect of improving the reliability of the semiconductor device.
第１図（ａ）〜（Ｃ）は本発明にかかる半導体装置の製
造方法の一実施例を示す工程図、第２図（ａ）〜（Ｑ）
は従来の半導体装置の製造方法の工程図である。
１・・・半導体基板、２・・・レジストパターン、３・
・下層配線、４・・・ＣＶＤ層間絶縁膜、５・・・第一
の塗布絶縁膜、６・・・第二の塗布絶縁膜。
代理人 森 本 義 弘
ｔ、ｖｖＱ間絶揉榎FIGS. 1(a) to (C) are process diagrams showing one embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 2(a) to (Q)
1 is a process diagram of a conventional method for manufacturing a semiconductor device. 1... Semiconductor substrate, 2... Resist pattern, 3...
- Lower layer wiring, 4... CVD interlayer insulating film, 5... first coated insulating film, 6... second coated insulating film. Agent Yoshihiro Morimoto, vvQ intercourse
Claims (1)
形成したのちに同導体膜上に所定のレジストパターンを
形成する工程と、同レジストパターンをマスクにして前
記導体膜にドライエッチングをほどこし導体膜パターン
を形成する工程と、前記半導体基板および前記導体膜パ
ターン上に絶縁膜を形成する工程と、同絶縁膜上に第一
の塗布絶縁膜を塗布する工程と、同工程で塗布した塗布
絶縁膜の溶剤を除去する工程と、前記第一の塗布絶縁膜
に第一の熱処理をほどこす工程と、同第一の塗布絶縁膜
上に第二の塗布絶縁膜を塗布する工程と、同第二の塗布
絶縁膜の溶剤を除去する工程と、同第二の塗布絶縁膜に
第二の熱処理をほどこす工程とを経て前記半導体基板の
表面の凹凸を平坦にする半導体装置の製造方法。 ２、第一の塗布絶縁膜の熱処理の温度が第二塗布絶縁膜
の熱処理の温度以上である請求項１記載の半導体装置の
製造方法。[Claims] 1. After forming a conductor film on a semiconductor substrate on which a semiconductor element is built, forming a predetermined resist pattern on the conductor film, and using the resist pattern as a mask to conduct the conductor film. a step of forming a conductor film pattern by dry etching the film; a step of forming an insulating film on the semiconductor substrate and the conductor film pattern; and a step of applying a first coated insulating film on the insulating film; a step of removing the solvent from the coated insulating film applied in the same process; a step of subjecting the first coated insulating film to a first heat treatment; and a step of applying a second coated insulating film on the same first coated insulating film. The unevenness on the surface of the semiconductor substrate is flattened through a step of coating, a step of removing the solvent of the second applied insulating film, and a step of subjecting the second applied insulating film to a second heat treatment. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of the heat treatment of the first coated insulating film is higher than the temperature of the heat treatment of the second coated insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17597488A JPH0226054A (en) | 1988-07-14 | 1988-07-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17597488A JPH0226054A (en) | 1988-07-14 | 1988-07-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0226054A true JPH0226054A (en) | 1990-01-29 |
Family
ID=16005502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17597488A Pending JPH0226054A (en) | 1988-07-14 | 1988-07-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0226054A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5110763A (en) * | 1990-01-29 | 1992-05-05 | Yamaha Corporation | Process of fabricating multi-level wiring structure, incorporated in semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61245540A (en) * | 1985-04-23 | 1986-10-31 | Seiko Epson Corp | Manufacture of semiconductor device |
-
1988
- 1988-07-14 JP JP17597488A patent/JPH0226054A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61245540A (en) * | 1985-04-23 | 1986-10-31 | Seiko Epson Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5110763A (en) * | 1990-01-29 | 1992-05-05 | Yamaha Corporation | Process of fabricating multi-level wiring structure, incorporated in semiconductor device |
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