JPS61245540A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61245540A JPS61245540A JP60087027A JP8702785A JPS61245540A JP S61245540 A JPS61245540 A JP S61245540A JP 60087027 A JP60087027 A JP 60087027A JP 8702785 A JP8702785 A JP 8702785A JP S61245540 A JPS61245540 A JP S61245540A
- Authority
- JP
- Japan
- Prior art keywords
- film layer
- silica film
- layer
- wiring
- silica
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法、より詳しくは半導体基
板の一主面上に比較的厚いシリカフィルム層を、内部に
クラック(亀裂)を生ずることなく形成する方法に関す
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device by forming a relatively thick silica film layer on one principal surface of a semiconductor substrate by forming a crack inside the silica film layer. Concerning how to form without.
本発明は半導体基板の一主面上に比較的厚いシリカフィ
ルム層を形成する半導体装置の製造方法において、前記
半導体基板上に第1のシリカフィルム層を塗布法により
形成し、200〜400℃の温度で焼成後、前記第1の
シリカフィルム層の上、に第2のシリカフィルム層を塗
布法によ膜形成し、200〜400℃の温度で焼成後、
順次かかる工程を複数回繰返し、しかる後に前記焼成温
度よシも高幅の加熱処理を行なうことによシ、層間絶縁
嗅としての特性を下げることなく、塗布法により比較的
厚いシリカフィルム層を形成し、これにより段差を少な
くし、その上に形成した配線の信頼性を同上させると共
に、上層、下層の配線間の絶縁耐圧の低下等を防止し、
半導体装置の製造歩留シを向上させたものである。The present invention provides a method for manufacturing a semiconductor device in which a relatively thick silica film layer is formed on one main surface of a semiconductor substrate, in which a first silica film layer is formed on the semiconductor substrate by a coating method, and After baking at a temperature, a second silica film layer is formed on the first silica film layer by a coating method, and after baking at a temperature of 200 to 400 ° C.,
By repeating these steps several times in sequence and then performing a heat treatment at a higher firing temperature, a relatively thick silica film layer can be formed by a coating method without degrading the interlayer insulation properties. However, this reduces the level difference, improves the reliability of the wiring formed on it, and prevents a drop in dielectric strength between the upper and lower layer wiring.
This improves the manufacturing yield of semiconductor devices.
半導体装t%に集積回路において、集積度の増大に伴っ
て多III配線が多く用いられるようになってきたが、
前記多層配線においては、下層配線上に形成した層間絶
縁膜の急峻な凹凸が上層配線の@線や、上1−2下層の
配線間の絶縁不良等の原因となる。In semiconductor devices and integrated circuits, multi-III wiring has come to be used more and more as the degree of integration increases.
In the multilayer wiring, steep irregularities of the interlayer insulating film formed on the lower layer wiring cause insulation defects in the @ line of the upper layer wiring and between the upper and second lower layer wiring.
そこで、最近では上記障害を除去するために、例えば第
2図に示すように、絶縁膜2を介して第1rfjA配線
3が形成されている半導体基板1上に、気相成長法によ
りケイ酸ガラス(以下NSGと記す)1114を形成後
、前記NEIG膜4上に珪酸51(OR)4またはその
低分子重合体等の溶液の塗布および加熱によりシリカフ
ィルムIfII5ヲ形成L、半導体基板表面の急峻な凹
凸部を平滑化し、前記シリカフィルム層4上に第21−
配線を形成する塗布法が用いられている。Therefore, in recent years, in order to eliminate the above-mentioned obstacles, silicate glass is grown by vapor phase growth on the semiconductor substrate 1 on which the first RFJA wiring 3 is formed through the insulating film 2, for example, as shown in FIG. After forming 1114 (hereinafter referred to as NSG), a solution of silicic acid 51 (OR) 4 or its low-molecular polymer is applied and heated to form a silica film IfII5 on the NEIG film 4, and a silica film L is formed on the steep surface of the semiconductor substrate. The uneven portions are smoothed, and a 21st layer is applied on the silica film layer 4.
A coating method is used to form wiring.
一1絽、ハ、4゜
〔発明が解決しようとする問題点及び目的〕しかし、段
差を小さくするには相当厚いシリカフィルム層5をクラ
ック等の発生なしに形成する必要がある。ところが、シ
リカフィルム層5は塗布後の加熱により脱水され収縮す
るので、膜が少し厚くなるとクラック7を生じてしまう
欠点がある。特に段差部はIll厚が大きいのでこの部
分でのクラックの発生確率は大きい。クラックの発生し
たシリカフィルム層の上に、例えばアルミニウム配線を
すると、このクラック部分で断線を生ずる。[Problems and Objectives to be Solved by the Invention] However, in order to reduce the level difference, it is necessary to form a considerably thick silica film layer 5 without generating cracks or the like. However, since the silica film layer 5 is dehydrated and shrinks due to heating after coating, there is a drawback that cracks 7 may occur if the film becomes slightly thicker. In particular, since the Ill thickness is large at the stepped portion, the probability of cracking occurring at this portion is high. If, for example, aluminum wiring is placed on a cracked silica film layer, the wire will break at the cracked portion.
したがって、従来は塗布法により形成されたシ 。Therefore, conventionally, sheets were formed by a coating method.
リカフィルム層の厚さを薄くして、例えば1000ス以
下としてクラックの発生を防いでいるが、このような薄
い膿では段差の解消効果が非常に少ないという問題点を
有する。Although the thickness of the pus film layer is made thin, for example, 1000 s or less, to prevent the occurrence of cracks, such a thin pus layer has a problem in that the effect of eliminating the step difference is very small.
そこで、本発明はこのような問題点を解決するもので、
その目的とするところは、層間絶縁膜としての特性を下
げることなく、塗布法により比較的厚いシリカフィルム
層を形成し、これにより段差を少なくし、その上に形成
した配線の信頼性を向上させると共に、上層、下層の配
線間の絶縁耐圧の低下等を防止し、半導体装置の製造歩
留りを向上させた半導体装置の製造方法を提供するとこ
ろにある。Therefore, the present invention aims to solve these problems.
The objective is to form a relatively thick silica film layer using a coating method without degrading the properties of the interlayer insulating film, thereby reducing steps and improving the reliability of the wiring formed on it. Another object of the present invention is to provide a method for manufacturing a semiconductor device that prevents a decrease in dielectric strength between upper and lower wiring layers and improves the manufacturing yield of the semiconductor device.
〔間1点を解決するための手段〕
本発明の半導体装置の製造方法は、半導体基板の一主面
上に比較的厚いシリカフィルム層を形成する方法におい
て、前記半導体基板上に第1のシリカフィルム層を塗布
法によ多形成し、前記第1のシリカフィルム層を焼成し
、かく処理された第1のシリカフィルム層の上に第2の
シリカフィルム層を塗布法によ多形成し、前記第2の゛
シリカフィルム層を焼成し、順次かかる工程を複数回繰
返し、しかる後に加熱処理することを特徴とする。[Means for Solving the Problem] The method for manufacturing a semiconductor device of the present invention includes a method for forming a relatively thick silica film layer on one principal surface of a semiconductor substrate. Forming a film layer by a coating method, baking the first silica film layer, and forming a second silica film layer by a coating method on the thus treated first silica film layer, The method is characterized in that the second silica film layer is fired, this process is sequentially repeated a plurality of times, and then heat treatment is performed.
この場合、前記焼成を200〜400℃の温度、又前記
加熱処理を前記焼成温度よシも高温で行なうことが好ま
しい。In this case, it is preferable that the firing is performed at a temperature of 200 to 400°C, and the heat treatment is performed at a higher temperature than the firing temperature.
以下図−を参照“し本発明の詳細について説明する。 The present invention will be explained in detail with reference to the following figures.
第1図を参照すると、半導体素子の機能部が形成され絶
縁11W2でおおわれた半導体基板1上に第1層目のア
ルミニウム(Aj)配ls5が形成され、その上にSi
n、等の81化合物と酸素o2の熱処理による気相成長
法によりNBG喚4を0.5〜1.0μm形成する。さ
らに、このN S G喚4上にシリカフィルムI* 5
を形成するのであるが、このシリカフィルムl−5は第
5図に示す如く多層に形成さレル。N 130 Ill
4の上に、塗布法によりリンを含んだ第17リカフイ
ルム層5 a ヲ500〜1.000λ程度形成する。Referring to FIG. 1, a first layer of aluminum (Aj) wiring Is5 is formed on a semiconductor substrate 1 on which a functional part of a semiconductor element is formed and covered with an insulator 11W2, and a Si
A NBG layer 4 having a thickness of 0.5 to 1.0 μm is formed by a vapor phase growth method using a heat treatment of 81 compounds such as n, etc. and oxygen O2. Furthermore, a silica film I*5 is placed on this NSG ring 4.
This silica film 1-5 is formed into multiple layers as shown in FIG. N 130 Ill
A seventeenth phosphorus-containing film layer 5 a having a thickness of about 500 to 1.000 λ is formed on the phosphorus film by a coating method.
形成には例えば、珪素Si(OR)4とリン化合物とエ
タノールを主溶剤とした珪酸溶剤を、上記N5GIIl
A上にスピンナーにより40o。For the formation, for example, a silicic acid solvent containing silicon Si(OR)4, a phosphorus compound, and ethanol as the main solvent is used to form the above N5GIIl.
40o on A with spinner.
〜6000rpm で10秒塗布後、200〜4o口℃
の温度で、゛50分間の加熱処理を行ないガラス化する
。さらに、第17リカフイルム1−5aの上にかかる第
17リカフイルム層5aと同様の厚さを府中る第27リ
カフイルム層5′bを前記塗布法によ多形成し、それを
前記と同様200〜400℃の温度で加熱処理する。引
続きかかる工程を繰返して比較的厚いシリカフィルム層
を得る。しかる後に、窒素雰囲気中において450〜5
00℃の温度で、20分間の加熱処理により、シリカフ
ィルム層を緻密化(aenstty) L、シリカフィ
ルム・層5を得る。なお、図において、第1.シリカフ
ィルム層5aは砂地で示して200〜400℃の温度で
の加熱処理の終わった状態を表わし、第2シリカフィル
ム層5bは溶剤塗布後で、前記加熱処理の行なわれてい
ない状態を表わす。以上よシ、第1目のアルミニウム配
線5によって生ずる段差は平滑化されているため、段切
れのない第21−目のアルミニウム配線6が実現される
。After applying for 10 seconds at ~6000 rpm, 200 ~ 4°C
Vitrification is performed at a temperature of 50 minutes. Further, a 27th lica film layer 5'b having the same thickness as the 17th lica film layer 5a over the 17th licar film 1-5a is formed by the coating method described above, and it is coated in the same manner as described above. Heat treatment is performed at a temperature of 200 to 400°C. This process is subsequently repeated to obtain a relatively thick silica film layer. After that, in a nitrogen atmosphere, 450-5
By heat treatment at a temperature of 00° C. for 20 minutes, the silica film layer is densified to obtain a silica film layer 5. In addition, in the figure, 1. The silica film layer 5a is shown as a sandy surface after being heated at a temperature of 200 to 400 DEG C., and the second silica film layer 5b is shown as having been coated with a solvent but not subjected to the heat treatment. As described above, since the level difference caused by the first aluminum wiring 5 is smoothed, the 21st aluminum wiring 6 without any step breaks is realized.
なお、上記−実施例においては、第1鳩目の配線がアル
ミニウムの場合を示したが、前記第1層目の配線がボ1
1シ11コンの場合は、前記最終加熱処理を窒素雰囲気
中において8□00〜1000℃の温度で、20分間、
もしくはハロゲンランプにより900〜+050℃、5
〜IO秒間行なうことが好ましい。In addition, in the above-mentioned embodiment, the case where the wiring of the first eyelet is made of aluminum is shown, but the wiring of the first layer is made of aluminum.
In the case of 1-Si-11-con, the final heat treatment is carried out in a nitrogen atmosphere at a temperature of 8□00 to 1000°C for 20 minutes.
Or 900~+050℃ with a halogen lamp, 5
It is preferable to carry out for ~10 seconds.
上記の如く形成されたシリカフィルム層5にクラックの
有無を調べることについては、シリカフィルムI95形
成後、次工程の窓開は後、第2層目のアルミニウム配線
6形成後に顕微鏡により観察L7’cが、クラックは全
く発生していないことが確認された。更に、モールド形
成後、ダイス付けの後において素子の性能を測定したが
、クラックの発生による悪影響と認められる現象は観測
されなかった。To check the presence or absence of cracks in the silica film layer 5 formed as described above, after the silica film I95 is formed, the window opening in the next step is performed, and after the second layer of aluminum wiring 6 is formed, observation L7'c is performed using a microscope. However, it was confirmed that no cracks were generated at all. Furthermore, when the performance of the device was measured after molding and after die attachment, no phenomenon that could be considered to be an adverse effect due to the occurrence of cracks was observed.
ところで、上記−実施例においては、シリカフィルム1
−はリン添加膜を使用しているが、シリカフィルムにリ
ンを添加することにより、膜内応力が緩和され、耐クラ
ツク性が向上することが確認されている。By the way, in the above-mentioned example, the silica film 1
- uses a phosphorus-added film, and it has been confirmed that by adding phosphorus to the silica film, the stress within the film is relaxed and the crack resistance is improved.
以上述べたように本発明の製造方法によれば、クラック
の生じない程度の膜厚のシリカフィルム層の塗布・焼成
を複数回繰返し、しかる後にシリカフィルムj#Iの緻
密化(density)を行なうため、シリカフィルム
層の急激な体積収縮を避けることができ、内部にクラッ
クを生ずることなく比較的厚いシリカフィルム層を形成
することができる。As described above, according to the manufacturing method of the present invention, the coating and baking of a silica film layer having a thickness that does not cause cracks is repeated multiple times, and then the density of the silica film j#I is densified. Therefore, rapid volumetric shrinkage of the silica film layer can be avoided, and a relatively thick silica film layer can be formed without causing internal cracks.
したがって、本発明方法によれば、層間絶縁−としての
特性を下げることなく、塗布法により比較的厚いシリカ
フィルム1−を形成し、これにより段差を少なくし、そ
の上に形成した配線の信頼性を向上させると共に、上層
、下層の配線間の絶縁耐力の低下等を防止し、半導体装
置の製造歩留りを向上させるという効果を有する。Therefore, according to the method of the present invention, a relatively thick silica film 1- can be formed by a coating method without deteriorating its properties as an interlayer insulation, thereby reducing the level difference and improving the reliability of the wiring formed thereon. This has the effect of improving the manufacturing yield of semiconductor devices by preventing a decrease in dielectric strength between upper and lower layer interconnects, and improving the manufacturing yield of semiconductor devices.
なお、上記一実施例において、絶縁−としてNBG膜を
用いた場合を示したが、前記絶縁模としてリンケイ酸ガ
ラス(PSG)ll!!li、ボロンリンケイ酸ガラス
(BPSG)IN、プラズマ窒化(P−8iN ) I
II等を用いても何ら問題はない。また、シリカフィル
ム層はリン添7Joll!の場合を例示したが、リンと
ボロンとを重加した溶剤も有効である。In the above embodiment, a case was shown in which an NBG film was used as an insulator, but phosphosilicate glass (PSG) was used as an insulator. ! li, boron phosphosilicate glass (BPSG) IN, plasma nitridation (P-8iN) I
There is no problem in using II or the like. In addition, the silica film layer is phosphorus-added 7Joll! Although the above case is illustrated, a solvent in which phosphorus and boron are heavily added is also effective.
また、上配実捲例では配線層にポリシリコンとアルミニ
ウム、あるいはアルミニウムを2層に設けた場合につい
て説明したが、配線層の少なくとも1mにポリサイドや
高一点金属を用いた場合もしくは、アルミニウムまたは
その他の金属を5層以上設けた多層配線にも本発明は有
効である。In addition, in the upper wiring example, we have explained the case where the wiring layer is made of polysilicon and aluminum, or two layers of aluminum, but it is also possible to use polycide or high single point metal for at least 1 m of the wiring layer, or use aluminum or other The present invention is also effective for multilayer wiring in which five or more layers of metal are provided.
第1図及び第5図は本発明の一実施例を示す半導体装置
の工程断面図、第2図は従来例を説明する半導体装置の
工程断面図である。
1・・・半導体基板
2.4・・・絶縁幌
5.6・・・金属配線
5・・・シリカフィルム層
5a・・・第17リカフイルム層
5b・・・第27リカフイルム層
7・・・クラック
以 上1 and 5 are process sectional views of a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a process sectional view of a semiconductor device illustrating a conventional example. 1... Semiconductor substrate 2.4... Insulating canopy 5.6... Metal wiring 5... Silica film layer 5a... 17th Lica film layer 5b... 27th Lica film layer 7...・Crack or higher
Claims (3)
ム層を形成する方法において、前記半導体基板上に第1
のシリカフィルム層を塗布法により形成し、前記第1の
シリカフィルム層を焼成し、かく処理された第1のシリ
カフィルム層の上に第2のシリカフィルム層を塗布法に
より形成し、前記第2のシリカフィルム層を焼成し、順
次かかる工程を複数回繰知し、しかる後に加熱処理する
工程を含むことを特徴とする半導体装置の製造方法。(1) In a method of forming a relatively thick silica film layer on one principal surface of a semiconductor substrate, a first
A silica film layer is formed by a coating method, the first silica film layer is fired, a second silica film layer is formed by a coating method on the thus treated first silica film layer, and the first silica film layer is formed by a coating method. 1. A method for manufacturing a semiconductor device, comprising the steps of firing the silica film layer of No. 2, sequentially repeating this step multiple times, and then heat-treating the silica film layer.
を特徴とする特許請求の範囲第1項記載の半導体装置の
製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the firing is performed at a temperature of 200 to 400°C.
ことを特徴とする特許請求の範囲第2項記載の半導体装
置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 2, wherein the heat treatment is performed at a higher temperature than the firing temperature.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60087027A JPH0821580B2 (en) | 1985-04-23 | 1985-04-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60087027A JPH0821580B2 (en) | 1985-04-23 | 1985-04-23 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61245540A true JPS61245540A (en) | 1986-10-31 |
JPH0821580B2 JPH0821580B2 (en) | 1996-03-04 |
Family
ID=13903470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60087027A Expired - Lifetime JPH0821580B2 (en) | 1985-04-23 | 1985-04-23 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0821580B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0226054A (en) * | 1988-07-14 | 1990-01-29 | Matsushita Electron Corp | Manufacture of semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5674930A (en) * | 1979-11-26 | 1981-06-20 | Internatl Rectifier Corp Japan Ltd | P-n junction part stabilization processing method of semiconductor device |
JPS58138052A (en) * | 1982-02-12 | 1983-08-16 | Nec Corp | Manufacture of semiconductor device |
-
1985
- 1985-04-23 JP JP60087027A patent/JPH0821580B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5674930A (en) * | 1979-11-26 | 1981-06-20 | Internatl Rectifier Corp Japan Ltd | P-n junction part stabilization processing method of semiconductor device |
JPS58138052A (en) * | 1982-02-12 | 1983-08-16 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0226054A (en) * | 1988-07-14 | 1990-01-29 | Matsushita Electron Corp | Manufacture of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPH0821580B2 (en) | 1996-03-04 |
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