JPH0669361A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH0669361A
JPH0669361A JP24127392A JP24127392A JPH0669361A JP H0669361 A JPH0669361 A JP H0669361A JP 24127392 A JP24127392 A JP 24127392A JP 24127392 A JP24127392 A JP 24127392A JP H0669361 A JPH0669361 A JP H0669361A
Authority
JP
Japan
Prior art keywords
film
insulating film
interlayer insulating
semiconductor device
phosphorus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24127392A
Other languages
Japanese (ja)
Inventor
Yoshiko Ii
由子 井伊
Masazumi Matsuura
正純 松浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP24127392A priority Critical patent/JPH0669361A/en
Publication of JPH0669361A publication Critical patent/JPH0669361A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent deposits such as phosphorus, etc., from occurring on the surface of an insulating film by providing an insulating moisture-absorption- resistant film on the interlayer insulating film doped in high concentration with hygroscopic impurities. CONSTITUTION:An applied film 3 is made as an interlayer insulating film so as to cover the first conductor pattern made on a semiconductor substrate 1. This applied film 3 can be gotten by rotationally applying spin-coat agent consisting of silanol. Moreover, this applied film 3 is doped with phosphorus about 5mol% or more in terms of, for example, P205, for prevention of cracking. Moreover, a nitride layer 4, 10-100Angstrom thick is made on this surface exposing the surface of this applied film 3 to nitrogen plasma. Deposits such as phosphoric acid, etc., can be prevented on the surface of a film by preventing the moisture absorption of the applied film.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置およびそ
の製造方法に関し、特に多層配線構造を有する半導体装
置およびその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a multilayer wiring structure and a method of manufacturing the same.

【0002】[0002]

【従来の技術】多層配線構造を実現するには、上層配線
と下層配線の間の電気的絶縁と、下層配線による凹凸の
発生を抑制するための平坦化とが必要である。その一例
として、例えばシラノールからなるスピンコート剤を回
転塗布し、150°〜450℃の熱処理により硬化させ
て塗布膜を形成し、平坦性を向上させる方法がある。
2. Description of the Related Art In order to realize a multi-layer wiring structure, it is necessary to electrically insulate between an upper layer wiring and a lower layer wiring, and to flatten the surface to prevent unevenness due to the lower layer wiring. As an example thereof, there is a method of improving the flatness by spin-coating a spin-coating agent made of silanol and curing it by heat treatment at 150 ° to 450 ° C. to form a coating film.

【0003】図2は、従来の技術による層間絶縁膜の形
成方法を説明するための装置断面図である。まず図2
(a) に示すように、素子(図示せず)が形成されたシリ
コン基板1上に第1の導電体パターン2を形成し、この
第1の導電体パターン2を覆うように基板1上に層間絶
縁膜として、シラノールからなる回転塗布膜3が形成さ
れる。次いで、図2(b) に示すように、塗布膜3上に、
第2の導電体パターン5が形成される。
FIG. 2 is a sectional view of a device for explaining a conventional method of forming an interlayer insulating film. First, Figure 2
As shown in (a), a first conductor pattern 2 is formed on a silicon substrate 1 on which elements (not shown) are formed, and a first conductor pattern 2 is formed on the substrate 1 so as to cover the first conductor pattern 2. A spin coating film 3 made of silanol is formed as an interlayer insulating film. Then, as shown in FIG. 2 (b), on the coating film 3,
The second conductor pattern 5 is formed.

【0004】上記塗布膜3を用いた平坦化方法では、下
地の凸部には薄く、凹部には厚くたまるという特性があ
り、これを層間絶縁膜の平坦化に利用しているが、厚く
たまりすぎると、後の熱処理時でクラックが発生しやす
い。そこで、クラックを抑止させるために、リンをドー
プする方法が広く用いられている。すなわち、リンをド
ープすることによってSiO2 形成時のストレスが緩和
されて膜厚の厚い部分でもクラックが生じにくくなる。
The flattening method using the coating film 3 has the characteristic that the convex portions of the base are thin and the concave portions are thick, and this is used for flattening the interlayer insulating film, but it is thickened. If it is too large, cracks tend to occur during the subsequent heat treatment. Therefore, a method of doping phosphorus is widely used to suppress cracks. That is, by doping phosphorus, the stress at the time of forming SiO2 is relieved, and cracks are less likely to occur even in a thick portion.

【0005】[0005]

【発明が解決しようとする課題】従来の半導体装置及び
その製造方法は以上のように構成されており、塗布膜に
リンをドープすることでクラックの発生を抑止してお
り、リンの添加量に比例してより厚く塗布膜を形成する
ことができ、平坦性をますます向上させることができる
が、リン濃度がP2 O5 換算で4mol %程度以上になる
と、膜形成後、吸湿作用により絶縁膜表面にリン酸等の
析出物が発生し、これがパーティクルとなって上層配線
層のパターニング不良や、配線の浸食等、信頼性不良の
原因となるため、4mol %以上は添加できず、平坦化に
は限界があるという問題点があった。
The conventional semiconductor device and the manufacturing method thereof are configured as described above, and the occurrence of cracks is suppressed by doping the coating film with phosphorus. A thicker coating film can be formed proportionately, and the flatness can be further improved. However, if the phosphorus concentration is about 4 mol% or more in terms of P2O5, the surface of the insulating film will absorb moisture after forming the film. Precipitate such as phosphoric acid is generated on the surface, which becomes particles and causes poor patterning of the upper wiring layer, erosion of wiring, and other reliability problems. Therefore, 4 mol% or more cannot be added. There was a problem that there was a limit.

【0006】この発明は、上記のような問題点を解消す
るためになされたもので、塗布膜の吸湿を抑止すること
により、膜表面にリン酸等の析出物が発生するのを防止
することができる半導体装置を得ることを目的としてお
り、さらにこの装置に適した製造方法を提供することを
目的とする。
The present invention has been made in order to solve the above-mentioned problems, and prevents the coating film from absorbing moisture to prevent the generation of precipitates such as phosphoric acid on the film surface. It is an object of the present invention to obtain a semiconductor device capable of performing the above-mentioned process, and further to provide a manufacturing method suitable for this device.

【0007】[0007]

【課題を解決するための手段】この発明に係る半導体装
置は、吸湿性を有する不純物が高濃度にドープされた層
間絶縁膜表面に薄い窒化層等の絶縁性の耐吸湿膜を備え
たものである。
A semiconductor device according to the present invention is provided with an insulating moisture-absorption-resistant film such as a thin nitride layer on the surface of an interlayer insulating film doped with a hygroscopic impurity at a high concentration. is there.

【0008】またこの発明に係る半導体装置の製造方法
は、高濃度のリン等の不純物をドープした層間絶縁膜を
窒化雰囲気中で処理してその表面に10〜100オング
ストローム程度の薄い窒化層を形成するようにしたもの
である。
In the method of manufacturing a semiconductor device according to the present invention, the interlayer insulating film doped with a high concentration of impurities such as phosphorus is processed in a nitriding atmosphere to form a thin nitride layer of about 10 to 100 angstrom on the surface thereof. It is something that is done.

【0009】[0009]

【作用】この発明においては、層間絶縁膜の表面に窒化
層等の絶縁性の膜が形成してあるので、耐吸湿性にすぐ
れており、したがって4mol %以上のリンをドープした
絶縁膜等を用いてもその表面にリン酸等の析出物による
パーティクルが発生することがない。
In the present invention, since an insulating film such as a nitride layer is formed on the surface of the interlayer insulating film, it has excellent moisture absorption resistance. Therefore, an insulating film doped with 4 mol% or more of phosphorus is used. Even if used, particles due to precipitates such as phosphoric acid do not occur on the surface.

【0010】[0010]

【実施例】実施例1.図1(a) 〜(c) は、この発明の一
実施例を説明するための概略的な装置断面図であり、図
2と同一符号は同一または相当部分を示し、4は塗布膜
3表面に形成された窒化層である。
EXAMPLES Example 1. 1 (a) to 1 (c) are schematic device sectional views for explaining an embodiment of the present invention, in which the same reference numerals as those in FIG. It is a nitride layer formed in.

【0011】次に製造方法について説明する。まず、図
1(a) に示すように、半導体基板1上に形成された第1
の導電体パターン2を覆うように、層間絶縁膜として塗
布膜3を形成する。この塗布膜3は、シラノールからな
るスピンコート剤を回転塗布することにより得られる。
またこの塗布膜3には、クラック抑止のために、リンが
例えばP2 O5 換算で4mol %程度以上ドープされてい
る。
Next, the manufacturing method will be described. First, as shown in FIG. 1 (a), a first substrate formed on a semiconductor substrate 1
A coating film 3 is formed as an interlayer insulating film so as to cover the conductor pattern 2 of. The coating film 3 is obtained by spin coating a spin coating agent made of silanol.
The coating film 3 is doped with phosphorus in an amount of, for example, about 4 mol% or more in terms of P2 O5 in order to suppress cracks.

【0012】次いで、この塗布膜3の表面を窒素のプラ
ズマにさらすことにより、その表面に10〜100オン
グストロームの厚さの窒化層が形成される(図1(b)
)。窒素プラズマにさらすには、例えば平行平板型の
電極が内部に設けられた真空チャンバを使用して、温度
300°cにおいてガス圧0.3Torrの窒化ガスを流量
1000SCCMで流しつつ、高周波電源により、周波
数400KHz,出力400Wで電極間に印加する。こ
れにより、真空チャンバー内に窒素のプラズマが発生す
る。そして図1(a) の基板1をこの窒素のプラズマの雰
囲気中に、10分間置く。このようにして形成された層
間絶縁膜3の上に、図1(c) に示すように第2の導伝電
体パターン5を形成する。
Next, the surface of the coating film 3 is exposed to nitrogen plasma to form a nitride layer having a thickness of 10 to 100 angstroms on the surface (FIG. 1 (b)).
). To expose to nitrogen plasma, for example, using a vacuum chamber in which parallel plate type electrodes are provided inside, a nitriding gas having a gas pressure of 0.3 Torr at a temperature of 300 ° C. and a flow rate of 1000 SCCM is used, and a high frequency power source is used. A voltage of 400 KHz and an output of 400 W are applied between the electrodes. As a result, nitrogen plasma is generated in the vacuum chamber. Then, the substrate 1 shown in FIG. 1A is placed in this nitrogen plasma atmosphere for 10 minutes. On the inter-layer insulation film 3 thus formed, a second conductor pattern 5 is formed as shown in FIG. 1 (c).

【0013】このように本実施例によれば、塗布膜3の
表面に耐吸湿性にすぐれた窒化層4が形成されているの
で、塗布膜に4mol %以上のリンがドープされていても
塗布膜3表面にリンの析出物が発生することはない。し
たがってクラックの発生を伴わずにより厚く塗布膜3を
形成することができ、平坦性をますます向上させること
ができる。
As described above, according to this embodiment, since the nitride layer 4 having excellent moisture absorption resistance is formed on the surface of the coating film 3, even if the coating film is doped with 4 mol% or more of phosphorus, the coating is performed. No phosphorus deposit is generated on the surface of the film 3. Therefore, the coating film 3 can be formed thicker without the occurrence of cracks, and the flatness can be further improved.

【0014】実施例2.上記第1の実施例では、層間絶
縁膜として塗布膜を用いて説明したが、この実施例では
CVD法を用いて層間絶縁膜を形成するようにしたもの
である。BPSG膜は、ボロンとリンをドープしたSi
O2 膜をCVD法(Chemical Vapor Deposition :化学
気相成長法)により堆積することで形成される。その後
CVD法で得られた膜を高温でアニールすることによ
り、液体状に変化させ、これを基板表面で流動させるこ
とによって凹凸をなめらかにする。
Example 2. In the first embodiment described above, the coating film is used as the interlayer insulating film, but in this embodiment, the interlayer insulating film is formed by using the CVD method. The BPSG film is made of Si doped with boron and phosphorus.
It is formed by depositing an O2 film by the CVD method (Chemical Vapor Deposition). After that, the film obtained by the CVD method is annealed at a high temperature to change it into a liquid state, and this is made to flow on the surface of the substrate to smooth the unevenness.

【0015】BPSG膜において、リンやボロンはシリ
カネットワークに歪みを生じさせ、SiO2 膜のガラス
転移温度を低下させる働きがあるが、この場合も、BP
SG膜のリン濃度が9mol %以上になるとリンの溶出が
おこり吸湿性が強く不安定な膜となる。そこで、BPS
G膜を高温アニールした後、表面を窒素のプラズマにさ
らすことにより、BPSG膜表面に10〜100オング
ストロームの耐吸湿性にすぐれた窒化層を形成し、リン
の溶出を防止することで上記実施例と同様の効果を奏す
ることができる。
In the BPSG film, phosphorus and boron have a function of causing strain in the silica network and lowering the glass transition temperature of the SiO2 film. In this case as well, BP is used.
When the phosphorus concentration of the SG film becomes 9 mol% or more, phosphorus is eluted and the film becomes highly hygroscopic and unstable. So BPS
After the G film is annealed at a high temperature, the surface is exposed to a plasma of nitrogen to form a nitride layer having excellent moisture absorption resistance of 10 to 100 angstrom on the surface of the BPSG film to prevent the elution of phosphorus. The same effect as can be obtained.

【0016】なお上記実施例では、層間絶縁膜にドープ
される吸湿性を有する不純物としてリンやボロンを例と
して説明したが、これら以外にも吸湿性を有する不純物
をドープされた層間絶縁膜を用いる場合においても同様
の効果を奏することができる。
In the above embodiment, phosphorus and boron are described as an example of the hygroscopic impurities to be doped into the interlayer insulating film, but an interlayer insulating film doped with other hygroscopic impurities is also used. Even in such a case, the same effect can be obtained.

【0017】[0017]

【発明の効果】以上のように、この発明によれば、層間
絶縁膜の表面に耐吸湿性の良い窒化層を形成したので、
例えば4mol %以上のリンをドープした吸湿性の高い層
間絶縁膜を用いても膜表面にリンの析出物が発生するこ
とがなく、信頼性の高い半導体装置を得ることができる
効果がある。
As described above, according to the present invention, since the nitride layer having good moisture absorption resistance is formed on the surface of the interlayer insulating film,
For example, even if an interlayer insulating film having a high hygroscopic property doped with 4 mol% or more of phosphorus is used, phosphorus deposits are not generated on the film surface, and a highly reliable semiconductor device can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の実施例による半導体装置の製造工程
を示す装置断面図である。
FIG. 1 is a device sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

【図2】従来の半導体装置の製造工程を示す断面図であ
る。
FIG. 2 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 第1の導電体パターン 3 塗布膜 4 窒化層 5 第2の導電体パターン 1 Silicon Substrate 2 First Conductor Pattern 3 Coating Film 4 Nitride Layer 5 Second Conductor Pattern

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 基板上に配置された下層配線層と、該下
層配線層上に層間絶縁膜を介して配置された上層配線層
とを備えた半導体装置において、 吸湿性を有する不純物が高濃度にドープされた層間絶縁
膜上に、絶縁性の耐吸湿膜を設けたことを特徴とする半
導体装置。
1. A semiconductor device comprising a lower wiring layer arranged on a substrate and an upper wiring layer arranged on the lower wiring layer via an interlayer insulating film, wherein a high hygroscopic impurity is contained in the semiconductor device. A semiconductor device, wherein an insulating moisture-absorption-resistant film is provided on the interlayer insulating film doped with.
【請求項2】 基板上に配置された下層配線層上に層間
絶縁膜を形成した後上層配線層を形成する工程を有する
半導体装置の製造方法において、 基板上に形成された下層配線層上に吸湿性を有する不純
物を高濃度ドープした層間絶縁膜を形成する工程と、 上記層間絶縁膜の表面に絶縁性の耐吸湿膜を形成する工
程とを含むことを特徴とする半導体装置の製造方法。
2. A method of manufacturing a semiconductor device, comprising the step of forming an upper layer wiring layer after forming an interlayer insulating film on a lower layer wiring layer arranged on a substrate, wherein a lower layer wiring layer formed on the substrate is formed. A method of manufacturing a semiconductor device, comprising: a step of forming an interlayer insulating film that is highly doped with an impurity having a hygroscopic property; and a step of forming an insulating hygroscopic resistant film on the surface of the interlayer insulating film.
【請求項3】 請求項2記載の半導体装置の製造方法に
おいて、 上記絶縁性の耐吸湿膜を形成する工程は、 上記層間絶縁膜を窒化雰囲気中にさらすことにより層間
絶縁膜表面を窒化層とするものであることを特徴とする
半導体装置の製造方法。
3. The method for manufacturing a semiconductor device according to claim 2, wherein in the step of forming the insulating moisture-absorption-resistant film, the surface of the interlayer insulating film is formed into a nitride layer by exposing the interlayer insulating film to a nitriding atmosphere. A method of manufacturing a semiconductor device, comprising:
JP24127392A 1992-08-17 1992-08-17 Semiconductor device and its manufacture Pending JPH0669361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24127392A JPH0669361A (en) 1992-08-17 1992-08-17 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24127392A JPH0669361A (en) 1992-08-17 1992-08-17 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH0669361A true JPH0669361A (en) 1994-03-11

Family

ID=17071809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24127392A Pending JPH0669361A (en) 1992-08-17 1992-08-17 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH0669361A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100322884B1 (en) * 1999-07-01 2002-02-08 박종섭 Method for fabricalting conductive wiring of a semiconductor device
US8368237B2 (en) 2007-07-12 2013-02-05 Robert Bosch Gmbh Starter device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100322884B1 (en) * 1999-07-01 2002-02-08 박종섭 Method for fabricalting conductive wiring of a semiconductor device
US8368237B2 (en) 2007-07-12 2013-02-05 Robert Bosch Gmbh Starter device

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