KR950009814B1 - Capacitor structure - Google Patents

Capacitor structure Download PDF

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KR950009814B1
KR950009814B1 KR1019930001490A KR930001490A KR950009814B1 KR 950009814 B1 KR950009814 B1 KR 950009814B1 KR 1019930001490 A KR1019930001490 A KR 1019930001490A KR 930001490 A KR930001490 A KR 930001490A KR 950009814 B1 KR950009814 B1 KR 950009814B1
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South Korea
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oxide film
tantalum oxide
stress
capacitor
gas atmosphere
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KR1019930001490A
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Korean (ko)
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KR940020547A (en
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김현명
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금성일렉트론주식회사
문정환
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

(i) forming a polysilicon(21) of 1500-5000 angstrom thickness dopted with P on a silicon substrate(20) by using the low pressure CVD process at 500-620 deg.C; (ii) forming a tantalum oxide film(22) of 100 angstrom in thickness on the polysilicon(21) by performing heat treatment at 500-620 deg.C under Ta(OET)5 and O2 gas atmosphere of 500 Torr presure; (iii) removing carbon component of the tantalum oxide film by performing heat treatment at 300 deg.C for 30 mins. under oxygen gas atmosphere including 9% ozone gas; (iv) performing a high density treatment it at 800 deg.C under O2 or N2O gas atmosphere; depositing a TiN(23) having the compressive stress on the tantalum oxide film(22); and depositing a tungsten(24) having the tensile stress on the TiN(23). The net stress of tantalum oxide film is minimized by using two materials of the different stress as respective electrode.

Description

캐패시터의 구조 및 그 제조 방법Capacitor Structure and Manufacturing Method Thereof

제1도는 종래 캐패시터 제조를 설명하기 위한 공정 단면도.1 is a cross-sectional view for explaining a conventional capacitor manufacturing.

제2도는 본 발명 캐패시터 제조를 설명하기 위한 공정 단면도.2 is a cross-sectional view for explaining the manufacture of the capacitor of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

20 : 기판 21 : 다결정 실리콘20: substrate 21: polycrystalline silicon

22 : 탄탈륨 산화막 23 : 질화 티타늄22: tantalum oxide film 23: titanium nitride

24 : 텅스텐24: tungsten

본 발명은 반도체 소자(Semiconductor Cell)에 사용하는 캐패시터(Capacitor)에 관한 것으로 특히, 캐패시터의 상위 전극 특성을 향상시킬 수 있는 캐패시터의 구조 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor for use in a semiconductor cell, and more particularly, to a structure of a capacitor capable of improving upper electrode characteristics of a capacitor and a method of manufacturing the same.

종래 기술은 제1a도와 같이 실리콘(Silicon) 기판(1) 위에 인(P31)이 도우핑(Deping)된 다결정 실리콘(2)을 500℃-650℃의 온도에서 저압 화학 기상 증착법(LPCVD)을 이용하여 면저항이 100Ω/□-200Ω/□으로 되도록 1500Å-5000Å두께만큼 형성한다.In the prior art, low-pressure chemical vapor deposition (LPCVD) is performed on a polycrystalline silicon (2) doped with phosphorus (P 31 ) on a silicon substrate (1) as shown in FIG. By using 1500Å-5000Å of thickness so that the sheet resistance becomes 100Ω / □ -200Ω / □.

다음, b도와 같이 인이 도우핑된 다결정 실리콘(2) 위에 Ta(OET)5및 산소 가스를 각각 0.1ml/min, 3SLPM 흘려주면서 500mTorr의 압력 및 430℃의 온도에서 탄탈륨산화막(Ta2O5)(3)을 100Å두께 만큼 형성한후 c도와 같이 탄탈륨 산화막(3)을 5%-9% 오존(O3) 분위기 및 300℃의 온도에서 서서히 열처리하므로서 탄탈륨 산화막(3)중에 포함되어 있는 탄소 성분등을 제거한다.Next, Ta (OET) 5 and oxygen gas were flowed on the phosphorus-doped polycrystalline silicon 2 by 0.1 ml / min and 3SLPM, respectively, as shown in b, at a pressure of 500 mTorr and a temperature of 430 ° C. (Ta 2 O 5 ) And the carbon contained in the tantalum oxide film 3 by gradually heat-treating the tantalum oxide film 3 in a 5% -9% ozone (O 3 ) atmosphere and a temperature of 300 ° C as shown in FIG. Remove ingredients.

이어서, O2분위기 및 800℃의 온도에서 고밀도화 하여 탄탈륨 산화막(3)의 누설 전류 특성을 개선할 수 있는 막질을 얻어 내고, 표면에 스퍼터(Sputter)를 이용하여 극판(TiN 또는 W)(4)을 형성한다.Subsequently, a film quality capable of improving the leakage current characteristics of the tantalum oxide film 3 by densification in an O 2 atmosphere and a temperature of 800 ° C. is obtained, and a plate (TiN or W) 4 is formed on the surface by using a sputter. To form.

그러나, 이와 같은 종래의 기술에 있어서는 극판(4)을 TiN 또는 W등을 사용하여 단일 금속층을 형성하므로써 이후 열 공정 특히, BPSG(Boron Phosphorus Silicate Glass) 플로우(Flow) 열 공정, 콘택(Contact) 열 공정 등에서 받는 열에 의해 TiN 또는 W의 스트레스(Stress)를 아주 얇은 박막인 탄탈륨 산화막(3)이 그대로 전달 받으므로 탄탈륨 산화막(3)의 전류 특성이 열화(Degradation)된다.However, in such a conventional technique, the electrode plate 4 is formed using TiN or W to form a single metal layer, and then a thermal process, in particular, a BPSG (Boron Phosphorus Silicate Glass) flow heat process and a contact heat process. Since the tantalum oxide film 3, which is a very thin film, is transmitted as it is due to the heat received in the process or the like, the current characteristic of the tantalum oxide film 3 is degraded.

본 발명은 이와 같은 종래의 결점을 감안하여 안출한 것으로, 상위전극을 금속으로 이루어지는 이중 구조로 형성시켜 탄탈륨 산화막의 열화 특성을 개선할 수 있는 캐패시터 구조 및 그 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described drawbacks, and an object thereof is to provide a capacitor structure and a method of manufacturing the same, which can improve the deterioration characteristics of a tantalum oxide film by forming the upper electrode in a double structure made of metal.

이하에서 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.

제2도는 본 발명의 공정 단면도로, 제2a도와 같이 실리콘 기판(20)위에 인이 도우핑된 다결정 실리콘(21)을 500℃-620℃의 온도에서 저압 화학 기상 증착법을 이용하여 1500Å-5000Å두께 만큼 형성한다.FIG. 2 is a cross-sectional view of the process of the present invention, in which the polycrystalline silicon 21 doped with phosphorus on the silicon substrate 20 as shown in FIG. 2a is subjected to low pressure chemical vapor deposition at a temperature of 500 ° C.-620 ° C. Form as much.

다음, b도와 같이 인이 도우핑된 다결정 실리콘(21) 위에 Ta(OET)5및 산소 가스를 각각 0.1ml/min, 3SLPM 흘려주면서 500mTorr의 압력 및 500℃-620℃의 온도에서 탄탈륨 산화막(22)을 100Å두께 만큼 형성한 후 c도와 같이 탄탈륨 산화막(22)을 9% 오존 가스가 포함된 산소 분위기 및 300℃의 온도에서 약 30분 동안 열처리하므로서 탄탈륨 산화막(22)중에 포함되어 있는 탄소 성분등을 제거한다.Next, the tantalum oxide film 22 at a pressure of 500 mTorr and a temperature of 500 ° C. to 620 ° C. is flowed by flowing Ta (OET) 5 and oxygen gas at 0.1 ml / min and 3 SLPM on the phosphorus-doped polycrystalline silicon 21 as shown in FIG. ) And the carbon component contained in the tantalum oxide film 22 by heat-treating the tantalum oxide film 22 for about 30 minutes in an oxygen atmosphere containing 9% ozone gas and at a temperature of 300 ° C. as shown in FIG. Remove it.

이어서, O2또는 N2O 분위기 및 800℃의 온도에서 고밀도화 한 후 탄탈륨 산화막(22) 위에 컴프레시브(Compressive) 응력을 가지는 물질로써 질화 티타늄(TiN)(23)을 증착하고, 그 질화 티타늄(23) 위에 텐사일(Tensile)응력을 갖는 물질로써 텅스텐(W)(24)을 저압 화학 기상 증착법을 이용하여 증착 하므로써 탄탈륨 산화막(22)이 받는 네트 스트레스(Net Stress)를 최소화한다.Subsequently, after densification in an O 2 or N 2 O atmosphere and a temperature of 800 ° C., titanium nitride (TiN) 23 is deposited on the tantalum oxide film 22 as a material having a compressive stress, and the titanium nitride The net stress of the tantalum oxide layer 22 is minimized by depositing tungsten (W) 24 as a material having a tensile stress on the layer 23 using low pressure chemical vapor deposition.

이상에서 설명한 바와 같이 본 발명은 탄탈륨 산화막(22)위에 질화 티타늄(23) 및 텅스텐(24)을 차례로 형성하여 반도체 소자에 사용되는 통상적인 캐패시터의 상위 전극을 형성하므로써 탄탈륨 산화막(22)의 열화가 억제되므로 탄탈륨 산화막(22)의 누설 전류 특성이 개선되는 효과가 있다.As described above, in the present invention, the titanium nitride 23 and the tungsten 24 are sequentially formed on the tantalum oxide film 22 to form an upper electrode of a conventional capacitor used in a semiconductor device, thereby deteriorating the tantalum oxide film 22. Since it is suppressed, the leakage current characteristic of the tantalum oxide film 22 is improved.

Claims (5)

기판(20)위에 다결정 실리콘(21) 및 탄탈륨 산화막(22)이 형성된 캐패시터에 있어서, 탄탈륨 산화막(22) 위에 응력이 서로 다른 두 물질이 차례로 형성되어 전극으로 사용되며 탄탈륨 산화막(22)의 열화를 억제하는 캐패시터의 구조.In the capacitor in which the polycrystalline silicon 21 and the tantalum oxide film 22 are formed on the substrate 20, two materials having different stresses are sequentially formed on the tantalum oxide film 22 to be used as electrodes, thereby deteriorating the tantalum oxide film 22. Capacitor structure to suppress. 제1항에 있어서, 응력이 서로 다른 두 물질로 질화 티타늄(23)의 텅스텐(24)을 사용하는 캐패시터의 구조.The structure of a capacitor according to claim 1, wherein tungsten (24) of titanium nitride (23) is used as two materials having different stresses. 기판(20)위에 다결정 실리콘(21), 탄탈륨 산화막(22)을 차례로 형성한 후 탄탈륨 산화막(22) 위에 컴프레시브 응력을 가지는 물질 및 텐사일 응력을 갖는 물질을 차례로 증착하여 전극을 형성하는 캐패시터의 제조방법.A capacitor which forms polycrystalline silicon 21 and tantalum oxide film 22 on the substrate 20 in turn, and then deposits a material having a compressive stress and a material having a tensyl stress on the tantalum oxide film 22 in order to form an electrode. Manufacturing method. 제3항에 있어서, 컴프레시브 응력을 갖는 물질로 질화 티타늄(23)을 사용하는 캐패시터의 제조방법.4. A method according to claim 3, wherein titanium nitride (23) is used as the material having a compressive stress. 제3항에 있어서, 텐사일 응력을 갖는 물질로 텅스텐(24)을 사용하는 캐패시터의 제조방법.The method of manufacturing a capacitor according to claim 3, wherein tungsten (24) is used as the material having tensyl stress.
KR1019930001490A 1993-02-04 1993-02-04 Capacitor structure KR950009814B1 (en)

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KR950009814B1 true KR950009814B1 (en) 1995-08-28

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