JPH0351094B2 - - Google Patents
Info
- Publication number
- JPH0351094B2 JPH0351094B2 JP56101895A JP10189581A JPH0351094B2 JP H0351094 B2 JPH0351094 B2 JP H0351094B2 JP 56101895 A JP56101895 A JP 56101895A JP 10189581 A JP10189581 A JP 10189581A JP H0351094 B2 JPH0351094 B2 JP H0351094B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate insulating
- thin film
- silane
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 28
- 239000010409 thin film Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 18
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 11
- 229910000077 silane Inorganic materials 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 238000000354 decomposition reaction Methods 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- -1 etc. are used Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】
本発明は薄膜トランジスタの製造方法に係り、
特に水素化無定形シリコンを用いた薄膜トランジ
スタの製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a thin film transistor,
In particular, the present invention relates to a method of manufacturing a thin film transistor using hydrogenated amorphous silicon.
従来薄膜トランジスタとしては半導体層として
CdS、CdSe、ａ−Si等が用いられ、ゲート絶縁
膜としてSiO2、Si3N4等が用いられている。 Conventionally, thin film transistors are used as a semiconductor layer.
CdS, CdSe, a-Si, etc. are used, and SiO 2 , Si 3 N 4 , etc. are used as the gate insulating film.
半導体層としてCdSを用い、ゲート絶縁膜とし
てSiO2を用いた場合について説明すると、ガラ
ス基板上にAl等の金属を蒸着後パターニングし、
ゲート電極を形成した基板上にゲート絶縁膜を真
空蒸着、スパツタリング、CVD等により被着形
成する。 To explain the case where CdS is used as the semiconductor layer and SiO 2 is used as the gate insulating film, metal such as Al is deposited on a glass substrate and then patterned.
A gate insulating film is deposited on the substrate on which the gate electrode is formed by vacuum evaporation, sputtering, CVD, or the like.
次いで、ゲート絶縁膜上に真空蒸着、スパツタ
リング等によりCdS等の半導体層を形成してい
た。しかしこの方法では、ゲート絶縁膜と半導体
層が連続して形成することができないので、ゲー
ト絶縁膜を形成した後、基板をゲート絶縁膜形成
装置から取出し、次いで半導体層形成装置にセツ
トして半導体層を形成するものである。 Next, a semiconductor layer such as CdS is formed on the gate insulating film by vacuum evaporation, sputtering, or the like. However, with this method, the gate insulating film and the semiconductor layer cannot be formed continuously, so after forming the gate insulating film, the substrate is taken out of the gate insulating film forming apparatus, and then set in the semiconductor layer forming apparatus to form the semiconductor layer. It forms a layer.
この方法では、絶縁膜の形成とその動作層であ
る半導体膜の形成は異なる工程により行なわれる
ので、これらの工程中で絶縁膜中で電荷トラツプ
として働き、トランジスタ動作点のドリフトを生
じるといつた不都合の原因となるアルカリ・イオ
ン等の不純物による絶縁膜の汚染は避け得ないと
いつた欠点がある。 In this method, the formation of the insulating film and the formation of the semiconductor film, which is its operating layer, are performed in different steps, so it is possible that charges may act as charge traps in the insulating film during these steps, causing a drift in the transistor operating point. A drawback is that the insulating film is unavoidably contaminated by impurities such as alkali ions, which causes problems.
また、これら絶縁膜と半導体層の形成温度に相
違がある場合には、両者の熱的性質の相違により
その境界面には大きなひずみが生じ、多くの欠陥
が生成されるという欠点がある。 Furthermore, if there is a difference in the formation temperature of the insulating film and the semiconductor layer, there is a drawback that a large strain is generated at the interface due to the difference in thermal properties between the two, and many defects are generated.
さらに、薄膜トランジスタに用いられる半導体
材料は熱的に極めて不安定であり、その絶縁膜ゲ
ート形成の工程も自ずと限られてしまうという不
都合が生じていた。 Furthermore, the semiconductor material used in thin film transistors is extremely unstable thermally, and the process for forming the insulating film gate is naturally limited.
第１図はゲート絶縁膜としてSiO2、半導体層
としてシランのグロー放電により形成したアモル
フアスシリコン（α−Si）を用いてガラス基板上
に薄膜トランジスタを形成する際、従来工程、即
ちSiO2膜形成後、一度真空をやぶり大気にさら
した後α−Si層を形成した、薄膜トランジスタ
（TFT）の特性を示したものである。縦軸はドレ
イン電流IDＡ、横軸はゲート電圧Ｖを示す。曲線
のNOはゲート電圧の変化によるドレイン電流の
変化を調べた順番を示し、測定する毎にその動作
点が大幅に変動するような不安定な薄膜トランジ
スタしか得られていない。 Figure 1 shows the conventional process of forming a SiO 2 film when forming a thin film transistor on a glass substrate using SiO 2 as the gate insulating film and amorphous silicon (α-Si) formed by silane glow discharge as the semiconductor layer. This shows the characteristics of a thin film transistor (TFT) in which an α-Si layer was formed after breaking the vacuum and exposing it to the atmosphere. The vertical axis shows the drain current IDA , and the horizontal axis shows the gate voltage V. The N O of the curve indicates the order in which changes in drain current due to changes in gate voltage were investigated, and only unstable thin film transistors whose operating points fluctuated significantly each time they were measured were obtained.
本発明は上述の点に鑑みなされたもので、水素
化無定形シリコンを用いた薄膜トランジスタのゲ
ート絶縁膜を、同一の連続した工程により形成す
ることでアルカリからの汚染をなくし、かつ、両
境界面でのひずみを少なくすることにより欠陥を
抑制し動作点変動のない高性能薄膜トランジスタ
を製造する方法を提供するものである。 The present invention was made in view of the above points, and it eliminates contamination from alkali by forming the gate insulating film of a thin film transistor using hydrogenated amorphous silicon in the same continuous process, and also eliminates contamination from both interfaces. The present invention provides a method for manufacturing high-performance thin film transistors with no operating point fluctuations by suppressing defects by reducing strain in the semiconductor device.
すなわち、本発明の特徴とするところはゲート
電極、ゲート絶縁膜、半導体層及びソース・ドレ
イン電極をガラス基板上に形成する薄膜トランジ
スタの製造方法において、前記ゲート絶縁膜と前
記半導体膜の形成に際し、真空槽中に酸素、酸素
と窒素を含む化合物もしくは混合ガス、窒素を含
むガスのいずれかとシラン（SiH4）とを混合し
た混合ガスを導入して、グロー放電分解法により
前記ゲート絶縁膜を形成し、また同一真空槽中に
シランもしくはドーパントを含むシランを導入し
て、グロー放電分解法により前記半導体層を形成
し、且つ該ゲート絶縁膜と該半導体層は一方が上
層に他方が下層になるようにその成膜時の真空を
破ることなく連続して積層形成した薄膜トランジ
スタの製造方法にある。 That is, the present invention is characterized by a method for manufacturing a thin film transistor in which a gate electrode, a gate insulating film, a semiconductor layer, and a source/drain electrode are formed on a glass substrate. The gate insulating film is formed by a glow discharge decomposition method by introducing oxygen, a compound or mixed gas containing oxygen and nitrogen, or a mixed gas of a nitrogen-containing gas and silane (SiH 4 ) into the tank. In addition, silane or silane containing a dopant is introduced into the same vacuum chamber, and the semiconductor layer is formed by a glow discharge decomposition method, and the gate insulating film and the semiconductor layer are arranged such that one is an upper layer and the other is a lower layer. The present invention provides a method for manufacturing a thin film transistor in which layers are successively formed without breaking the vacuum during film formation.
実施例
第２図にグロー放電分解装置の概略図を示す。
１は真空槽、２は真空ポンプ、３は陽極、４は陰
極、５はゲート電極が形成された基板、６は高周
波発振器、７は基板加熱ヒータ、８はアルゴンあ
るいは水素で希釈されたシラン（SiH4）、９はア
ルゴンで希釈された酸素である。Embodiment FIG. 2 shows a schematic diagram of a glow discharge decomposition apparatus.
1 is a vacuum chamber, 2 is a vacuum pump, 3 is an anode, 4 is a cathode, 5 is a substrate on which a gate electrode is formed, 6 is a high frequency oscillator, 7 is a substrate heater, 8 is silane diluted with argon or hydrogen ( SiH 4 ), 9 is oxygen diluted with argon.
まず、真空槽１を十分に排気した後ヒータ７に
よりゲート電極が形成された基板５を150〜200℃
に加熱する。その後ボンベ８よりシランを0.05〜
0.1Torr導入した後、ボンベ９から酸素をその５
〜10％体積導入し、高周波発振器６より５〜20W
の電力を投入すると、陽極３、陰極４間に放電が
開始され、ゲート電極が形成されている基板５上
にSiO2が分解、堆積する。 First, after the vacuum chamber 1 is sufficiently evacuated, the substrate 5 on which the gate electrode is formed is heated to 150 to 200°C using the heater 7.
Heat to. After that, add silane from cylinder 8 to 0.05~
After introducing 0.1Torr, oxygen from cylinder 9
~10% volume introduced, 5~20W from high frequency oscillator 6
When power is applied, a discharge is started between the anode 3 and the cathode 4, and SiO 2 is decomposed and deposited on the substrate 5 on which the gate electrode is formed.
このSiO2を所望の膜厚まで堆積後、ボンベイ
９からの酸素の導入を止めると、この形成された
SiO2上に今度は水素化された無定形シリコンの
堆積が始まり、これを所望の膜厚まで堆積させ
る。 After depositing this SiO 2 to the desired thickness, when the introduction of oxygen from Bombay 9 is stopped, the formed
Deposition of hydrogenated amorphous silicon now begins on the SiO 2 and is deposited to the desired thickness.
その後、基板を真空槽外に取り出し、ソース・
ドレイン電極を形成し、薄膜トランジスタとす
る。 After that, take the board out of the vacuum chamber and put it in the source
A drain electrode is formed to form a thin film transistor.
このようにして製造された薄膜トランジスタの
特性の一例を第３図に示す。前述の第１図と同様
縦軸にドレイン電流、横軸にゲート電圧でブロツ
トしたものである。このプロセスで作製したもの
では、ここに観ろれるように何度測定を繰り返し
ても、動作点変動のない良好な特性をもつた薄膜
トランジスタが得られる。 An example of the characteristics of the thin film transistor manufactured in this manner is shown in FIG. As in FIG. 1 described above, the drain current is plotted on the vertical axis and the gate voltage is plotted on the horizontal axis. As can be seen here, thin film transistors manufactured using this process have good characteristics with no fluctuation in operating point no matter how many times the measurements are repeated.
なお、実施例においてはSiO2の形成にシラン
と酸素のガスを混合したものを用いることを示し
たが、SiO2形成には酸素の他亜酸化窒素N2O等
でも良い。 In addition, in the embodiment, it is shown that a mixture of silane and oxygen gas is used to form SiO 2 , but nitrous oxide N 2 O or the like other than oxygen may be used to form SiO 2 .
また、絶縁膜としてはSi3N4でも良くこの場合
には、シランとアンモニアNH3の混合ガスを用
いれば良い。 Further, the insulating film may be made of Si 3 N 4 , and in this case, a mixed gas of silane and ammonia NH 3 may be used.
更に、このSiO2と水素化無定形シリコンの製
造の順は逆でも良く、その場合にはソース・ドレ
イン電極をまず基板上に形成しておけば良い。 Furthermore, the order of manufacturing this SiO 2 and hydrogenated amorphous silicon may be reversed, in which case the source/drain electrodes may be formed on the substrate first.
本発明によれば、薄膜トランジスタの動作層と
絶縁ゲート膜が同一工程で製造できるので、不純
物による汚染がなく境界面での歪みが少なくな
り、動作点変動のない高性能トランジスタを製造
することができる。 According to the present invention, since the active layer and the insulated gate film of a thin film transistor can be manufactured in the same process, there is no contamination by impurities, distortion at the interface is reduced, and a high-performance transistor without operating point fluctuation can be manufactured. .
第１図は従来の絶縁ゲートを異なる工程で形成
したときの薄膜トランジスタの特性を示すグラ
フ、第２図は、グロー放電分解装置の概略図、第
３図は、本発明の絶縁ゲートと半導体層とを同一
工程で形成したときの薄膜トランジスタの特性を
示すグラフである。
Fig. 1 is a graph showing the characteristics of thin film transistors when conventional insulated gates are formed in different steps, Fig. 2 is a schematic diagram of a glow discharge decomposition device, and Fig. 3 is a graph showing the characteristics of thin film transistors formed using conventional insulated gates and semiconductor layers. 3 is a graph showing characteristics of thin film transistors formed in the same process.
Claims (1)
ース・ドレイン電極をガラス基板上に形成する薄
膜トランジスタの製造方法において、 前記ゲート絶縁膜と前記半導体膜の形成に際
し、真空槽中に酸素、酸素と窒素を含む化合物も
しくは混合ガス、窒素を含むガスのいずれかとシ
ラン（SiH4）とを混合した混合ガスを導入して、
グロー放電分解法により前記ゲート絶縁膜を形成
し、また同一真空槽中にシランもしくはドーパン
トを含むシランを導入して、グロー放電分解法に
より前記半導体層を形成し、且つ該ゲート絶縁膜
と該半導体層は一方が上層に他方が下層になるよ
うにその成膜時の真空を破ることなく連続して積
層形成することを特徴とした薄膜トランジスタの
製造方法。[Scope of Claims] 1. A method for manufacturing a thin film transistor in which a gate electrode, a gate insulating film, a semiconductor layer, and a source/drain electrode are formed on a glass substrate, including the steps of: forming the gate insulating film and the semiconductor film in a vacuum chamber; Introducing oxygen, a compound or mixed gas containing oxygen and nitrogen, or a mixed gas consisting of a gas containing nitrogen and silane (SiH 4 ),
The gate insulating film is formed by a glow discharge decomposition method, and the semiconductor layer is formed by a glow discharge decomposition method by introducing silane or silane containing a dopant into the same vacuum chamber, and the gate insulating film and the semiconductor are formed by a glow discharge decomposition method. A method for manufacturing a thin film transistor, characterized in that the layers are successively stacked such that one layer is an upper layer and the other is a lower layer without breaking the vacuum during film formation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10189581A JPS583289A (en) | 1981-06-30 | 1981-06-30 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10189581A JPS583289A (en) | 1981-06-30 | 1981-06-30 | Manufacture of thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS583289A JPS583289A (en) | 1983-01-10 |
| JPH0351094B2 true JPH0351094B2 (en) | 1991-08-05 |
Family
ID=14312650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10189581A Granted JPS583289A (en) | 1981-06-30 | 1981-06-30 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583289A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60166435A (en) * | 1984-02-09 | 1985-08-29 | Toyobo Co Ltd | Oriented polyester film |
| JPH0682839B2 (en) * | 1984-08-21 | 1994-10-19 | セイコー電子工業株式会社 | Manufacturing method of display panel |
| JPS61179721A (en) * | 1985-02-05 | 1986-08-12 | Toyobo Co Ltd | Oriented polyester film |
| JPS61237622A (en) * | 1985-04-16 | 1986-10-22 | Teijin Ltd | Polyester film |
| JPS6292371A (en) * | 1985-10-18 | 1987-04-27 | Hitachi Ltd | Thin-film transistor and manufacture thereof |
| JPS6375028A (en) * | 1986-09-18 | 1988-04-05 | Toray Ind Inc | Base film for magnetic recording medium |
| JPH0659679B2 (en) * | 1989-09-01 | 1994-08-10 | 東レ株式会社 | Biaxially oriented thermoplastic resin film |
| EP0608633B1 (en) * | 1993-01-28 | 1999-03-03 | Applied Materials, Inc. | Method for multilayer CVD processing in a single chamber |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5667751U (en) * | 1979-10-29 | 1981-06-05 |
-
1981
- 1981-06-30 JP JP10189581A patent/JPS583289A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS583289A (en) | 1983-01-10 |
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