KR100445410B1 - METHOD FOR FABRICATING BIT LINE OF SEMICONDUCTOR DEVICE USING CVD-Ti LAYER, CVD-TiN LAYER, AND TUNGSTEN LAYER HAVING SPECIFIC RESISTANCE LOWER THAN SPECIFIC RESISTANCE OF TUNGSTEN SILICIDE LAYER - Google Patents

METHOD FOR FABRICATING BIT LINE OF SEMICONDUCTOR DEVICE USING CVD-Ti LAYER, CVD-TiN LAYER, AND TUNGSTEN LAYER HAVING SPECIFIC RESISTANCE LOWER THAN SPECIFIC RESISTANCE OF TUNGSTEN SILICIDE LAYER Download PDF

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KR100445410B1
KR100445410B1 KR1019970030256A KR19970030256A KR100445410B1 KR 100445410 B1 KR100445410 B1 KR 100445410B1 KR 1019970030256 A KR1019970030256 A KR 1019970030256A KR 19970030256 A KR19970030256 A KR 19970030256A KR 100445410 B1 KR100445410 B1 KR 100445410B1
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layer
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bit line
semiconductor device
tungsten
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KR19990006034A (en
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김정태
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract

PURPOSE: A method for fabricating a bit line of a semiconductor device is provided to improve thermal stability in a post-process by forming the bit line with a CVD-Ti layer, a CVD-TiN layer, and a tungsten layer. CONSTITUTION: A lower CVD-Ti layer(11) is formed on a semiconductor substrate(1) by using a PECVD method. A lower CVD-TiN layer is deposited thereon by using a thermal CVD method. An upper CVD-Ti layer(13) is formed thereon and a thermal process is performed. An upper CVD-TiN layer is deposited thereon by using a CVD method. A tungsten layer pattern is formed thereon.

Description

반도체소자의 비트라인 제조방법Bit line manufacturing method of semiconductor device

본 발명은 반도체소자의 비트라인 제조방법에 관한 것으로서, 특히 화학기상 증착(Chemical Vapor Deposition; 이하 CVD라 칭함)법으로 Ti 및 TiN을 이중층으로 형성하고 그 상부에 W층을 형성하여 고온 열안정성이 우수한 반도체소자의 비트라인 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bit line of a semiconductor device, and in particular, Ti and TiN are formed as a double layer by chemical vapor deposition (CVD), and a W layer is formed thereon to provide high temperature thermal stability. An excellent method of manufacturing a bit line of a semiconductor device.

최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 이러한 미세 패턴의 분해능은 축소노광장치(stepper)의 광원 파장 및 공정 변수에 비례하고, 축소노광장치의 렌즈 구경(numerical aperture; NA)에 반비례한다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern forming technology, and the resolution of these fine patterns is proportional to the light source wavelength and process variables of the stepper, and the lens aperture of the miniature exposure device ( inversely proportional to the numerical aperture (NA).

따라서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되는데, 파장이 각각 436 및 365nm인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이며, 0.5㎛ 이하의 미세 패턴을 형성하기 위해서는 파장이 작은 원자외선(deep ultra violet), 예를들어 파장이 248nm인 KrF 레이저나 193nm인 ArF 레이저를 광원으로 사용하는 축소노광장치를 이용하고, 더욱 미세한 패턴 형성을 위하여 X-선이나 전자빔을 광원으로 이용하기도 한다.Therefore, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. G-line and i-line reduced exposure apparatuses having wavelengths of 436 and 365 nm, respectively, have a process resolution of about 0.7 and 0.5 μm, respectively. In order to form a fine pattern of 0.5 μm or less, a reduced exposure apparatus using deep ultra violet, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used. X-rays or electron beams may be used as light sources to form fine patterns.

일반적으로 반도체소자는 각각의 소자들을 형성한 후, 소자의 최상층에는 각각의 소자에 전압을 인가하는 전원선등의 금속배선이 형성된다. 이러한 금속배선으로는 다른 재료들에 비해 증착 공정이 간단하고, 저저항의 특성을 갖는 Al 계열 금속이 주로 사용되며, 저항의 감소나 열적 안정성을 향상시키기 위하여 W과의 적층구조로 형성하기도 한다.In general, after the semiconductor devices are formed with respective devices, metal wiring such as a power supply line for applying a voltage to each device is formed on the top layer of the device. As the metal wiring, the deposition process is simpler than other materials, and an Al-based metal having low resistance is mainly used. In order to reduce resistance or improve thermal stability, the metal wiring may be formed in a laminated structure with W.

더욱이 소자 형성의 초기 단계에 형성되는 비트라인은 저저항을 물론 열적 안정성도 중요한 고려 요인이되는데, 1기가 DRAM 이상의 초고집적 반도체소자에서의 비트라인 콘택은 약 0.1-0.2㎛로 매우 미세하다.In addition, the bit line formed in the initial stage of device formation is an important consideration factor, as well as low resistance, the bit line contact in the ultra-high density semiconductor device of more than 1G DRAM is very fine, about 0.1-0.2㎛.

따라서 베선의 높은 면저항 및 콘택 저항을 감소시키기 위하여 살리사이드 (salicide; self- aligned silicide) 방법이나 선택적 금속막 증착 방법으로 금속실리사이드막을 형성하기도 한다.Therefore, in order to reduce the high sheet resistance and contact resistance of the wire, a metal silicide film may be formed by a salicide (self-aligned silicide) method or a selective metal film deposition method.

각 세대에서 요구되는 면저항은 0.35㎛ 세대에서 20 ～ 30Ω/

Figure pat00003
, 0.25㎛ 세대에서 5 ～ 10Ω/
Figure pat00004
, 0.1㎛세대에서 5Ω/
Figure pat00005
이하로 예상된다.The sheet resistance required in each generation is 20 to 30Ω / in 0.35㎛ generation.
Figure pat00003
, 5 to 10 Ω / in 0.25 µm generation
Figure pat00004
, 5 Ω / in 0.1 μm generation
Figure pat00005
Expected below.

현재는 비트라인을 형성하기 위하여 CVD 방법으로 형성되는 텅스텐 실리사이드를 사용하고 있다.Currently, tungsten silicide formed by CVD is used to form bit lines.

도1은 종래 기술에 따른 비트라인이 형성되어 있는 반도체소자의 단면도로서, 반도체기판(1)상에 게이트산화막(2)과 게이트전극(3), 콘택홀을 구비하는 층간절연막(4)과 절연 스페이서(7)가 형성되어 있으며, 비트라인이 다결정 실리콘층(8)과 W-실리사이드막(9) 패턴으로된 비트라인이 형성되어있다.1 is a cross-sectional view of a semiconductor device having a bit line according to the prior art, insulated from an interlayer insulating film 4 having a gate oxide film 2, a gate electrode 3, and contact holes on a semiconductor substrate 1; Spacers 7 are formed, and bit lines are formed in which the bit lines are formed of the polycrystalline silicon layer 8 and the W-silicide film 9 pattern.

상기와 같은 종래 기술에 따른 W-실리사이드막을 비트라인으로 사용하는 반도체소자에서 상기 텅스텐실리사이드층은 박막의 비저항이 높을 뿐만 아니라 고온에서 실리콘 산화물층과의 열적 안정성이 매우 나빠 다결정 실리콘층상에 W-실리사이드를 증착하여 사용하는데, 소자의 고집적화에 따라서 비트라인의 선폭은 매우 감소하여 선저항이 크게 증가되므로 W-실리사이드막으로는 저항을 낮추는데 한계가 있어 소자의 특성을 악화시키는 문제점이 있다.In the semiconductor device using the conventional W-silicide layer as a bit line, the tungsten silicide layer has a high resistivity of the thin film and thermal stability with the silicon oxide layer at a high temperature. Since the line width of the bit line is greatly reduced and the line resistance is greatly increased according to the high integration of the device, there is a limitation in lowering the resistance of the W-silicide film, thereby deteriorating the characteristics of the device.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 발명은 상기 언급한 비트라인 형성 공정을 CVD-Ti 와 CVD-TiN층 및 비저항이 텅스텐실리사이드보다 더 작은 텅스텐층으로 대체하여 비트라인의 고온 열안정성을 향상시키고, 선저항이 작아서 소자의 특성 및 신뢰성을 크게 향상시킬 수 있는 반도체소자의 비트라인 제조방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to replace the above-described bit line forming process with a CVD-Ti and CVD-TiN layer and a tungsten layer having a lower resistivity than tungsten silicide. The present invention provides a method for manufacturing a bit line of a semiconductor device that can improve the high temperature thermal stability of a line and can significantly improve the characteristics and reliability of the device due to a small line resistance.

도 1은 종래 기술에 따른 비트라인이 형성되어있는 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device having a bit line according to the prior art.

도 2는 본 발명에 따른 비트라인이 형성되어있는 반도체소자의 단면도.2 is a cross-sectional view of a semiconductor device having a bit line according to the present invention.

＜도면의 주요 부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

1 : 반도체기판 2 : 게이트산화막1 semiconductor substrate 2 gate oxide film

3 : 게이트전극 4 : 층간절연막3: gate electrode 4: interlayer insulating film

7 : 절연 스페이서 8 : 다결정 실리콘층7 insulation spacer 8 polycrystalline silicon layer

9 : W-실리사이드막 10, 12 : CVD-Ti층9: W-silicide film 10, 12: CVD-Ti layer

11, 13 : CVD-TiN층 14 : W층11, 13: CVD-TiN layer 14: W layer

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 비트라인 제조방법은,Bit line manufacturing method of a semiconductor device according to the present invention for achieving the above object,

하부 CVD-Ti층을 PECVD 방법으로 형성하는 단계와, 하부 CVD-TiN층을 열 CVD 방법으로 증착하는 단계와, 상부 CVD-Ti층을 형성하고 열처리하는 단계와, 상부 CVD-TiN층을 CVD 방법으로 증착하는 단계 및 텅스텐층 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.Forming the lower CVD-Ti layer by PECVD, depositing the lower CVD-TiN layer by thermal CVD, forming and heat-treating the upper CVD-Ti layer, and subjecting the upper CVD-TiN layer to the CVD method. And depositing a tungsten layer pattern.

이하, 본발명에 따른 반도체소자의 비트라인 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a bit line of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도2는 본 발명에 따른 비트라인이 형성되어있는 반도체소자의 단면도이다.2 is a cross-sectional view of a semiconductor device having a bit line according to the present invention.

먼저, 반도체기판(1)상에 게이트산화막(2)과 게이트전극(3)이 형성되어있고, 상기 반도체기판(1)에서 비트라인 콘택으로 예정되어있는 부분을 노출시키는 콘택홀을 구비하는 층간절연막(4)이 형성되어있으며, 상기 콘택홀의 측벽에 절연 스페이서(7)가 형성되어있다.First, an interlayer insulating film having a gate oxide film 2 and a gate electrode 3 formed on the semiconductor substrate 1 and having a contact hole exposing a portion intended as a bit line contact in the semiconductor substrate 1. (4) is formed, and an insulating spacer (7) is formed on the sidewall of the contact hole.

또한 상기 콘택홀을 통하여 노출되어있는 반도체기판(1)과 접촉되는 하부 CVD-Ti층(10), 하부 CVD-TiN층(11), 상부 CVD-Ti층(12), 상부 CVD-TiN층(13) 및 텅스텐층(14) 패턴으로된 비트라인이 형성되어있다.In addition, the lower CVD-Ti layer 10, the lower CVD-TiN layer 11, the upper CVD-Ti layer 12, and the upper CVD-TiN layer contacting the semiconductor substrate 1 exposed through the contact hole ( 13) and a bit line in the tungsten layer 14 pattern is formed.

여기서 하부 CVD-Ti층(10)은 텅스텐층(14)과 하지의 실리콘층과의 오믹콘택 (OHMIC CONTACT)을 유지하기 위하여 형성되는 층으로서 대부분의 금속 Ti층은 고온공정에서 형성되는 관계로 증착 즉시 TiSix화 한다. 상기 Ti층(10)의 증착조건을 살펴보면 증착온도는 400 ～ 800℃, 증착압력은 0.5 ～ 20Torr, TiCl4유량은 0.5 ～ 50sccm, 수소 유량은 50 ～ 500sccm, 아르곤 유량은 50 ～ 1000sccm 분위기에서 수행하였으며 RF 파워는 100 ～ 1000와트(WATT)를 인가하여 플라즈마 여기 화학기상 증착법(PECVD) 방법으로 형성한다.The lower CVD-Ti layer 10 is a layer formed to maintain ohmic contact between the tungsten layer 14 and the underlying silicon layer, and most of the metal Ti layers are formed in a high temperature process. TiSix immediately. Looking at the deposition conditions of the Ti layer 10, the deposition temperature is 400 ~ 800 ℃, the deposition pressure is 0.5 ~ 20 Torr, TiCl 4 flow rate is 0.5 ~ 50sccm, hydrogen flow rate is 50 ~ 500sccm, argon flow rate is carried out in 50 ~ 1000sccm atmosphere RF power is formed by plasma excitation chemical vapor deposition (PECVD) by applying 100 to 1000 watts (WATT).

또한 하부 CVD-TiN층(11)은 증착온도는 400 ～ 700℃, 증착압력은 0.5 ～ 100 Torr, TiCl4유량은 50 ～ 1000sccm, 질소 가스 10 ～ 3000sccm, 암모니아(이하 NH3) 가스 10 ～ 300sccm의 분위기에서 수행하며 소스와 반응성가스의 열반응에 의한 CVD(THERMAL CVD) 방법으로 증착한다.In addition, the lower CVD-TiN layer 11 has a deposition temperature of 400 to 700 ° C, a deposition pressure of 0.5 to 100 Torr, a TiCl 4 flow rate of 50 to 1000 sccm, nitrogen gas 10 to 3000 sccm, ammonia (hereinafter NH 3 ) gas 10 to 300 sccm It is carried out in an atmosphere of and deposited by the thermal reaction of the source and the reactive gas CVD (THERMAL CVD) method.

그리고 상부 CVD-Ti층(12)은 연속하여 증착하며 다음으로 이 박막을 메탈어닐쳄버(이하 MAC)에서 산소 분위기에서 400 ～ 700℃ 온도에서 열처리를 수행하는데 이는 CVD-Ti박막은 입자가 다소 크고 다공질성으로서 산소기들이 CVD-Ti 입계를 따라서 충분히 흡수되어 그 뒤에 증착되는 금속 텅스텐층과 하지의 실리콘층과의 확산에 의해 발생하는 텅스텐실리사이드 형성을 방지하기 위함이다. 만일 텅스텐실리사이드가 형성될 때는 막의 부피가 팽창하여 박막에 균열을 일으키거나 금속층 내부에 기공을 형성시켜 소자특성을 현저히 저하 시키는 원인이 된다. 그리고 텅스텐의 접착막으로 기능하는 상부 CVD-TiN층(13)을 하부 CVD-TiN층(11)의 증착조건과 동일한 증착조건으로 증착한다.The upper CVD-Ti layer 12 is continuously deposited, and then the thin film is heat-treated at a temperature of 400-700 ° C. in an oxygen atmosphere in a metal anneal chamber (hereinafter referred to as MAC). This is to prevent the formation of tungsten silicide caused by diffusion of the metal tungsten layer and the underlying silicon layer which are sufficiently absorbed and deposited after the CVD-Ti grain boundary as porous material. If tungsten silicide is formed, the volume of the film expands to cause cracks in the thin film or to form pores in the metal layer, thereby causing a significant deterioration of device characteristics. The upper CVD-TiN layer 13 serving as an adhesive film of tungsten is deposited under the same deposition conditions as those of the lower CVD-TiN layer 11.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 비트라인 제조방법은 비트라인을 CVD-Ti층 및 CVD-TiN층을 이중층으로 형성하고 그 상부에 텅스텐을 이용하여 비트라인을 형성하였으므로, 후속공정시 고온 열적 특성이 안정되고, 텅스텐 실리사이보다 낮은 비저항 값을 가져 소자 특성 및 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a bit line of a semiconductor device according to the present invention, since the bit line is formed of a CVD-Ti layer and a CVD-TiN layer as a double layer, and a bit line is formed on the upper part of the bit line, a subsequent process is performed. When the high temperature thermal properties are stable and have a lower resistivity value than tungsten silicide, there is an advantage of improving device characteristics and reliability.

Claims (4)

하부 CVD-Ti층을 PECVD 방법으로 형성하는 단계;Forming a lower CVD-Ti layer by PECVD; 하부 CVD-TiN층을 열 CVD 방법으로 증착하는 단계;Depositing a bottom CVD-TiN layer by thermal CVD; 상부 CVD-Ti층을 형성하고 열처리하는 단계;Forming and heat-treating a top CVD-Ti layer; 상부 CVD-TiN층을 CVD 방법으로 증착하는 단계; 및Depositing a top CVD-TiN layer by a CVD method; And 텅스텐층 패턴을 형성하는 단계Forming a tungsten layer pattern 를 포함하는 것을 특징으로 하는 반도체소자의 비트라인 제조방법.Bit line manufacturing method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 하부 CVD-Ti층은 400 ～ 800℃, 0.5 ～ 20Torr, TiCl4유량은 0.5 ～ 50sccm, 수소 유량은 50 ～ 500sccm, 아르곤 유량은 50 ～ 1000sccm 분위기에서 RF 파워는 100 ～ 1000와트 인가하여 PECVD 방법으로 형성하는 것을 특징으로 하는 반도체소자의 비트라인 제조방법.The lower CVD-Ti layer was applied at 400 to 800 ° C., 0.5 to 20 Torr, TiCl 4 flow rate of 0.5 to 50 sccm, hydrogen flow rate of 50 to 500 sccm, argon flow rate of 50 to 1000 sccm, and RF power of 100 to 1000 watts. Bit line manufacturing method of a semiconductor device, characterized in that formed. 제1항에 있어서,The method of claim 1, 상부 및 하부 CVD-TiN층은 각각 400 ～ 700℃, 0.5 ～ 100 Torr, TiCl4유량은 50 ～ 1000sccm, 질소 가스 10 ～ 3000sccm, 암모니아 가스 10 ～ 300sccm의 분위기에서 열반응 CVD 방법으로 형성하는 것을 특징으로 하는 반도체소자의 비트라인 제조방법.The upper and lower CVD-TiN layers are formed by thermal reaction CVD in an atmosphere of 400 to 700 ° C., 0.5 to 100 Torr, TiCl 4 flow rate of 50 to 1000 sccm, nitrogen gas 10 to 3000 sccm, and ammonia gas 10 to 300 sccm, respectively. A bit line manufacturing method of a semiconductor device. 제1항에 있어서,The method of claim 1, 상기 열처리 공정은 메탈어닐쳄버 내에서 산소 분위기 및 400 ～ 700℃의 온도에서 수행되는 것을 특징으로 하는 반도체소자의 비트라인 제조방법.The heat treatment process is a bit line manufacturing method of a semiconductor device, characterized in that carried out in a metal atmosphere in an oxygen atmosphere and the temperature of 400 ~ 700 ℃.
KR1019970030256A 1997-06-30 1997-06-30 METHOD FOR FABRICATING BIT LINE OF SEMICONDUCTOR DEVICE USING CVD-Ti LAYER, CVD-TiN LAYER, AND TUNGSTEN LAYER HAVING SPECIFIC RESISTANCE LOWER THAN SPECIFIC RESISTANCE OF TUNGSTEN SILICIDE LAYER KR100445410B1 (en)

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