KR100332122B1 - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR100332122B1 KR100332122B1 KR1019990025768A KR19990025768A KR100332122B1 KR 100332122 B1 KR100332122 B1 KR 100332122B1 KR 1019990025768 A KR1019990025768 A KR 1019990025768A KR 19990025768 A KR19990025768 A KR 19990025768A KR 100332122 B1 KR100332122 B1 KR 100332122B1
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- Prior art keywords
- film
- forming
- tungsten
- stress relaxation
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 17
- 239000002184 metal Substances 0.000 title claims abstract description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 37
- 239000010937 tungsten Substances 0.000 claims abstract description 37
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 26
- 239000010410 layer Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 239000012495 reaction gas Substances 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 59
- 239000010409 thin film Substances 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 abstract description 5
- 230000003139 buffering effect Effects 0.000 abstract description 2
- 230000002040 relaxant effect Effects 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- 230000010365 information processing Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로 특히, 텅스텐을 이용한 비트 라인 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a bit line forming method using tungsten.
종래 텅스텐 금속 라인 구조에서 후속 고온 캐패시터 형성공정시 텅스텐이 갖는 높은 인장 응력으로 인하여 발생하는 텅스텐 리프팅 현상을 억제 하기 위하여 본 발명은 텅스텐 비트라인 패턴 형성 전후에 박막의 압축 응력 특성을 갖는 절연막을 텅스텐 비트라인 상. 하부에 샌드위치(Sandwich) 형태로 형성한다.In order to suppress the tungsten lifting phenomenon caused by the high tensile stress of tungsten in the subsequent high temperature capacitor formation process in the conventional tungsten metal line structure, the present invention provides an insulating film having compressive stress characteristics of the thin film before and after forming the tungsten bit line pattern. On line. It is formed in the form of a sandwich (Sandwich) at the bottom.
따라서, 본 발명은 텅스텐의 높은 인장 응력을 완화 및 완충 하여 텅스텐 금속 배선의 리프팅 현상을 방지하는 반도체 소자의 금속 배선 형성방법을 제공하고자 한다.Accordingly, the present invention is to provide a method for forming a metal wiring of a semiconductor device to prevent the lifting phenomenon of the tungsten metal wiring by relaxing and buffering the high tensile stress of tungsten.
Description
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로 특히, 텅스텐을 이용한 비트 라인 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a bit line forming method using tungsten.
종래 반도체 메모리 소자에 있어서 각각의 단위 셀에 저장되어 있는 데이터 신호 출력 경로인 비트 라인(Bit-Line) 제작을 도프트 폴리실리콘과 텅스텐 실리사이드의 적층 구조를 사용하고 있다. 종래 폴리실리콘과 텅스텐 실리사이드의 적층 구조는 소자의 집적도 증가와 고속의 정보 처리 능력을 요구하는 차세대 반도체 메모리 소자에 있어서는 높은 면저항값을 인하여 그 적용에 한계가 있다.BACKGROUND ART In the conventional semiconductor memory device, a dopant polysilicon layer and a tungsten silicide layered structure are used to fabricate a bit line, which is a data signal output path stored in each unit cell. The stack structure of the conventional polysilicon and tungsten silicide has a limitation in its application due to high sheet resistance in the next-generation semiconductor memory devices which require an increase in device integration and high-speed information processing capability.
최근에 반도체 소자의 금속 배선에 적용하고 있는 텅스텐 금속 배선층은 상기 폴리실리콘과 텅스텐 실리사이드 적층 구조를 대체하여 고속의 정보 처리를 가능하게 하는 비트 라인 구조이다.The tungsten metal wiring layer, which has recently been applied to metal wiring of semiconductor devices, is a bit line structure that enables high-speed information processing by replacing the polysilicon and tungsten silicide stacked structures.
기존의 텅스텐 비트라인 구조를 도 1을 참조하여 설명하면 다음과 같다.The conventional tungsten bit line structure will be described with reference to FIG. 1.
도 1을 참조하면, 반도체 기판(1) 상에 층간절연막(2)을 형성한 후 반도체 기판(1)이 노출 되도록 콘택 홀을 형성한다. 그후 콘택 홀이 매립되도록 Ti막(3), TiN막(4), 텅스텐막(5) 및 반사방지막인 SiON막(6)을 순차적으로 형성한 후 패터닝하여 비트라인을 형성한다.Referring to FIG. 1, after forming the interlayer insulating film 2 on the semiconductor substrate 1, a contact hole is formed to expose the semiconductor substrate 1. After that, the Ti film 3, the TiN film 4, the tungsten film 5, and the SiON film 6, which is an antireflection film, are sequentially formed and patterned so as to fill the contact holes, thereby forming a bit line.
도 1에 도시된 비트라인 구조는 캐패시터가 형성되지 않는 주변(Periphery)영역에서 형성된다. 이러한 텅스텐을 이용한 주변영역의 비트라인은 N+ 영역과 P+ 영역에 관계없이 비트라인 콘택 형성이 가능하다. 도 1에 도시된 비트라인 구조는종래 폴리실리콘/텅스텐 실리사이드 적층구조의 비트라인 구조에서 주변영역에 NMOS 만을 형성하던 형태를 벗어나 주변영역에 NMOS 및 PMOS 모두를 형성할 수 있는 장점이 있다.The bit line structure shown in FIG. 1 is formed in a peripheral region in which no capacitor is formed. The bit line of the peripheral region using the tungsten can form a bit line contact regardless of the N + region and the P + region. The bit line structure shown in FIG. 1 has the advantage of forming both NMOS and PMOS in the peripheral region, instead of forming the NMOS only in the peripheral region in the bit line structure of the conventional polysilicon / tungsten silicide stack structure.
그러나, 화학 기상증착 공정으로 증착되는 텅스텐 박막은 9×109dyne/cm2이상의 높은 인장 응력(Tensile stress) 특성을 나타내며, 종래 층간절연막으로 사용되는 BPSG 산화막 자체도 인장응력 특성을 가지고 있다. 따라서, 텅스텐 및 BPSG막의 높은 인장력에 의하여 후속 캐패시터 형성공정시 780℃ 이상의 고온 공정으로인하여 텅스텐 비트라인 가장 자리에서부터 리프팅(Lifting) 현상이 발생한다.However, the tungsten thin film deposited by the chemical vapor deposition process exhibits a high tensile stress characteristic of 9 × 10 9 dyne / cm 2 or more, and the BPSG oxide film itself, which is conventionally used as an interlayer insulating film, also has a tensile stress characteristic. Accordingly, the phenomenon of lifting occurs from the edge of the tungsten bit line due to the high temperature process of 780 ° C. or higher during the subsequent capacitor formation process due to the high tensile force of the tungsten and BPSG films.
종래 텅스텐 금속 라인 구조에서 후속 고온 캐패시터 형성공정시 텅스텐이 갖는 높은 인장 응력으로 인하여 발생하는 텅스텐 리프팅 현상을 억제 하기 위하여 본 발명은 텅스텐 비트라인 패턴 형성 전후에 박막의 압축 응력 특성을 갖는 절연막을 텅스텐 비트라인 상. 하부에 샌드위치(Sandwich) 형태로 형성한다. 따라서, 본 발명은 텅스텐의 높은 인장 응력을 완화 및 완충 하여 텅스텐 금속 배선의 리프팅 현상을 방지하는 반도체 소자의 금속 배선 형성방법을 제공하는데 그 목적이 있다.In order to suppress the tungsten lifting phenomenon caused by the high tensile stress of tungsten in the subsequent high temperature capacitor formation process in the conventional tungsten metal line structure, the present invention provides an insulating film having compressive stress characteristics of the thin film before and after forming the tungsten bit line pattern. On line. It is formed in the form of a sandwich (Sandwich) at the bottom. Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device to prevent the lifting phenomenon of the tungsten metal wiring by relaxing and buffering the high tensile stress of tungsten.
상기한 목적을 달성하기 위한 본 발명은 반도체 기판상에 층간절연막 및 제 1 응력완화층을 순차적으로 형성한 후 반도체 기판이 노출 되도록 콘택 홀을 형성하는 단계와, 전체 상부면에 확산 방지막을 증착한 후 열처리 하는 단계와, 상기 콘택 홀이 매립되도록 텅스텐 막을 형성한 후 전체 상부면에 반사방지막을 형성하는 단계와, 상기 반사방지막, 확산 방지막 및 텅스텐막을 패터닝하여 비트라인을 형성한 후 전체 상부면에 제 2 응력 완화층을 증착하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object is formed by sequentially forming an interlayer insulating film and a first stress relaxation layer on the semiconductor substrate and forming a contact hole so that the semiconductor substrate is exposed, and depositing a diffusion barrier film on the entire upper surface Post-heat treatment, forming a tungsten film to fill the contact hole, and then forming an anti-reflection film on the entire upper surface; and forming a bit line by patterning the anti-reflection film, the diffusion barrier and the tungsten film on the entire upper surface And depositing a second stress relief layer.
도 1은 종래 반도체 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a metal wiring formation method of a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 금속 배선 형성방법을 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
1 및 11 : 반도체 기판 2 : 층간절연막1 and 11: semiconductor substrate 2: interlayer insulating film
12 : BPSG막 3 및 14: Ti막12: BPSG film 3 and 14: Ti film
4 및 15 : TiN막 5 및 16 : 텅스텐막4 and 15 TiN film 5 and 16 tungsten film
13 : 제 1 SiON막 6 : SiON막13: First SiON Film 6: SiON Film
17 : 제 2 SiON막 18 : 제 3 SiON막17: second SiON film 18: third SiON film
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 소자의 단면도이다.2A to 2C are cross-sectional views of devices for describing a method for forming metal wirings of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체 기판(11) 상에 층간절연막인 BPSG막(12) 및 인장응력에 대한 응력 완화층인 제 1 SiON막(13)을 순차적으로 형성한 후 반도체 기판(11)이 노출 되도록 콘택홀(A)을 형성한다.Referring to FIG. 2A, after the BPSG film 12, which is an interlayer insulating film, and the first SiON film 13, which is a stress relaxation layer against tensile stress, are sequentially formed on the semiconductor substrate 11, the semiconductor substrate 11 is exposed. The contact hole A is formed as much as possible.
이때, 응력 완화층인 제 1 SiON막(13)은 SiH4, N2O 및 NH3반응가스를 이용하여 플라즈마 강화 화학기상증착(Plasma enhanced chemical vapor deposition) 방법으로 1000 내지 3000Å 두께로 형성한다. 플라즈마 강화 화학기상증착 방법으로 형성되는 SiON 증착 반응식을 다음과 같다.In this case, the first SiON film 13, which is a stress relaxation layer, is formed to have a thickness of 1000 to 3000 Pa by plasma enhanced chemical vapor deposition using SiH 4 , N 2 O, and NH 3 reaction gases. The SiON deposition reaction formula formed by the plasma enhanced chemical vapor deposition method is as follows.
또한, 제 1 SiON막(13)의 압축 응력을 높이기 위하여 RF(Radio Frequency)전력의 범위는 저주파수(Low Frequency) 일때 0.65 내지 0.85kWatt, 고주파수일(HighFrequency) 때는 0.15 내지 0.35 kWatt 로 설정한다. 고주파수 전력은 이온과 비교하여 상대적으로 가벼운 전자의 운동 에너지를 높여주어 증착 반응에 참여하는 반응가스와의 충돌을 증가 시키므로 반응 가스의 이온화를 높여주고 전체적인 플라즈마 밀도를 증가시킨다. 저주파수 전력은 전자와 비교하여 상대적으로 무거운 플라즈마 이온들과 반응하여 증착 반응성을 높여주어 결과적으로 박막의 밀도를 높여주고 응력 특성을 변화 시킨다.In addition, in order to increase the compressive stress of the first SiON film 13, the RF (Radio Frequency) power range is set to 0.65 to 0.85 kWatt at low frequency and 0.15 to 0.35 kWatt at high frequency. High-frequency power increases the kinetic energy of electrons that are relatively light compared to ions and increases the collision with the reaction gas participating in the deposition reaction, thereby increasing the ionization of the reaction gas and increasing the overall plasma density. The low frequency power reacts with the relatively heavy plasma ions compared to the electrons to increase the deposition reactivity, resulting in higher density of the thin film and changing stress characteristics.
그리고, 상기 반응가스의 유량 범위는 SiH4는 100 내지 250 sccm, N2O 는 2500 내지 3500 sccm, NH3는 1500 내지 2500 sccm 로 한다. 그리고, 상기 플라즈마 화학기상 증착시 온도는 380 내지 460℃ 로 하고, 압력은 2.0 내지 5.0 Torr로 하여 증착한다.In addition, the flow range of the reaction gas is SiH 4 100 to 250 sccm, N 2 O is 2500 to 3500 sccm, NH 3 is 1500 to 2500 sccm. In the plasma chemical vapor deposition, the deposition temperature is 380 to 460 ° C. and the pressure is 2.0 to 5.0 Torr.
도 2b를 참조하면, 전체 상부면에 확산 방지막인 Ti막(14) 및 TiN막(15)을 화학 기상증착방법으로 순차적으로 형성한 후 콘택홀이 매립 되도록 텅스텐막(16)을 형성한다. 그후 비트라인 패턴시 노광공정을 위해 반사방지막인 제 2 SiON막(17)을 형성한다. 이때, Ti막(14)은 50 내지 500Å, TiN막(15)는 100 내지 500Å 두께로 형성하고 콘택 저항을 낮추기 위하여 상기 확산방지막을 650 내지 850℃의 온도에서 급속 열처리한다. 텅스텐막(16)은 500 내지 2500Å 두께로 형성한다.Referring to FIG. 2B, after the Ti film 14 and the TiN film 15, which are diffusion preventing films, are sequentially formed on the entire upper surface, a tungsten film 16 is formed to fill contact holes. Thereafter, a second SiON film 17, which is an antireflection film, is formed for the exposure process in the bit line pattern. At this time, the Ti film 14 is 50 to 500 kPa, the TiN film 15 is formed to a thickness of 100 to 500 kPa and the heat-resistant diffusion film is rapidly heat treated at a temperature of 650 to 850 ℃ to lower the contact resistance. The tungsten film 16 is formed to a thickness of 500 to 2500 mm 3.
도 2c를 참조하면, 사진 및 식각공정으로 Ti막(14), TiN막(15),텅스텐막(16) 및 제 2 SiON막(17)을 식각하여 비트라인 패턴을 형성한 후 전체 상부면에 응력 완화층인 제 3 SiON막(18)을 형성하여 텅스텐 비트라인이 응력 완화층인 제 1 및 2 SiON막(13 및 18)으로 둘러 싸이는 샌드위치형으로 형성되어 인장응력이 완화된다. 이때, 제 3 SiON막(18)은 제 1 SiON막(13)과 동일한 방법으로 형성한다.Referring to FIG. 2C, the Ti film 14, the TiN film 15, the tungsten film 16, and the second SiON film 17 are etched by photo and etching to form a bit line pattern on the entire upper surface. The third SiON film 18, which is a stress relaxation layer, is formed so that the tungsten bit line is formed in a sandwich form surrounded by the first and second SiON films 13 and 18, which are stress relaxation layers, thereby reducing the tensile stress. At this time, the third SiON film 18 is formed in the same manner as the first SiON film 13.
상술한 바와같이 텅스텐이 갖는 높은 인장응력을 완화할 수 있는 응력 완화층으로 SiON막을 이용한다. 또한, 전체적인 RF 전력을 동일하게 하게 유지하면서 응력 완화층인 제 1 및 2 SiON막(13 및 18)이 높은 압축 응력을 갖도록 고주파수 인가량을 줄이고 저 주파수 인가량을 증가 시킨다. 이때, 텅스텐막(16)이 갖는 9×109dyne/cm2의 높은 인장응력에 대해 SiON막의 -3 ×109dyne/cm2내지 -5 ×109dyne/cm2의 압축응력이 적용되어 텅스테 비트라인 패턴이 후속 열공정시 발생되는 리프팅 현상이 방지된다.As described above, a SiON film is used as a stress relaxation layer that can alleviate the high tensile stress of tungsten. In addition, while maintaining the same overall RF power, the first and second SiON films 13 and 18, which are the stress relaxation layers, reduce the high frequency application amount and increase the low frequency application amount so as to have a high compressive stress. At this time, the compressive stress of -3 × 10 9 dyne / cm 2 to -5 × 10 9 dyne / cm 2 of the SiON film is applied to the high tensile stress of 9 × 10 9 dyne / cm 2 of the tungsten film 16. The lifting phenomenon in which the tungsten bit line pattern occurs during subsequent thermal processing is prevented.
그리고, RF 전력 뿐만 아니라 반응가스에 따라서 증착되는 SiON막의 특성이 변화된다. SiON막은 α-Si과 SiO2그리고 Si3N4의 삼상계로 구성된 물질이다. 박막내 α-Si의 양에 따라 α-Si의 함유량이 증가하면 인장 응력 특성을 갖고, α-Si 함유량이 감소하면 압축 응력 특성을 나타낸다. 본 발명에서 SiON막 형성시 압축 응력 특성을 갖도록 반응가스인 SiH4, N2O 및 NH3반응계에서 SiH4반응가스의 양을 줄이고 NH3반응가스의 양은 늘이는 조건하에서 형성한다. 그 결과 SiON막은 Si 함유량이 줄어들고 SiO2의 함유량이 상대적으로 증가하여 박막내 산소 성분이 증가된다. SiON막 내의 산소 성분의 증가는 크랙(Crack) 저항 특성을 개선하여 텅스텐 비트라인 모서리 부분의 크랙 발생을 억제한다.In addition, the characteristics of the SiON film deposited are changed depending on not only the RF power but also the reaction gas. SiON film is a material consisting of a three-phase system of α-Si, SiO 2 and Si 3 N 4 . Increasing the content of α-Si in accordance with the amount of α-Si in the thin film has a tensile stress characteristic, while decreasing the α-Si content exhibits a compressive stress characteristic. Reducing the amount of reaction gas SiH 4 in the present invention, the reaction gas is SiH 4, N 2 O and NH 3 reaction system so as to have a compressive stress characteristic in forming an SiON film is formed under a condition in extending the amount of the NH 3 gas reaction. As a result, the SiON film decreases the Si content and the SiO 2 content increases relatively to increase the oxygen content in the thin film. Increasing the oxygen content in the SiON film improves crack resistance characteristics, thereby suppressing crack generation at the tungsten bit line edges.
본 발명은 텅스텐 비트라인을 압축 응력 특성을 갖는 SiON막으로 둘러싸게 하여 후속 캐패시터 공정에서 고온으로 인한 텅스텐 비트라인의 리프팅 현상을 방지한다. 따라서, 256M DRAM 이상의 고집적 반도체 메모리 소자 제작시 요구되는 고속의 정보 처리를 수행 할수 있고, 소자의 전기적 특성이 향상되는 효과가 있다.The present invention surrounds the tungsten bitline with a SiON film having compressive stress characteristics to prevent lifting of the tungsten bitline due to high temperatures in subsequent capacitor processes. Therefore, it is possible to perform high-speed information processing required when fabricating a highly integrated semiconductor memory device of 256M DRAM or more, and the electrical characteristics of the device are improved.
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