KR20090056673A - Method for forming electrode of semiconductor device - Google Patents

Method for forming electrode of semiconductor device Download PDF

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KR20090056673A
KR20090056673A KR1020070123920A KR20070123920A KR20090056673A KR 20090056673 A KR20090056673 A KR 20090056673A KR 1020070123920 A KR1020070123920 A KR 1020070123920A KR 20070123920 A KR20070123920 A KR 20070123920A KR 20090056673 A KR20090056673 A KR 20090056673A
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film
tungsten
forming
pattern
semiconductor device
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KR1020070123920A
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Korean (ko)
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지연혁
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming an electrode of a semiconductor device is provided to reduce manufacturing cost by defining a condition of forming a capping nitride. In a method for forming an electrode of a semiconductor device, a pattern is formed on the semiconductor substrate(200) while including a hard mask deposited on a tungsten film(250) and a hard mask(260). The capping layer is formed at a temperature of 400°C to 600°C and surrounds the same pattern, and the pattern, is formed by laminating a gate insulating layer, a polysilicon layer, and a tungsten film and hard mask in successively. At that time the pattern is a bit line.

Description

반도체 소자의 전극 형성방법{Method for forming electrode of semiconductor device}Method for forming electrode of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 기판에 형성되는 소자들 간의 전기적 신호를 보내기 위한 전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an electrode forming method for transmitting electrical signals between devices formed on a semiconductor substrate.

최근 반도체 메모리(Memory) 소자의 미세화가 가속화됨에 따라 한정된 면적 내에 메모리 소자를 구현하는데 있어서 많은 어려움을 겪고 있다. 예를 들면, 하나의 셀(Cell)당 1 트랜지스터와 1 캐패시터의 구조로 형성되어 있는 디램(DRAM) 메모리 소자의 경우, 한정된 면적 내에 트랜지스터의 활성영역의 면적이 점차 축소화되면서 비저항이 낮은 게이트 전극물질의 개발이 요구되고 있다. Recently, as the miniaturization of semiconductor memory devices is accelerated, there are many difficulties in implementing memory devices in a limited area. For example, in the case of a DRAM memory device having a structure of one transistor and one capacitor per cell, a gate electrode material having a low specific resistance while gradually reducing the area of an active region of a transistor within a limited area Development is required.

현재 개발되어 양산이 이루어지고 있는 게이트 전극으로는 텅스텐(W)이 사용되고 있다. 텅스텐은 고집적 디램(DRAM) 소자에서 비저항이 낮아 게이트 신호시간지연(Gate RC Time Delay) 특성을 개선시키는 장점이 있다.Tungsten (W) is used as a gate electrode that is currently developed and mass produced. Tungsten has the advantage of improving the gate RC time delay characteristics because of the low resistivity in high-density DRAM devices.

도 1은 종래의 텅스텐(W) 게이트를 형성하는 방법을 설명하기 위해 나타낸 도면이다.1 is a view illustrating a conventional method of forming a tungsten (W) gate.

반도체 기판(100) 상에 게이트 절연막(110), 폴리실리콘막(120) 및 장벽층으 로 예를들면, 텅스텐 실리사이드막(WSix)(130) 또는 티타늄 나이트라이드막(TiN)(130)을 형성한다. 이어서 텅스텐 나이트라이드막(WN)(140), 텅스텐막(W)(150) 및 하드마스크(160)를 적층한 후, 노광 및 현상과 식각 공정을 수행하여 텅스텐 실리사이드막(130)까지 패터닝한다. For example, a tungsten silicide layer (WSix) 130 or a titanium nitride layer (TiN) 130 is formed as the gate insulating layer 110, the polysilicon layer 120, and the barrier layer on the semiconductor substrate 100. . Subsequently, after the tungsten nitride layer (WN) 140, the tungsten layer (W) 150, and the hard mask 160 are stacked, the tungsten silicide layer 130 is patterned by performing exposure, development, and etching processes.

다음, 열처리 단계를 진행하는데, 실리콘을 포함하는 전구체, 예를 들면 디클로로실란(SiH2C12; DCS) 전구체와 암모니아(NH3) 반응가스를 유입시켜 텅스텐 스택(130~160)을 감싸는 캡핑 나이트라이드막(Capping Nitirde)(170)을 형성한다. 이때 730℃ 정도의 온도에서 열처리를 수행하여 텅스텐 막의 비정상적인 산화를 억제한다. Next, a heat treatment step is performed, and a precursor containing silicon, for example, a dichlorosilane (SiH 2 C 12 ; DCS) precursor and ammonia (NH 3 ) are introduced into a capping nit covering the tungsten stack 130 to 160. Ride film (Capping Nitirde) 170 is formed. At this time, heat treatment is performed at a temperature of about 730 ° C. to suppress abnormal oxidation of the tungsten film.

그런데 캡핑 나이트라이드막을 형성할 때는 통상 730℃ 정도의 온도에서 열처리를 수행하는데, 상기 온도구간에서 비정질 상의 텅스텐이 결정질로 바뀌는 상전이 현상이 일어나게 되어 격자가 어긋나는 현상(Mismatch)이 나타나게 된다. 이 때문에 응력이 발생하게 되고, 게이트가 기울어지는 현상(Gate Leaning)(180)이 나타나 소자에 악영향을 미치게 된다.However, when the capping nitride film is formed, heat treatment is usually performed at a temperature of about 730 ° C. In the temperature range, a phase transition phenomenon in which an amorphous tungsten is turned into a crystalline phase occurs and a lattice mismatch occurs. As a result, a stress is generated, and a gate tilting phenomenon 180 appears to adversely affect the device.

본 발명은, 반도체 기판상에 텅스텐막과 상기 텅스텐막 상에 적층된 하드마스크를 포함하는 패턴을 형성하는 단계; 및 400℃ 내지 600℃의 온도에서 상기 패턴을 감싸는 캡핑막을 형성하는 단계를 포함한다.The present invention includes forming a pattern on a semiconductor substrate including a tungsten film and a hard mask stacked on the tungsten film; And forming a capping film surrounding the pattern at a temperature of 400 ° C to 600 ° C.

상기 패턴은 게이트절연막, 폴리실리콘막, 텅스텐막 및 하드마스크가 차례로 적층된 게이트 패턴을 형성할 수 있다.The pattern may form a gate pattern in which a gate insulating film, a polysilicon film, a tungsten film, and a hard mask are sequentially stacked.

상기 패턴은 비트라인 패턴일 수 있다.The pattern may be a bit line pattern.

상기 텅스텐막 하부에 장벽층을 형성할 수 있다.A barrier layer may be formed under the tungsten film.

상기 장벽층은 텅스텐 나이트라이드(WN), 텅스텐 실리사이드(WSi), 티타늄(Ti), 티타늄 나이트라이드(TiN)에서 적어도 어느 하나를 선택하여 형성할 수 있다.The barrier layer may be formed by selecting at least one of tungsten nitride (WN), tungsten silicide (WSi), titanium (Ti), and titanium nitride (TiN).

상기 캡핑막은 모노 실란(SiH4)과 암모니아(NH3)를 사용하여 형성할 수 있다.The capping layer may be formed using mono silane (SiH 4 ) and ammonia (NH 3 ).

상기 캡핑막을 형성한 후에, 반도체 기판에 열처리를 수행할 수 있다.After the capping layer is formed, heat treatment may be performed on the semiconductor substrate.

상기 반도체기판을 열처리하는 단계는 500℃ 내지 600℃에서 30분 동안 진행할 수 있다.The heat treatment of the semiconductor substrate may be performed at 500 ° C. to 600 ° C. for 30 minutes.

상기 캡핑막을 형성하는 단계 및 상기 반도체기판을 열처리하는 단계는 인-시츄(In-Situ)로 진행할 수 있다.The forming of the capping layer and the heat treatment of the semiconductor substrate may be performed in-situ.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다. 그러나 본 발명은 여러 가지 다양한 형태로 구현될 수 있으며 여기에서 설명하는 실시예에 한정되지 않는다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

도 2 내지 도 4는 본 발명의 실시예에 따른 반도체 소자의 전극 형성방법을 설명하기 위하여 나타낸 도면들이다.2 to 4 are diagrams for explaining an electrode forming method of a semiconductor device according to an embodiment of the present invention.

도 2를 참조하면, 반도체기판(200) 상에, 예를 들어 산화막을 형성하여 게이트 절연막(210)을 형성한 후, 불순물이 도핑된 폴리실리콘막(220)을 1000Å이하의 두께로 형성한다. 다음 폴리실리콘막(220) 상에 예를 들면, 텅스텐 나이트라이드막, 텅스텐 실리사이드막, 티타늄 및 티타늄 나이트라이드막 중 적어도 어느 하나를 100Å이하의 두께로 증착하여 장벽층(230)을 형성한다. 본 발명에서는 장벽층(230)으로 폴리실리콘막(220) 상에 텅스텐 실리사이드막 또는 티타늄 나이트라이드를 형성한다음 텅스텐 나이트라이드(240) 및 텅스텐막(250)을 적층한다. 이때 텅스텐 나이트라이드막(240)과 텅스텐막(250)과의 총 두께가 500Å이하가 되도록 형성한다. 텅스텐 나이트라이드(240)는 텅스텐막(250)과 폴리실리콘막(220) 사이의 화학적 반응을 억제하고 접촉성을 높이는 역할을 한다. Referring to FIG. 2, an oxide film is formed on the semiconductor substrate 200, for example, to form a gate insulating film 210, and then a polysilicon film 220 doped with impurities is formed to a thickness of 1000 Å or less. For example, at least one of a tungsten nitride film, a tungsten silicide film, a titanium, and a titanium nitride film is deposited on the polysilicon film 220 to a thickness of 100 kΩ or less to form a barrier layer 230. In the present invention, a tungsten silicide film or titanium nitride is formed on the polysilicon film 220 using the barrier layer 230, and then tungsten nitride 240 and tungsten film 250 are stacked. At this time, the total thickness of the tungsten nitride film 240 and the tungsten film 250 is formed to be 500 Å or less. Tungsten nitride 240 serves to suppress the chemical reaction between the tungsten film 250 and the polysilicon film 220 and to improve contactability.

다음 하드마스크(260)로 질화막을 형성하는데, 이때 질화막의 두께는 3000Å 이하로 형성한다.Next, a nitride film is formed using the hard mask 260, in which the thickness of the nitride film is less than 3000 GPa.

도 3을 참조하면, 상기 하드마스크(260) 상에 포토레지스트막을 도포한 다음, 게이트가 형성될 영역을 한정하기 위하여 포토레지스트막(도시되지 않음)을 패터닝한다. 그리고 패턴된 포토레지스트막(도시되지 않음)을 마스크로 사용하여 하 드마스크(260)를 선택적으로 식각한다. 이어서 패턴된 하드마스크(260)를 이용하여 장벽층(230), 텅스텐 나이트라이드(240), 및 텅스텐막(250)을 선택적으로 식각한다. 그러면, 텅스텐막(250)을 포함하는 게이트 패턴이 형성된다. Referring to FIG. 3, after applying a photoresist film on the hard mask 260, a photoresist film (not shown) is patterned to define a region where a gate is to be formed. The hard mask 260 is selectively etched using a patterned photoresist film (not shown) as a mask. Next, the barrier layer 230, the tungsten nitride 240, and the tungsten film 250 are selectively etched using the patterned hard mask 260. As a result, a gate pattern including the tungsten film 250 is formed.

도 4를 참조하면, 텅스텐막(250) 표면의 비정상적인 산화를 방지하기 위하여 게이트 패턴을 감싸는 캡핑막(270)을 형성한다. 캡핑막(270)의 형성은 텅스텐의 비정질에서 결정질로의 상전이를 방지하기 위하여 비교적 낮은 온도인 400℃ 내지 600℃에서 공정을 진행한다. 또한 캡핑막(270)의 두께 산포를 개선하기 위하여 공정압력은 0.2 torr 이하에서 수행한다. 그리고 실리콘(Si) 소스로서 모노실란(SiH4; MS) 전구체를 사용하고, 반응 가스로는 암모니아(NH3) 가스를 챔버 내에 유입하여 캡핑 나이트라이드를 형성한다. 이때 상기 캡핑막(270)을 형성하는 과정에서 반응온도가 비교적 낮은 모노실란(MS) 전구체를 사용함으로써, 열예산(Thermal Budget)을 줄일 수 있고, 텅스텐의 상전이에 의하여 격자가 어긋나는 현상(Mismatch)을 억제할 수 있다. Referring to FIG. 4, a capping layer 270 surrounding the gate pattern is formed to prevent abnormal oxidation of the surface of the tungsten layer 250. The capping film 270 is formed at a relatively low temperature of 400 ° C. to 600 ° C. in order to prevent a phase transition from amorphous to crystalline tungsten. In addition, to improve the thickness distribution of the capping layer 270, the process pressure is performed at 0.2 torr or less. A monosilane (SiH 4 ; MS) precursor is used as a silicon (Si) source, and ammonia (NH 3 ) gas is introduced into the chamber as a reaction gas to form capping nitride. At this time, by using a monosilane (MS) precursor having a relatively low reaction temperature in the process of forming the capping film 270, thermal budget can be reduced, and the lattice shift due to the phase transition of tungsten (Mismatch) Can be suppressed.

다음, 캡핑막(270)의 치밀도를 개선하기 위하여 인-시츄(In-situ)로 열처리를 수행한다. 이때에도 텅스텐의 상전이를 차단하기 위하여 500℃ 내지 600℃의 온도에서 열처리를 진행한다. 그리고 챔버 내의 분위기는 아르곤(Ar)과 같은 비활성 가스를 사용하고 열처리 시간은 30분 이내로 공정을 진행한다.Next, heat treatment is performed in-situ to improve the density of the capping layer 270. In this case, heat treatment is performed at a temperature of 500 ° C. to 600 ° C. to block the phase transition of tungsten. And the atmosphere in the chamber uses an inert gas such as argon (Ar) and the heat treatment time proceeds within 30 minutes.

상기 캡핑막(270)의 형성으로 인하여 텅스텐막의 산화를 방지할 수 있음은 물론, 후속 랜딩 플러그 컨택 형성을 위한 식각 공정 시 자기정렬컨택(SAC)이 가능 하고 랜딩 플러그 컨택의 오픈(Open)을 형성할 수 있게 된다. Due to the formation of the capping layer 270, the oxidation of the tungsten film may be prevented, as well as self alignment contact (SAC) is possible during the etching process for forming the subsequent landing plug contact, and the landing plug contact is opened. You can do it.

본 발명은 게이트 패턴 또는 비트라인 패턴을 캡핑하기 위한 캡핑 나이트라이드를 형성함에 있어서, 열처리 조건을 한정하고, 디클로로실란(SiH2C12; DCS) 대신 비교적 반응온도가 낮은 모노실란(SiH4)을 사용함으로써, 열예산(Thermal Budget)을 줄일 수 있다. 또한 텅스텐의 상전이에 의해 격자가 어긋나는 현상(Mismatch)을 억제할 수 있기 때문에 게이트가 기울어지는 현상이 사라진다. 그리고 후속 랜딩 플러그 컨택 형성을 위한 식각 공정 시, 자기정렬컨택(Self Aligned Contact; SAC)이 가능하고, 랜딩 플러그 컨택의 오픈(Open)이 원활하게 진행되어 소자의 수율을 증가시킬 수 있다.In the present invention, in forming a capping nitride for capping a gate pattern or a bit line pattern, the heat treatment conditions are limited, and instead of dichlorosilane (SiH 2 C 12 ; DCS), monosilane (SiH 4 ) having a relatively low reaction temperature is used. By using this, the thermal budget can be reduced. In addition, the phenomenon that the grating shifts (Mismatch) can be suppressed by the phase transition of tungsten, so that the gate tilting disappears. In the etching process for forming subsequent landing plug contacts, self-aligned contacts (SAC) are possible, and opening of the landing plug contacts is smoothly performed to increase the yield of devices.

이상 본 발명은 게이트 전극을 형성하는 공정에 적용한 것을 예를 들어 설명하였으나, 비트라인 형성공정에도 본 발명을 유용하게 적용할 수 있다. As described above, the present invention has been described using an example of a process for forming a gate electrode, but the present invention can also be usefully applied to a bit line forming process.

도 1은 종래 기술의 반도체 소자의 전극 형성방법에서 발생하는 문제점을 설명하기 위해 나타낸 도면이다. 1 is a view illustrating a problem that occurs in the electrode forming method of a conventional semiconductor device.

도 2 내지 도 4은 본 발명에 따른 반도체 소자의 전극 형성방법을 설명하기 위하여 나타낸 도면이다.2 to 4 are diagrams for explaining the electrode forming method of the semiconductor device according to the present invention.

＊도면의 주요 부분에 대한 부호의 설명＊＊ Explanation of symbols for main parts of drawing *

100....반도체기판 110....게이트 절연막 120....폴리 실리콘막 130....텅스텐 실리사이드막 또는 티타늄 나이트라이드막 100. Semiconductor board 110 Gate insulating film Polysilicon film Tungsten silicide film or titanium nitride film

140....텅스텐 나이트라이드막 150....텅스텐막 160....하드마스크 140..Tungsten nitride film 150.Tungsten film 160.Hardmask

170....캡핑 나이트라이드막 180....게이트 리닝(Gate leaning) 현상 170 .... Capping nitride film 180 .... Gate leaning phenomenon

200....반도체기판 210....게이트 절연막 220....폴리 실리콘막 200 .... semiconductor substrate 210 ... gate insulating film 220 ... polysilicon film

230....장벽층 230 .... barrier floor

240....텅스텐 나이트라이드막 250....텅스텐막 260....하드마스크 240 Tungsten nitride film 250 Tungsten film 260 Hard mask

270....캡핑막 270 ... capping film

Claims (9)

반도체 기판상에 텅스텐막과 상기 텅스텐막 상에 적층된 하드마스크를 포함하는 패턴을 형성하는 단계; 및Forming a pattern including a tungsten film on the semiconductor substrate and a hard mask stacked on the tungsten film; And 400℃ 내지 600℃의 온도에서 상기 패턴을 감싸는 캡핑막을 형성하는 단계를 포함하는 반도체 소자의 전극 형성방법.Forming a capping film surrounding the pattern at a temperature of 400 ℃ to 600 ℃ electrode forming method of a semiconductor device. 제1항에 있어서,The method of claim 1, 상기 패턴은 게이트절연막, 폴리실리콘막, 텅스텐막 및 하드마스크가 차례로 적층된 게이트 패턴인 반도체 소자의 전극 형성방법.And the pattern is a gate pattern in which a gate insulating film, a polysilicon film, a tungsten film, and a hard mask are sequentially stacked. 제1항에 있어서,The method of claim 1, 상기 패턴은 비트라인 패턴인 반도체 소자의 전극 형성방법.And the pattern is a bit line pattern. 제1항에 있어서,The method of claim 1, 상기 텅스텐막 하부에 장벽층을 형성하는 반도체 소자의 전극 형성방법.And forming a barrier layer under the tungsten film. 제4항에 있어서,The method of claim 4, wherein 상기 장벽층은 텅스텐 나이트라이드(WN), 텅스텐 실리사이드(WSi), 티타늄(Ti), 티타늄 나이트라이드(TiN)에서 적어도 어느 하나를 선택하여 형성하는 반 도체 소자의 전극 형성방법.The barrier layer is an electrode forming method of a semiconductor device formed by selecting at least one of tungsten nitride (WN), tungsten silicide (WSi), titanium (Ti), titanium nitride (TiN). 제1항에 있어서,The method of claim 1, 상기 캡핑막은 모노 실란(SiH4)과 암모니아(NH3)를 사용하여 형성하는 반도체 소자의 전극 형성방법.The capping film is a method of forming an electrode of a semiconductor device formed using mono silane (SiH 4 ) and ammonia (NH 3 ). 제1항에 있어서,The method of claim 1, 상기 캡핑막을 형성한 후에,After the capping film is formed, 반도체 기판에 열처리를 수행하는 반도체 소자의 전극 형성방법.An electrode forming method of a semiconductor device that performs a heat treatment on a semiconductor substrate. 제7항에 있어서,The method of claim 7, wherein 상기 반도체기판을 열처리하는 단계는The heat treatment of the semiconductor substrate is 500℃ 내지 600℃에서 30분 동안 진행하는 반도체 소자의 전극 형성방법.Electrode formation method of a semiconductor device that proceeds for 30 minutes at 500 ℃ to 600 ℃. 제1항 및 제7항에 있어서,The method according to claim 1 and 7, 상기 캡핑막을 형성하는 단계 및 상기 반도체기판을 열처리하는 단계는 인-시츄(In-Situ)로 진행하는 반도체 소자의 전극 형성방법.The forming of the capping layer and the heat treatment of the semiconductor substrate may be performed in-situ.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110085591A (en) * 2018-01-25 2019-08-02 联华电子股份有限公司 The method for making semiconductor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110085591A (en) * 2018-01-25 2019-08-02 联华电子股份有限公司 The method for making semiconductor structure

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