CN110085591A - The method for making semiconductor structure - Google Patents

The method for making semiconductor structure Download PDF

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Publication number
CN110085591A
CN110085591A CN201810072028.4A CN201810072028A CN110085591A CN 110085591 A CN110085591 A CN 110085591A CN 201810072028 A CN201810072028 A CN 201810072028A CN 110085591 A CN110085591 A CN 110085591A
Authority
CN
China
Prior art keywords
layer
bit line
semiconductor structure
metal layer
tungsten metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810072028.4A
Other languages
Chinese (zh)
Inventor
林冠君
黄信富
陈威志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
Original Assignee
Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujian Jinhua Integrated Circuit Co Ltd, United Microelectronics Corp filed Critical Fujian Jinhua Integrated Circuit Co Ltd
Priority to CN201810072028.4A priority Critical patent/CN110085591A/en
Priority to US15/888,069 priority patent/US20190229014A1/en
Publication of CN110085591A publication Critical patent/CN110085591A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Abstract

The present invention discloses a kind of method for making semiconductor structure, includes: providing a substrate；A bit line is formed on this substrate, and wherein the bit line includes cap rock in a tungsten metal layer and one, and cap rock is located in the tungsten metal layer on this；And low-temperature physics vapor deposition manufacture craft is carried out, one silicon nitride gap parietal layer of deposition covers the bit line and the substrate, and wherein the silicon nitride gap parietal layer directly contacts the tungsten metal layer.Wherein low-temperature physics vapor deposition manufacture craft is carried out at 200~400 DEG C.

Description

The method for making semiconductor structure
Technical field
The present invention relates to a kind of semiconductor structures and forming method thereof, a kind of bit line structure more particularly to memory and Its forming method.
Background technique
With the increasingly promotion of the integrated level of non-volatility memorizer, the bit line line width of memory must also reduce.However, The line width of bit line, which becomes smaller, will cause the rising of its resistance value, so that the electric current of storage unit becomes smaller and leads to excessively high bit-line load (bit line loading).It follows that the bit line resistance value of memory is particularly significant for the operation efficiency of memory.
In general, the bit line of memory includes the stacked structure of multilayer material film, for example, being equipped with tungsten gold on the polysilicon layer Belong to layer, then, cap rock on a silicon nitride is equipped in tungsten metal layer.In the etching for completing above-mentioned stacked structure and then to change Vapor deposition manufacture craft is learned in depositing a silicon nitride gap parietal layer on stacked structure, however, in above-mentioned chemical vapor deposition system Make in the hot environment of technique, nitrogen can be reacted with the tungsten metal layer of stacked structure generates tungsten nitride on its side wall, thus causes The resistance value of the bit line of memory increases.
Therefore, there is still a need for bit line structures of memory of a kind of improvement and forming method thereof for the technical field at present, with solution Certainly the deficiencies in the prior art and disadvantage.
Summary of the invention
The main purpose of the present invention is to provide a kind of production methods of semiconductor structure, can solve the prior art not Foot and disadvantage.
One embodiment of the invention provides a kind of production method of semiconductor structure, includes: providing a substrate；On this substrate A bit line is formed, wherein the bit line includes cap rock in a tungsten metal layer and one, and cap rock is located in the tungsten metal layer on this；And into One low-temperature physics of row vapor deposition manufacture craft, one silicon nitride gap parietal layer of deposition cover the bit line and the substrate, wherein the nitrogen SiClx gap wall layer directly contacts the tungsten metal layer.Wherein low-temperature physics vapor deposition manufacture craft ties up at 200~400 DEG C It carries out.
For above-mentioned purpose of the invention, feature and advantage can be clearer and more comprehensible, preferred embodiment is cited below particularly, and match Appended attached drawing is closed, is described in detail below.However following preferred embodiment and attached drawing it is only for reference with illustrate to use, not For the present invention is limited person.
Detailed description of the invention
Fig. 1 and Fig. 2 is the diagrammatic cross-section of the production method of production semiconductor structure depicted in one embodiment of the invention.
Main element symbol description
10 bit lines
100 substrates
102 polysilicon layers
103 titanium coatings
104 titanium nitride layers
105 tungsten silicide layers
106 tungsten metal layers
Cap rock on 107
110 silicon nitride gap parietal layers
Specific embodiment
Hereinafter, illustrate details with reference to the accompanying drawings, the content in those attached drawings also constitutes the one of specification datail description Part, and be painted with the special case describing mode of the practicable embodiment.Examples below, which has described enough details, makes this The general technology personage in field is implemented.
Certainly, other embodiments can also be adopted, or are made under the premise of not departing from embodiment described in text any Change in structural, logicality and electrical property.Therefore, following detailed description is not considered as limiting, conversely, wherein institute The embodiment for including will be defined by appended claims.
The present invention provides a kind of production method of semiconductor structure, for example, the bit line of memory, can have lower resistance Value.
Fig. 1 and Fig. 2 is please referred to, the production method to make semiconductor structure depicted in an embodiment according to the present invention Diagrammatic cross-section.As shown in Figure 1, a substrate 100 is provided, for example, silicon base.A bit line 10 is formed in substrate 100.According to The embodiment of the present invention, bit line 10 are the stacked structures of multilayer material film, from the bottom to top sequentially include a polysilicon layer 102, a titanium Metal layer 103, titanium nitride (TiN) layer 104, a tungsten silicide (WSi) layer 105, cap rock 107 in a tungsten metal layer 106 and one.
According to embodiments of the present invention, upper cap rock 107 is located in tungsten metal layer 106, and directly contacts with tungsten metal layer 106. According to embodiments of the present invention, upper cap rock 107 includes a silicon nitride layer.
According to embodiments of the present invention, polysilicon layer 102 is between substrate 100 and tungsten metal layer 106.Titanium coating 103 Between polysilicon layer 102 and tungsten metal layer 106.Titanium nitride layer 104 is between titanium coating 103 and tungsten metal layer 106. Tungsten silicide layer 105 is between titanium nitride layer 104 and tungsten metal layer 106.
As shown in Fig. 2, then carrying out low-temperature physics vapor deposition manufacture craft in 10 surface of bit line and 100 surface of substrate Conformal one silicon nitride gap parietal layer 110 of deposition.According to embodiments of the present invention, silicon nitride gap parietal layer 110 directly contacts tungsten gold Belong to layer 106.
According to embodiments of the present invention, above-mentioned low-temperature physics vapor deposition manufacture craft is carried out at 200~400 DEG C.? The physical vapour deposition (PVD) carried out under this relative low temperature environment not will lead to nitrogen and react generation nitridation with the tungsten metal layer of stacked structure Tungsten is on bit line side wall, therefore its resistance value is lower.
The foregoing is merely the preferred embodiment of the present invention, all equivalent changes done according to the claims in the present invention with repair Decorations, should all belong to the scope of the present invention.

Claims (8)

1. a kind of method for making semiconductor structure, characterized by comprising:
One substrate is provided；
A bit line is formed on this substrate, and wherein the bit line packet contains tungsten metal layer and upper cap rock, and cap rock is located at the tungsten metal on this On layer；And
Low-temperature physics vapor deposition manufacture craft is carried out, one silicon nitride gap parietal layer of deposition covers the bit line and the substrate, In the silicon nitride gap parietal layer directly contact the tungsten metal layer.
2. the method for production semiconductor structure as described in claim 1, wherein the bit line additionally comprises polysilicon layer, between the base Between bottom and the tungsten metal layer.
3. the method for production semiconductor structure as claimed in claim 2, wherein the bit line additionally comprises titanium coating, more between this Between crystal silicon layer and the tungsten metal layer.
4. the method for production semiconductor structure as claimed in claim 3, wherein the bit line additionally comprises titanium nitride layer, between the titanium Between metal layer and the tungsten metal layer.
5. the method for production semiconductor structure as claimed in claim 4, wherein the bit line additionally comprises tungsten silicide layer, between the nitrogen Change between titanium layer and the tungsten metal layer.
6. the method for production semiconductor structure as described in claim 1, wherein cap rock includes silicon nitride layer on this.
7. as described in claim 1 production semiconductor structure method, wherein the low-temperature physics vapor deposition manufacture craft be It is carried out at 200~400 DEG C.
8. semiconductor structure made by a kind of any one according to claim 1 to 7.
CN201810072028.4A 2018-01-25 2018-01-25 The method for making semiconductor structure Pending CN110085591A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201810072028.4A CN110085591A (en) 2018-01-25 2018-01-25 The method for making semiconductor structure
US15/888,069 US20190229014A1 (en) 2018-01-25 2018-02-04 Method for fabricating a semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810072028.4A CN110085591A (en) 2018-01-25 2018-01-25 The method for making semiconductor structure

Publications (1)

Publication Number Publication Date
CN110085591A true CN110085591A (en) 2019-08-02

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CN (1) CN110085591A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6165894A (en) * 1998-07-09 2000-12-26 Advanced Micro Devices, Inc. Method of reliably capping copper interconnects
US6239014B1 (en) * 1999-08-16 2001-05-29 Vanguard International Semiconductor Corporation Tungsten bit line structure featuring a sandwich capping layer
KR20090056673A (en) * 2007-11-30 2009-06-03 주식회사 하이닉스반도체 Method for forming electrode of semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6358810B1 (en) * 1998-07-28 2002-03-19 Applied Materials, Inc. Method for superior step coverage and interface control for high K dielectric capacitors and related electrodes
US9633839B2 (en) * 2015-06-19 2017-04-25 Applied Materials, Inc. Methods for depositing dielectric films via physical vapor deposition processes
US10103194B2 (en) * 2016-09-26 2018-10-16 Omnivision Technologies, Inc. Self-aligned optical grid on image sensor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6165894A (en) * 1998-07-09 2000-12-26 Advanced Micro Devices, Inc. Method of reliably capping copper interconnects
US6239014B1 (en) * 1999-08-16 2001-05-29 Vanguard International Semiconductor Corporation Tungsten bit line structure featuring a sandwich capping layer
KR20090056673A (en) * 2007-11-30 2009-06-03 주식회사 하이닉스반도체 Method for forming electrode of semiconductor device

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US20190229014A1 (en) 2019-07-25

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Application publication date: 20190802

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