CN110085591A - 制作半导体结构的方法 - Google Patents

制作半导体结构的方法 Download PDF

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Publication number
CN110085591A
CN110085591A CN201810072028.4A CN201810072028A CN110085591A CN 110085591 A CN110085591 A CN 110085591A CN 201810072028 A CN201810072028 A CN 201810072028A CN 110085591 A CN110085591 A CN 110085591A
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layer
bit line
semiconductor structure
metal layer
tungsten metal
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林冠君
黄信富
陈威志
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Priority to CN201810072028.4A priority Critical patent/CN110085591A/zh
Priority to US15/888,069 priority patent/US20190229014A1/en
Publication of CN110085591A publication Critical patent/CN110085591A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Abstract

本发明公开一种制作半导体结构的方法，包含：提供一基底；在该基底上形成一位线，其中该位线包含一钨金属层及一上盖层，该上盖层位于该钨金属层上；以及进行一低温物理气相沉积制作工艺，沉积一氮化硅间隙壁层覆盖该位线与该基底，其中该氮化硅间隙壁层直接接触该钨金属层。其中该低温物理气相沉积制作工艺是在200～400℃下进行。

Description

制作半导体结构的方法
技术领域
本发明涉及一种半导体结构及其形成方法，特别是涉及一种存储器的位线结构及其形成方法。
背景技术
随着非挥发性存储器的集成度的日益提升，存储器的位线线宽也必须缩小。然而，位线的线宽变小会造成其阻值的上升，使得存储单元的电流变小而导致过高的位线负载(bit line loading)。由此可知，存储器的位线阻值对于存储器的操作效能十分重要。
通常，存储器的位线包含多层材料膜的堆叠结构，例如，在多晶硅层上设有一钨金属层，然后，在钨金属层上设有一氮化硅上盖层。在完成上述堆叠结构的蚀刻之后，再以化学气相沉积制作工艺于堆叠结构上沉积一氮化硅间隙壁层，然而，在上述化学气相沉积制作工艺的高温环境中，氮会与堆叠结构的钨金属层反应生成氮化钨在其侧壁上，因而导致存储器的位线的阻值升高。
因此，目前该技术领域仍需要一种改良的存储器的位线结构及其形成方法，以解决现有技术的不足与缺点。
发明内容
本发明的主要目的在于提供一种半导体结构的制作方法，可以解决现有技术的不足与缺点。
本发明一实施例提供一种半导体结构的制作方法，包含：提供一基底；在该基底上形成一位线，其中该位线包含一钨金属层及一上盖层，该上盖层位于该钨金属层上；以及进行一低温物理气相沉积制作工艺，沉积一氮化硅间隙壁层覆盖该位线与该基底，其中该氮化硅间隙壁层直接接触该钨金属层。其中该低温物理气相沉积制作工艺系在200～400℃下进行。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1及图2为本发明一实施例所绘示的制作半导体结构的制作方法的剖面示意图。
主要元件符号说明
10 位线
100 基底
102 多晶硅层
103 钛金属层
104 氮化钛层
105 硅化钨层
106 钨金属层
107 上盖层
110 氮化硅间隙壁层
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
本发明提供一种半导体结构的制作方法，例如，存储器的位线，可以具有较低的阻值。
请参阅图1及图2，其为依据本发明一实施例所绘示的制作半导体结构的制作方法的剖面示意图。如图1所示，提供一基底100，例如，硅基底。在基底100上形成一位线10。根据本发明实施例，位线10是多层材料膜的堆叠结构，由下至上依序包含一多晶硅层102、一钛金属层103、一氮化钛(TiN)层104、一硅化钨(WSi)层105、一钨金属层106及一上盖层107。
根据本发明实施例，上盖层107位于钨金属层106上，且与钨金属层106直接接触。根据本发明实施例，上盖层107包含一氮化硅层。
根据本发明实施例，多晶硅层102介于基底100与钨金属层106之间。钛金属层103介于多晶硅层102与钨金属层106之间。氮化钛层104介于钛金属层103与钨金属层106之间。硅化钨层105介于氮化钛层104与钨金属层106之间。
如图2所示，接着进行一低温物理气相沉积制作工艺于位线10表面与基底100表面顺形的沉积一氮化硅间隙壁层110。根据本发明实施例，氮化硅间隙壁层110直接接触钨金属层106。
根据本发明实施例，上述低温物理气相沉积制作工艺是在200～400℃下进行。在此相对低温环境下进行的物理气相沉积，不会导致氮与堆叠结构的钨金属层反应生成氮化钨在位线侧壁上，故其阻值较低。
以上所述仅为本发明之优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (8)

1.一种制作半导体结构的方法，其特征在于，包含：
提供一基底；
在该基底上形成一位线，其中该位线包含钨金属层及上盖层，该上盖层位于该钨金属层上；以及
进行一低温物理气相沉积制作工艺，沉积一氮化硅间隙壁层覆盖该位线与该基底，其中该氮化硅间隙壁层直接接触该钨金属层。
2.如权利要求1所述的制作半导体结构的方法，其中该位线另包含多晶硅层，介于该基底与该钨金属层之间。
3.如权利要求2所述的制作半导体结构的方法，其中该位线另包含钛金属层，介于该多晶硅层与该钨金属层之间。
4.如权利要求3所述的制作半导体结构的方法，其中该位线另包含氮化钛层，介于该钛金属层与该钨金属层之间。
5.如权利要求4所述的制作半导体结构的方法，其中该位线另包含硅化钨层，介于该氮化钛层与该钨金属层之间。
6.如权利要求1所述的制作半导体结构的方法，其中该上盖层包含氮化硅层。
7.如权利要求1所述的制作半导体结构的方法，其中该低温物理气相沉积制作工艺是在200～400℃下进行。
8.一种依据权利要求1至7的任一项所制作的半导体结构。
CN201810072028.4A 2018-01-25 2018-01-25 制作半导体结构的方法 Pending CN110085591A (zh)

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US15/888,069 US20190229014A1 (en) 2018-01-25 2018-02-04 Method for fabricating a semiconductor structure

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Citations (3)

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US6239014B1 (en) * 1999-08-16 2001-05-29 Vanguard International Semiconductor Corporation Tungsten bit line structure featuring a sandwich capping layer
KR20090056673A (ko) * 2007-11-30 2009-06-03 주식회사 하이닉스반도체 반도체 소자의 전극 형성방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6358810B1 (en) * 1998-07-28 2002-03-19 Applied Materials, Inc. Method for superior step coverage and interface control for high K dielectric capacitors and related electrodes
US9633839B2 (en) * 2015-06-19 2017-04-25 Applied Materials, Inc. Methods for depositing dielectric films via physical vapor deposition processes
US10103194B2 (en) * 2016-09-26 2018-10-16 Omnivision Technologies, Inc. Self-aligned optical grid on image sensor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6165894A (en) * 1998-07-09 2000-12-26 Advanced Micro Devices, Inc. Method of reliably capping copper interconnects
US6239014B1 (en) * 1999-08-16 2001-05-29 Vanguard International Semiconductor Corporation Tungsten bit line structure featuring a sandwich capping layer
KR20090056673A (ko) * 2007-11-30 2009-06-03 주식회사 하이닉스반도체 반도체 소자의 전극 형성방법

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