CN101882610B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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CN101882610B
CN101882610B CN2009101517298A CN200910151729A CN101882610B CN 101882610 B CN101882610 B CN 101882610B CN 2009101517298 A CN2009101517298 A CN 2009101517298A CN 200910151729 A CN200910151729 A CN 200910151729A CN 101882610 B CN101882610 B CN 101882610B
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semiconductor structure
conductive pattern
dielectric layer
tungsten
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罗翊仁
邱钰珊
苏国辉
林江宏
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Nanya Technology Corp
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Abstract

本发明公开了一种半导体结构及其制造方法。一种半导体结构，包括：基材；介电层，设于该基材上；导电图案，设于该介电层上，且该导电图案包括上表面及侧壁；以及金属薄膜，仅选择性地沉积在该导电图案的上表面及侧壁上，而不沉积在该介电层上。

Description

半导体结构及其制造方法
技术领域
本发明涉及半导体技术，特别涉及一种半导体结构，例如一种垂直沟道晶体管的金属栅极或字线结构，以及相关于这种半导体结构的工艺方法。
背景技术
随着电路集成度的增加，半导体工艺中针对膜厚的均一性及工艺控制也显得日益重要。目前业界已发展出许多工艺技术，其能够在半导体基材上以较经济的方式沉积出材料薄膜，并且能够有效的控制薄膜的特性。
例如，选择性化学气相沉积工艺等选择性沉积方法即为周知技艺，其可以被用来在集成电路工艺中选择性地在特定半导体结构的表面上沉积材料薄膜，由此可以避免传统的光刻、蚀刻及光致抗蚀剂剥除等较为繁杂的步骤。选择性化学气相沉积工艺的优点在于可应用在各种的半导体结构上，加上有自动对准的特性，故能够配合更严格的设计规范。
然而，目前的选择性沉积方法仍有缺点。举例来说，选择性沉积方法常被用来在接触洞中生长钨金属层，而在进行钨金属的生长或沉积步骤之前，必须先对接触洞进行一连串的清洗步骤，以确保硅表面的洁净度。若有反应离子蚀刻(Reactive Ion Etching，RIE)所造成的RIE伤害层存在于接触洞的底部，就无法在接触洞中生长钨金属层，因为RIE伤害层会在选择性沉积过程中扮演类似绝缘层的角色。因此，RIE伤害层必须在金属膜生长前被完全清除。
此外，目前的选择性沉积方法似乎仍然无法在非硅基的金属底层上形成厚度超薄(小于15纳米)、具高度膜厚均一性，同时又能够在结构上连续的选择性沉积薄膜，例如，钨金属薄膜。再者，要能够在介电层与金属底层之间维持足够高的选择性，而又要同时沉积出均厚且超薄的金属薄膜，以目前工艺水准而言仍是属于十分困难的技术。
由此可知，目前业界仍需要一种改良的半导体结构及制造方法，以配合在某些应用中需要均厚且超薄的薄膜，且这样的薄膜可以被选择性地沉积在非硅基的金属底层，同时在介电层与该金属底层之间具有非常高的选择性。此外，前述形成均厚且超薄的薄膜的方法还需有经济、快速等特性，并具有高产出能力。
发明内容
本发明的主要目的在提供一种改良的半导体结构，例如一种垂直沟道晶体管的金属栅极或字线结构，以及相关于这种半导体结构的工艺方法，以解决先前技艺的问题与缺点。
本发明提供半导体结构，包括基材；介电层，设于该基材上；导电图案，设于该介电层上，且该导电图案包括上表面及侧壁；以及金属薄膜，仅选择性地沉积在该导电图案的上表面及侧壁上，而不沉积在该介电层上。
根据本发明另一优选实施例，提供一种制作半导体结构的方法，包含有：提供基材；于该基材上形成介电层；于该介电层的主表面上形成导电图案，该导电图案具有上表面以及侧壁；以及进行选择性原子层沉积工艺，选择性地在该导电图案的该上表面及该侧壁上沉积均厚金属层，但使该介电层的该主表面实质上无该金属薄膜形成。
附图说明
图1为依据本发明一优选实施例所绘示的集成电路中的半导体结构剖面示意图。
图2为依据本发明优选实施例所绘示的制作图1中的半导体结构的方法流程图。
附图标记说明
1    半导体结构              10    半导体基材
12   介电层                  12a   主表面
14   导电图案                14a   上表面
14b  侧壁                    16    金属薄膜
20   方法                    21    提供基材
22   形成介电层              23    形成金属图案
24   导入硅甲烷(或氢气)      25    抽真空
26   导入钨前驱物            27    惰性气体吹除
28    重复步骤24-27
具体实施方式
图1为依据本发明一优选实施例所绘示的集成电路中的半导体结构剖面示意图。如图1所示，半导体结构1包含半导体基材10，例如，硅基材；介电层12，设于该半导体基材10上；导电图案14，形成在介电层12的主表面12a上；以及超薄的金属薄膜16，选择性地沉积在导电图案14的上表面14a及侧壁14b上。其中，金属薄膜16实质上不会直接长在介电层12的主表面12a上。
根据本发明，半导体结构1可以是金属栅极晶体管元件，而介电层12做为该金属栅极晶体管元件的栅极介电层或栅极氧化层。本发明特别适合应用在金属栅极、垂直沟道晶体管元件，这样的元件可以被应用在先进的动态随机存取存储器(DRAM)技术中，其中，金属薄膜16可以用来降低字线的阻值。此外，在前述技术中，为顾及金属栅极晶体管元件的功函数，通常要求金属薄膜16具有超薄厚度(小于15纳米左右)，同时需为结构上连续且厚度均一的高品质材料层。
依据本发明的优选实施例，介电层12可以包含有氧化硅、氮化硅或氮氧化硅等。导电图案14可以包含有钛、氮化钛、钽、氮化钽、铝、铜、金、钨、硅化金属或上述任意组合或合金。优选地，导电图案14是由氮化钛所构成，而金属薄膜16是以原子沉积法所形成的厚度小于15纳米的钨金属层。此外，优选地，可以是属于金属栅极或者字线一部分的导电图案14，其厚度同样要小于15纳米，例如，介于6到8纳米之间。
图2为依据本发明优选实施例所绘示的制作图1中的半导体结构1的方法20流程图。如图2所示，在步骤21中，首先提供半导体基材，如图1中所绘示的半导体基材10，接着在步骤22中，在半导体基材表面上以热氧化或热生长法形成介电层，如图1中所绘示的介电层12，其中，该介电层可以包含有氧化硅、氮化硅或氮氧化硅等。
在步骤23中，在介电层的主表面上形成金属图案，例如图1中所绘示的导电图案14，其中该金属图案可以包含有钛、氮化钛、钽、氮化钽、铝、铜、金、钨、硅化金属或上述任意组合或合金。优选地，该金属图案是由氮化钛所构成，且该金属图案是以湿法蚀刻法所形成的。例如，在例如氮化钛的金属层上形成遮盖层，例如多晶硅层，此遮盖层仅仅盖住金属层的上表面，但暴露出金属层的侧壁，随后再以湿法蚀刻法蚀刻掉金属层的侧壁，如此形成该金属图案。最后，移除该遮盖层，暴露出金属图案的上表面。
在形成金属图案之后，接着进行选择性钨原子层沉积工艺(selectivetungsten atomic layer deposition process)，选择性地在前述金属图案上长出超薄且均厚的钨金属薄膜，例如图1中所绘示的金属薄膜16。根据本发明，前述超薄且均厚的钨金属薄膜的厚度小于15纳米，且具有良好的阶梯覆盖(stepcoverage)特性。前述的选择性钨原子层沉积工艺可包括进行多次原子层沉积循环(ALD cycle)，以达到在金属图案上所要的钨金属薄膜的沉积厚度。为简化说明，图2中仅显示单一次的原子层沉积循环(步骤24至27)。
依据本发明的优选实施例，前述的原子层沉积循环包括：(1)将含氢物质，例如硅甲烷或氢气，导入反应室中，并维持预定时间，使得氢自由基能够吸附在介电层的主表面上以及金属图案的表面上(步骤24)；(2)将反应室抽真空，同时暂停所有气体供应，选择性地将先前吸附在介电层的主表面上的氢自由基去除(步骤25)；(3)将钨前驱物，例如六氟化钨(WF6)导入反应室中，并维持在低压下(低于5torr)，以及低温下(低于300℃)，使钨前驱物与吸附在金属图案表面上的氢自由基反应，如此选择性地在金属图案表面上沉积出钨金属薄膜(步骤26)；以及(4)以惰性气体，例如，氩气，进行反应室的吹除，以移除反应副产物(步骤27)。如前所述，为了达到所要的厚度，上述原子层沉积循环可以重复进行(步骤28)。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (18)

1.一种半导体结构，包含有：
基材；
介电层，设于该基材上；
导电图案，设于该介电层的主表面上，且该导电图案包括上表面及侧壁；以及
金属薄膜，包覆住该导电图案，包括该上表面及该侧壁，但该介电层的该主表面无该金属薄膜形成，且该金属薄膜的厚度小于15纳米。
2.如权利要求1所述的半导体结构，其特征在于该介电层包含氧化硅、氮化硅或氮氧化硅。
3.如权利要求1所述的半导体结构，其特征在于该导电图案包含钛、氮化钛、钽、氮化钽、铝、铜、金、钨、硅化金属或上述组合或合金。
4.如权利要求1所述的半导体结构，其特征在于该金属薄膜包含钨。
5.如权利要求1所述的半导体结构，其特征在于该导电图案由氮化钛所构成。
6.如权利要求5所述的半导体结构，其特征在于该金属薄膜是钨金属层。
7.如权利要求1所述的半导体结构，其特征在于该介电层为垂直沟道晶体管的栅极介电层。
8.如权利要求7所述的半导体结构，其特征在于该导电图案为金属栅极或字线的一部分。
9.如权利要求8所述的半导体结构，其特征在于该导电图案的厚度小于15纳米。
10.如权利要求8所述的半导体结构，其特征在于该导电图案的厚度介于6到8纳米。
11.一种制作半导体结构的方法，包含有：
提供基材；
于该基材上形成介电层；
于该介电层的主表面上形成导电图案，该导电图案具有上表面以及侧壁；以及
进行选择性原子层沉积工艺，选择性地在该导电图案的该上表面及该侧壁上沉积均厚金属薄膜，但使该介电层的该主表面无该金属薄膜形成，且该金属薄膜的厚度小于15纳米。
12.如权利要求11所述的制作半导体结构的方法，其特征在于该择性原子层沉积工艺包含以下步骤：
(1)将含氢物质导入反应室中，并维持预定时间，使得氢自由基能够吸附在介电层的主表面上以及导电图案的表面上；
(2)将反应室抽真空，同时暂停所有气体供应，选择性地将先前吸附在介电层的主表面上的氢自由基去除；
(3)将钨前驱物导入反应室中，并维持在压力低于5torr及温度低于300℃下，使钨前驱物与吸附在导电图案表面上的氢自由基反应，如此选择性地在导电图案表面上沉积出钨金属薄膜；以及
(4)进行反应室的吹除，以移除反应副产物。
13.如权利要求12所述的制作半导体结构的方法，其特征在于该含氢物质包含硅甲烷或氢气。
14.如权利要求12所述的制作半导体结构的方法，其特征在于该钨前驱物包含六氟化钨。
15.如权利要求11所述的制作半导体结构的方法，其特征在于该介电层包含氧化硅、氮化硅或氮氧化硅。
16.如权利要求11所述的制作半导体结构的方法，其特征在于该导电图案包含钛、氮化钛、钽、氮化钽、铝、铜、金、钨、硅化金属或上述组合或合金。
17.如权利要求11所述的制作半导体结构的方法，其特征在于该均厚金属薄膜包含钨。
18.如权利要求11所述的制作半导体结构的方法，其特征在于该导电图案的厚度小于15纳米。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9460932B2 (en) * 2013-11-11 2016-10-04 Applied Materials, Inc. Surface poisoning using ALD for high selectivity deposition of high aspect ratio features
US9659864B2 (en) * 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for forming self-aligned via with selectively deposited etching stop layer
US20200006274A1 (en) * 2018-06-29 2020-01-02 Powertech Technology Inc. Semiconductor package and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5576928A (en) * 1994-08-01 1996-11-19 Texas Instruments Incorporated High-dielectric-constant material electrodes comprising thin platinum layers
US6268621B1 (en) * 1999-08-03 2001-07-31 International Business Machines Corporation Vertical channel field effect transistor
CN1507653A (zh) * 2001-01-11 2004-06-23 ����Τ�����ʹ�˾ 用于窄隙填充用途的介电薄膜
US7214602B2 (en) * 1999-03-01 2007-05-08 Micron Technology, Inc. Method of forming a conductive structure

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5126283A (en) * 1990-05-21 1992-06-30 Motorola, Inc. Process for the selective encapsulation of an electrically conductive structure in a semiconductor device
JPH04302151A (ja) * 1991-03-29 1992-10-26 Toshiba Corp 電荷結合装置の製造方法
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5506449A (en) * 1993-03-24 1996-04-09 Kawasaki Steel Corporation Interconnection structure for semiconductor integrated circuit and manufacture of the same
US5413953A (en) * 1994-09-30 1995-05-09 United Microelectronics Corporation Method for planarizing an insulator on a semiconductor substrate using ion implantation
JPH08115984A (ja) 1994-10-17 1996-05-07 Hitachi Ltd 半導体装置及びその製造方法
US6136687A (en) * 1997-11-26 2000-10-24 Integrated Device Technology, Inc. Method of forming air gaps for reducing interconnect capacitance
US6110768A (en) * 1999-03-04 2000-08-29 United Microelectronics Corp. Method of manufacturing aluminum gate electrode
US6391795B1 (en) * 1999-10-22 2002-05-21 Lsi Logic Corporation Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
US7405158B2 (en) * 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US7205604B2 (en) * 2001-03-13 2007-04-17 International Business Machines Corporation Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof
TW508677B (en) * 2001-11-06 2002-11-01 Vanguard Int Semiconduct Corp Transistor with W/Tin gate fabricated
US6858524B2 (en) * 2002-12-03 2005-02-22 Asm International, Nv Method of depositing barrier layer for metal gates
KR100871465B1 (ko) * 2003-02-13 2008-12-03 도쿄엘렉트론가부시키가이샤 반도체 장치의 제조방법, 실리콘 산화막 형성방법 및 반도체 제조장치
KR100520837B1 (ko) * 2003-04-01 2005-10-13 삼성전자주식회사 반도체 소자의 제조방법
US7514353B2 (en) * 2005-03-18 2009-04-07 Applied Materials, Inc. Contact metallization scheme using a barrier layer over a silicide layer
TWI329135B (en) * 2005-11-04 2010-08-21 Applied Materials Inc Apparatus and process for plasma-enhanced atomic layer deposition
US7473946B2 (en) * 2006-02-22 2009-01-06 International Business Machines Corporation CMOS structure and method including multiple crystallographic planes
JP2007305681A (ja) * 2006-05-09 2007-11-22 Elpida Memory Inc 半導体装置の製造方法
GB2441355B (en) * 2006-08-31 2009-05-20 Cambridge Display Tech Ltd Organic electronic device
JP4302151B2 (ja) 2007-04-20 2009-07-22 本田技研工業株式会社 車両用フロアパネル
US20090057780A1 (en) * 2007-08-27 2009-03-05 International Business Machines Corporation Finfet structure including multiple semiconductor fin channel heights

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5576928A (en) * 1994-08-01 1996-11-19 Texas Instruments Incorporated High-dielectric-constant material electrodes comprising thin platinum layers
US7214602B2 (en) * 1999-03-01 2007-05-08 Micron Technology, Inc. Method of forming a conductive structure
US6268621B1 (en) * 1999-08-03 2001-07-31 International Business Machines Corporation Vertical channel field effect transistor
CN1507653A (zh) * 2001-01-11 2004-06-23 ����Τ�����ʹ�˾ 用于窄隙填充用途的介电薄膜

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JP特开2005-12214A 2005.01.13
JP特开平4-302151A 1992.10.26

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