KR100587056B1 - Method for forming contact hole of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a contact hole in a semiconductor device, the method comprising: forming a first insulating film on a semiconductor substrate and then forming a conductive layer wiring on the first insulating film; Forming a second insulating film on the first insulating film including the conductive layer wiring, and then sequentially forming an upper electrode polysilicon layer and a low etch rate material layer on the second insulating film; Etching only the low etch rate material layer and the polysilicon layer on the conductive layer wiring and the semiconductor substrate; And forming a third insulating film on the resultant, and then forming an upper electrode contact hole, a conductive layer wiring contact hole, and a semiconductor substrate contact hole in the insulating film.

Description

Method for forming contact hole of semiconductor device             

1 is a process cross-sectional view showing a method for forming a contact hole in a semiconductor device according to the prior art.

2A through 2D are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.

3 is an enlarged view of the upper electrode part of FIG. 2D;

Figure 4 is a graph showing the reduction of the resistance value and the deviation of the plate chain compared to the metal contact according to the prior art and the present invention.

(Code description of main parts of drawing)

100 semiconductor substrate 110 first insulating film

120: bit line 130: nitride film

140: second insulating film 150: polysilicon layer

150b: upper electrode 160, 160a, 160b: low etch rate material layer

170: first photoresist 180: third insulating film

190: second photoresist 200: contact hole for upper electrode contact

300: contact hole for word line contact 400: contact hole for semiconductor substrate contact

The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device for stabilizing resistance in a contact hole.

In general, in the DRAM, a contact hole etching process is performed to connect a wire to a semiconductor substrate, a bit line, a word line, or the like after the formation of the upper electrode. In this case, the material layer to be etched is an interlayer insulating film and is typically a material layer of an oxide film series or a nitride film series.

In addition, in order to secure a margin of the lithography process according to the improvement of the integration degree of the semiconductor device, a CMP (Chemical Mechanical Polishing) process is introduced and used in the manufacturing process of many semiconductor devices.

However, in the case of the CMP process, the thin film portion must remain even after the flattening process, so there is a problem that a thin film thicker than the thin film portion to be planarized must be deposited.

In addition, the deposition uniformity and the deposition thickness of the etching material layer are required to secure a margin (uniformity within wafer, uniformity between wafers, etc.) in the CMP process.

In this case, as shown in FIG. 1, a semiconductor substrate (not shown), a bit line (or word line) (not shown), an upper electrode 15, or the like, which is a part where the contact hole 20 for the wiring process is opened, is shown. The contact hole etch depth is very different.

Therefore, when the contact hole etching process is performed by adjusting the contact hole etching depth to a deep portion, there is a problem in that the contact hole etching depth is low, that is, the upper electrode 15 receives relatively severe plasma etching damage.

Assuming that a typical contact hole geometry is circular, the contact area Z between the upper electrode and the contact hole filling material can be obtained by the following formula Z = 2πr × h.

Where r is the radius of the contact hole and h is the thickness of the upper electrode being punched.

In particular, in the case of the conventional upper electrode made of polysilicon, the punch is generated by opening the upper electrode when the contact hole is etched. As a result, all of the line patterns in the region having a low contact hole etching depth are etched during the etching process, resulting in a large contact resistance due to a difference in the contact area (Z) between the lower layer pattern and the bridge or contact hole.

In particular, when PVD Ti / PVD or CVD TiN is used as the barrier metal among the contact hole filling materials, the contact area between the upper electrode and the contact hole filling material is very small, and thus silicide formation is not performed properly. There is a problem that the contact resistance value increases.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and provides a method for forming a contact hole of a semiconductor device capable of reducing the contact resistance displacement caused by the difference in the etching depth of the contact hole and realizing stable device characteristics. There is a purpose.                         

In addition, another object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of improving yield by preventing bridges with a lower layer pattern generated by a contact hole etching process having a large difference in contact hole etching depths.

The present invention for achieving the above object, the step of forming a first insulating film on a semiconductor substrate and then forming a conductive layer wiring on the first insulating film; After the second insulating film is formed on the first insulating film including the conductive layer wiring, the polysilicon layer for the upper electrode and the low etch rate material layer made of a two-component metal compound or a two-component silicon compound are sequentially formed on the second insulating film. Forming; Etching only the low etch rate material layer and the polysilicon layer on the conductive layer wiring and the semiconductor substrate; And forming an upper electrode contact hole, a conductive layer wiring contact hole, and a semiconductor substrate contact hole in the insulating film after the third insulating film is formed on the resultant.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views illustrating processes for forming a contact hole in a semiconductor device according to the present invention.

First, as shown in FIG. 2A, after forming the first insulating layer 110 on the semiconductor substrate 100, the bit line (or word line) 120 and the nitride layer 130 are formed. Subsequently, the second insulating layer 140 is sequentially formed on the entirety of the resultant product, and then the polysilicon layer 150 for the upper electrode is formed on the second insulating layer 140.

Subsequently, a low etch rate material layer 160, which is a material layer having a low contact hole etch rate, is deposited on the upper surface of the polysilicon layer 150, and then patterned by forming a first photoresist thereon.

The reason for depositing the material layer 160b having the low etch rate on the upper electrode 150b in which the punch is generated is that the contact hole for the upper electrode contact, the bit line or the word line contact, and the contact hole for the semiconductor substrate contact. When the contact hole etching process (contact hole etching using a fluorine (F) source) having an etching height difference of more than 5000Å is performed, the upper electrode 150b and the contact hole filling are filled due to the punch in the contact hole 200 opened at a lower portion. The contact area Z with the material decreases, thereby increasing the contact resistance value, which is to prevent this.

The low etch rate material layer 160b may be formed using SixNy, SiOxNy, Ti, TiSix, TiN, or TaON.

In addition, the low etch rate material layer 160b may be formed using TiSix, CoSix, TiN, TiOxNy or TaOxNy, which are two or more metal compounds.

The metal compound may be formed by a sputtering method or a thermal reduction method. Further, the low etch rate material layer 160b may use SiOxNy or SixNy, which are two or more silicon compounds. Such two-component or higher silicon compounds can be formed by a thermal reduction method using a SiH ₄ source.

In particular, when the barrier metal is Ti / TiN for smooth filling of the contact hole filling material, a large difference in contact resistance occurs depending on whether the polysilicon upper electrode 150b is punched, which is the contact with the upper electrode 150b. This is because the TiSix layer at the upper electrode is further formed to the bottom of the contact hole as well as the contact area between the hole filling materials is increased.

In addition, the low etch rate material layer 160b may not be formed of a single material but may be formed of multiple layers, or may be a conductive material.

Meanwhile, another embodiment of the present invention will be described.

After depositing a single thin layer of low etch rate material (e.g. Ti), the metal thin film of low etch rate material may be reacted with a portion of the polysilicon layer by subsequent heat treatment to change it into a low etch rate material layer (e.g. TiSix). It may be.

The metal thin film may be formed to a thickness within 30% of the thickness of the polysilicon layer by sputtering using Ti, W, or Co, which is a metal of one component.

In addition, the heat treatment may be performed at 850 ° C. or less for less than 1 hour, and may be performed after the third insulating film is formed.

The low etch rate material layer 160b is deposited on the entire surface of the polysilicon layer as the upper electrode 150b after deposition, and may be deposited in a conventionally known manner. For example, a diffusion tube type nitride film, a PE-CVD type nitride film or an oxynitride film, a PVD type Ti, TiSix, TiN, TaON, or the like may be used as the low etch rate material layer.

When the low etch rate material layer 160b is formed on the upper electrode 150b as described above, the lower etch rate material layer 160b is lower than the etch rate of the polysilicon itself during the contact hole etching process.

The reason why the etching rate is lowered as described above is as follows.

In other words, the silicon etching process is a process of bonding Si-F using plasma and removing the bonded Si-F from the substrate as a volatile material. When silicon is present in a stable state by reacting with other compounds, it is stable during plasma etching. The etching rate is lowered because additional energy is required to dissociate the silicon compound.

In addition, when two or more stable materials 160b are present on the polysilicon upper electrode 150b, the etching rate of the polysilicon upper electrode 150b is lowered after dissociating and etching the stable phase material 160b. will be.

Next, as shown in FIG. 2B, the polysilicon layer 150a and the low etch rate material layer 160a for the upper electrode are formed by performing the exposure and etching process using the patterned first port resist 170 as a mask. do.

Subsequently, as illustrated in FIG. 2C, a third insulating layer 180 may be formed on the whole of the resultant product, and heat treatment may be performed if necessary.

Next, as shown in FIG. 2D, when the second photoresist 190 is formed on the third insulating layer 180 to perform an exposure and etching process for opening the contact hole, the upper electrode contact contact hole 200 is formed. ), A bit line or word line contact contact 300, and a semiconductor substrate contact hole 400. As a result, it is possible to implement a device having a stable resistance that no punch is generated.

In this case, the contact hole may be formed using Ti / TiN as a barrier metal, and the barrier metal may be formed by sputtering.

3 is an enlarged view illustrating the upper electrode part of FIG. 2D.

As shown in FIG. 3, the amount of etching loss of the upper electrode during the contact hole etching according to the related art can be obtained by the following equation.

That is, assuming that the conventional contact hole geometry is circular, the contact area Z between the upper electrode and the contact hole filling material in the case of punching during contact hole etching can be obtained by the following formula Z = 2πr × h.

In addition, the contact area Z 'between the upper electrode and the contact hole filling material in the case where no punch is generated during the contact hole etching according to the present invention can be obtained by the following formula Z' = 2πr × h '+ πr ² .

This allows Z '≥ Z,

Z '-Z ≥ 0,

(2πr × h '+ πr ² )-(2πr × h) ≥ 0,

r ≥ 2 (h-h '),

The loss amount h 'of the upper electrode is

h '≥ (2h-r) / 2,

Where r is the radius of the contact hole and h is the thickness of the upper electrode being punched.

As shown in FIG. 4, when the process is performed in this manner, it can be seen that the resistance value and the deviation of the plate chain compared to the metal-1 contact are greatly reduced.

As described above, the present invention has the effect that the variation of the contact resistance due to the difference in the etching depth of the contact hole is reduced and stable device characteristics can be realized. In particular, the effect is large in a memory device in which the upper electrode is made of polysilicon.

In addition, there is an effect that the yield can be improved by preventing the bridge with the lower layer pattern due to the contact hole etching process having a large difference in the etching depth of the contact hole.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (21)

Forming a conductive layer wiring on the first insulating layer after forming the first insulating layer on the semiconductor substrate; After the second insulating film is formed on the first insulating film including the conductive layer wiring, the polysilicon layer for the upper electrode and the low etch rate material layer made of a two-component metal compound or a two-component silicon compound are sequentially formed on the second insulating film. Forming; Etching only the low etch rate material layer and the polysilicon layer on the conductive layer wiring and the semiconductor substrate; And And forming a third insulating film on the resultant, and then forming an upper electrode contact hole, a conductive layer wiring contact hole, and a semiconductor substrate contact hole in the insulating film. Contact hole formation method. delete The method of claim 1, wherein the two-component or higher metal compound is TiSix, CoSix, TiN, TiOxNy or TaOxNy. The method of claim 1, wherein the two-component metal compound or more is formed by a sputtering method. The method of claim 1, wherein the two-component or more metal compound is formed by a thermal reduction method. delete The method of claim 1, wherein the two-component silicon compound or more is SiOxNy or SixNy. The method of claim 1, wherein the silicon compound having two or more components is formed by PE-CVD using a SiH ₄ source. 2. The method of claim 1, wherein the at least two-component silicon compound is formed by a thermal reduction method using a SiH ₄ source. The method of claim 1, wherein the contact hole for the upper electrode contact is formed using Ti / TiN as a barrier metal. The method of claim 10, wherein the barrier metal is formed by a sputtering method. Forming a metal layer wiring after forming a first insulating film on the semiconductor substrate; Forming a second insulating film on the first insulating film including the metal layer wiring, and then forming a polysilicon layer and a metal thin film for the upper electrode on the second insulating film; Heat-treating the upper portion of the thin film to change to a low etch rate material layer; Etching only the polysilicon layer on the bit line and the semiconductor substrate; And And forming a contact hole for the upper electrode contact, the contact hole for the metal layer contact, and the contact hole for the semiconductor substrate contact after forming the third insulating layer on the resultant. Way. 13. The method of claim 12, wherein the thin film is formed of a metal of one component type. 15. The method of claim 13, wherein the metal of one component is Ti, W, or Co. 15. The method of claim 13, wherein the metal of one component is formed by a sputtering method. The method of claim 12, wherein the heat treatment is performed at about 850 ° C. or less for less than 1 hour. The method of claim 12, wherein the heat treatment is performed after the third insulating film is formed. The method of claim 12, wherein the thin film is formed to a thickness within 30% of the thickness of the polysilicon layer. The method of claim 12, wherein the contact hole for the upper electrode contact comprises Ti / TiN as a barrier metal. 20. The method of claim 19, wherein the barrier metal is formed by a sputtering method. The loss amount (h ') of the upper electrode is 50% of the thickness (h) and contact hole radius (r) of the upper electrode according to the following equation h' = ≥ h-0.5r. The contact hole forming method of a semiconductor device, characterized in that formed above the difference value.

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