KR20080002548A - Method of manufacturing semiconductor device prevented abnormal oxidation of metal electrode - Google Patents

Method of manufacturing semiconductor device prevented abnormal oxidation of metal electrode Download PDF

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KR20080002548A
KR20080002548A KR1020060061435A KR20060061435A KR20080002548A KR 20080002548 A KR20080002548 A KR 20080002548A KR 1020060061435 A KR1020060061435 A KR 1020060061435A KR 20060061435 A KR20060061435 A KR 20060061435A KR 20080002548 A KR20080002548 A KR 20080002548A
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nitride film
semiconductor device
oxide film
manufacturing
patterns
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Korean (ko)
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한기현
남기원
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a semiconductor device preventing abnormal oxidation of a metal electrode is provided to reduce TAT(Turn Around Time) without nitride film etching and cleaning processes. A method for manufacturing a semiconductor device preventing abnormal oxidation of a metal electrode(24) includes the steps of: forming a plurality of patterns including metal electrodes on a semiconductor substrate(21) at predetermined intervals; forming a nitride film at a front surface of the semiconductor substrate with the patterns; changing the nitride layer on a surface of the semiconductor substrate between the patterns into a first oxide film; and depositing a second oxide film for interlayer insulating to fill a gap between the patterns on the first oxide film.

Description

메탈전극의 이상 산화를 방지할 수 있는 반도체소자의 제조 방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE PREVENTED ABNORMAL OXIDATION OF METAL ELECTRODE}Manufacturing method of semiconductor device which can prevent abnormal oxidation of metal electrode {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE PREVENTED ABNORMAL OXIDATION OF METAL ELECTRODE}

도 1a 및 도 1b는 종래기술에 따른 텅스텐전극을 사용한 게이트에서의 정상적인 상태와 이상산화가 발생한 상태를 도시한 사진.1A and 1B are photographs showing a normal state and abnormal state in a gate using a tungsten electrode according to the related art.

도 2는 종래기술에 따른 메탈전극의 이상산화 방지 방법을 도시한 도면.2 is a diagram illustrating a method for preventing abnormal oxidation of a metal electrode according to the related art.

도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체소자의 제조 방법을 도시한 도면.3A to 3C illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 4는 본 발명의 실시예에 따른 산화막 증착시 질화막의 변질로 생성되는 SiO2를 나타낸 사진.Figure 4 is a photograph showing the SiO 2 generated by the deterioration of the nitride film when the oxide film deposition according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체기판 22 : 게이트산화막21 semiconductor substrate 22 gate oxide film

23 : 폴리실리콘 24 : 메탈전극23 polysilicon 24 metal electrode

25 : 하드마스크질화막 26 : 질화막25: hard mask nitride film 26: nitride film

27A : RO-SiO2 27B : D-SiO2 27A: RO-SiO 2 27B: D-SiO 2

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 반도체소자 제조시에 메탈전극의 이상산화를 방지할 수 있는 반도체소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing abnormal oxidation of a metal electrode during semiconductor device manufacturing.

반도체메모리소자의 고집적화, 소형화 및 고속화에 따라 게이트 및 비트라인의 면적이 점점 감소하고 있으며, 텅스텐실리사이드(WSi) 등의 금속화합물을 게이트 및 비트라인의 전극으로 사용하는 경우 소자의 안정적인 전압을 얻을 수 있었으나 소자가 점점 미세화됨에 따라 저항 측면에서 불리하다.The area of gate and bit line is decreasing with high integration, miniaturization and high speed of semiconductor memory device, and stable voltage of device can be obtained when metal compound such as tungsten silicide (WSi) is used as gate and bit line electrode. However, as the device becomes increasingly finer, it is disadvantageous in terms of resistance.

따라서, 최근에는 DRAM 등의 소자 제조시에 게이트 및 비트라인의 전극으로금속화합물보다 특성이 좋은 W, Ti, Mo, Ni 등의 금속전극을 사용하고 있다.Therefore, in recent years, metal electrodes, such as W, Ti, Mo, and Ni, which have better characteristics than metal compounds, have been used as electrodes for gates and bit lines when manufacturing devices such as DRAMs.

그러나, 금속전극을 사용하는 게이트 및 비트라인 제조시에, 특히 게이트 제조시에 후속 공정으로 층간절연막으로 사용되는 산화막(Oxide) 증착시 적용되는 고온과 산소 가스에 의하여 이상 산화(Abnormal oxidation)가 발생하는 문제가 있다.However, abnormal oxidation occurs due to high temperature and oxygen gas applied during the deposition of an oxide film used as an interlayer insulating film in a subsequent process, particularly in the manufacture of gates and bit lines using metal electrodes. There is a problem.

도 1a 및 도 1b는 종래기술에 따른 텅스텐전극을 사용한 게이트에서의 정상적인 상태와 이상산화가 발생한 상태를 도시한 사진이다.1A and 1B are photographs showing a normal state and abnormal state in a gate using a tungsten electrode according to the related art.

이상산화가 발생된 도 1b를 참조하면, 텅스텐전극이 이상 산화되어 기형적으 로 면적이 늘어남을 알 수 있다.Referring to FIG. 1B in which abnormal oxidation occurs, it can be seen that the tungsten electrode is abnormally oxidized and the area is increased abnormally.

위와 같이 금속전극 사용시 후속 산화막 증착에 의한 이상 산화를 방지하기 위하여 질화막을 증착하는 방법이 제안되었다.As described above, a method of depositing a nitride film has been proposed in order to prevent abnormal oxidation by subsequent oxide film deposition when using a metal electrode.

도 2는 종래기술에 따른 메탈전극의 이상산화 방지 방법을 도시한 도면이다.2 is a diagram illustrating a method for preventing abnormal oxidation of a metal electrode according to the prior art.

도 2를 참조하면, 반도체기판(11) 상부에 게이트산화막(12), 폴리실리콘(13), 텅스텐전극(14) 및 하드마스크질화막(15)의 순서로 적층된 게이트를 형성한다.Referring to FIG. 2, gates stacked in the order of the gate oxide film 12, the polysilicon 13, the tungsten electrode 14, and the hard mask nitride film 15 are formed on the semiconductor substrate 11.

이어서, 게이트를 포함한 전면에 질화막(16)을 증착한다. 이때, 질화막(16)은 100∼200Å 두께로 증착하되 단차피복성을 조절(게이트 상부에서 두껍게 증착되고 게이트측벽에서 얇게 증착되도록 함)하여 게이트의 측벽에서는 20∼50Å 두께의 질화막이 증착되도록 한다. 이와 같은 질화막(16)은 후속 층간절연을 위한 산화막 증착시 산소가스에 텅스텐전극(14)이 노출되는 것을 방지하여 이상 산화를 억제하는 역할을 한다.Subsequently, the nitride film 16 is deposited on the entire surface including the gate. At this time, the nitride film 16 is deposited to a thickness of 100 ~ 200Å, but the step coverage is controlled (to be thickly deposited at the top of the gate and to be deposited thinly on the gate side wall) so that the nitride film of 20 to 50Åm thickness on the sidewall of the gate. The nitride film 16 serves to suppress abnormal oxidation by preventing the tungsten electrode 14 from being exposed to oxygen gas during the deposition of an oxide film for subsequent interlayer insulation.

이어서, 이웃한 게이트 사이의 반도체기판(11) 표면 상에 형성된 질화막(16)을 식각한다. Subsequently, the nitride film 16 formed on the surface of the semiconductor substrate 11 between neighboring gates is etched.

이후, 전면에 게이트 사이를 채울때까지 층간절연막 역할을 하는 산화막(17)을 형성한다.Thereafter, an oxide film 17 serving as an interlayer insulating film is formed until the entire surface is filled with gates.

그러나, 종래기술은 질화막 식각시 50Å 두께의 얇은 타겟의 식각이므로 장비의 플라즈마 턴온-턴오프(Turn ON-OFF) 시간이 5∼10초 정도로 매우 짧아 장비의 수명에 영향을 주며, 또한 식각 후에 세정(Cleaning)을 진행하여 식각반응물을 제 거해주는 등 공정이 매우 복잡해진다.However, in the conventional technology, since 50 nm-thick thin target is etched during nitride film etching, the plasma turn-on-off time of the equipment is very short, such as 5 to 10 seconds, affecting the life of the equipment, and also cleaning after etching. The process is very complicated, such as cleaning to remove the etch reactant.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 메탈전극의 이상산화 방지를 위해 질화막을 적용할 때 장비의 수명에 영향을 주지 않으면서도 질화막 식각 및 식각후 세정 등의 공정이 필요하지 않는 반도체소자의 제조방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the above problems of the prior art, the process of etching the nitride film and cleaning after etching without affecting the life of the equipment when applying the nitride film to prevent abnormal oxidation of the metal electrode It is an object of the present invention to provide a method for manufacturing a semiconductor device.

상기 목적을 달성하기 위한 본 발명의 반도체소자의 제조 방법은 반도체기판 상에 적어도 메탈전극을 포함하는 일정 간격으로 배치되는 복수의 패턴을 형성하는 단계; 상기 패턴들을 포함한 전면에 질화막을 형성하는 단계; 상기 패턴 사이 반도체기판 표면의 질화막을 제1산화막으로 변질시키는 단계; 및 상기 제1산화막 상에 상기 패턴 사이를 갭필하는 층간절연을 위한 제2산화막을 증착하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a plurality of patterns arranged at regular intervals including at least a metal electrode on a semiconductor substrate; Forming a nitride film over the entire surface including the patterns; Altering the nitride film on the surface of the semiconductor substrate between the patterns with a first oxide film; And depositing a second oxide film for interlayer insulation that gap-fills the pattern on the first oxide film.

바람직하게, 상기 질화막을 제1산화막으로 변질시키는 단계와 상기 제2산화막을 증착하는 단계는 동일 플라즈마 증착 챔버 내에서 인시튜로 진행하는 것을 특징으로 하며, 상기 플라즈마 증착챔버의 내부는 0.3∼1.5Torr의 압력과 400∼700℃의 온도를 유지하고, 상기 플라즈마 증착 챔버 내부에 사일렌(SiH4) 가스, O2 및 헬 륨(He) 가스를 공급하여 진행하고, 상기 플라즈마증착챔버 내부에 상기 사일렌(SiH4) 가스/O2/헬륨(He) 가스와 함께 수소(H2) 가스를 혼합하여 공급하여, 상기 제2산화막 증착보다 상기 질화막의 제1산화막으로의 변질이 먼저 일어나도록 한다.Preferably, the step of deforming the nitride film to the first oxide film and the step of depositing the second oxide film is carried out in situ in the same plasma deposition chamber, the interior of the plasma deposition chamber is 0.3 to 1.5 Torr Maintaining a pressure of 400 ° C. and a temperature of 400 ° C. to 700 ° C., by supplying a silene (SiH 4 ) gas, O 2, and helium (He) gas into the plasma deposition chamber, and proceeding with the silo inside the plasma deposition chamber. The hydrogen (H 2 ) gas is mixed and supplied together with the ethylene (SiH 4 ) gas / O 2 / helium (He) gas, so that deterioration of the nitride film to the first oxide film occurs before the second oxide film deposition.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체소자의 제조 방법을 도시한 도면이다.3A to 3C illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a에 도시된 바와 같이, 반도체기판(21) 상부에 게이트산화막(22), 폴리실리콘(23), 메탈전극(24) 및 하드마스크질화막(25)의 순서로 적층된 게이트를 형성한다. 여기서, 메탈전극(24)은 W, Ti, Mo 및 Ni 로 이루어진 그룹중에서 선택된 어느 하나를 사용한다.As shown in FIG. 3A, gates stacked in the order of the gate oxide layer 22, the polysilicon 23, the metal electrode 24, and the hard mask nitride layer 25 are formed on the semiconductor substrate 21. Here, the metal electrode 24 uses any one selected from the group consisting of W, Ti, Mo, and Ni.

이어서, 게이트를 포함한 전면에 질화막(26)을 증착한다. 이때, 질화막(26)은 100∼200Å 두께로 증착하되 단차피복성을 조절(게이트 상부에서는 두껍게('D1' 참조) 증착되고, 게이트측벽 및 반도체기판 표면 상에서는 얇게('D2', 'D3'(D2>D3) 참조) 증착되도록 함)하여 게이트의 측벽에서는 20∼50Å 두께(D2)의 질화막(26)이 증착되도록 한다. 한편, 게이트 상부에서는 100∼200Å 두께로 증착한다. 이처럼, 단차피복성을 조절할 수 있는 증착법으로는 PECVD(Plasma Enhanced Chemical Vapor Deposition)가 알려져 있다. Next, the nitride film 26 is deposited on the entire surface including the gate. At this time, the nitride film 26 is deposited to a thickness of 100 to 200Å, but the step coverage is controlled (thickness (see 'D1' at the top of the gate)) and deposited on the gate side wall and the semiconductor substrate thin ('D2', 'D3' ( D2> D3)) to deposit a nitride film 26 having a thickness of 20 to 50 占 퐉 (D2) on the sidewall of the gate. On the other hand, it is deposited to a thickness of 100 to 200 kHz on the gate. As such, PECVD (Plasma Enhanced Chemical Vapor Deposition) is known as a deposition method that can control step coverage.

이와 같은 질화막(26)은 후속 층간절연을 위한 산화막 증착시 산소가스에 메탈전극(24)이 노출되는 것을 방지하여 이상 산화를 억제하는 역할을 하는데, 바람직하게는 실리콘질화막(Si3N4)이다.The nitride film 26 serves to prevent abnormal oxidation by preventing the metal electrode 24 from being exposed to oxygen gas during the deposition of an oxide film for subsequent interlayer insulation. Preferably, the nitride film 26 is a silicon nitride film (Si 3 N 4 ). .

상술한 바와 같이 질화막(26)을 증착한 후에는, 후속 산화막 내부의 불순물(소자에 악영향을 미침)이 배출될 수 있는 통로를 만들어주도록 게이트 사이 반도체기판(21) 표면의 질화막(26)을 제거해주어야 한다. 여기서, 불순물의 배출은 후속 열공정에 의해 이루어진다.After depositing the nitride film 26 as described above, the nitride film 26 on the surface of the semiconductor substrate 21 is removed to form a passage through which impurities (which adversely affect the device) inside the oxide film can be discharged. You should. Here, the discharge of impurities takes place by a subsequent thermal process.

본 발명은 질화막(26)을 식각하는 것이 아니라, 도 3B와 같이 라디칼산화(Radical oxidation)를 통해 게이트 사이 반도체기판(21) 표면의 질화막(26)을 산화막으로 변질시켜 질화막을 제거한다.Instead of etching the nitride film 26, the nitride film 26 on the surface of the semiconductor substrate 21 between gates is changed to an oxide film to remove the nitride film as shown in FIG. 3B.

도 3b 및 도 3c에 도시된 바와 같이, 전면에 게이트 사이를 갭필할때까지 층간절연막 역할을 하는 D-SiO2(27B)을 형성한다. 이때, D-SiO2(27B) 증착시 초기에 질화막(26)의 일부를 라디칼산화를 통해 RO-SiO2(27A)으로 변질시킨다. 예컨대, 플라즈마 내 라디칼에 의하여 증착 초기에 질화막을 산화시키는 것이며, 이를 위해 저압력하에서 산소(Oxygen)와 수소(Hydrogen)를 이용하여 SiO2(27A)으로 변질시킨다.As shown in Figs. 3B and 3C, a D-SiO 2 27B is formed on the front surface to serve as an interlayer insulating film until a gap is filled between the gates. At this time, during the deposition of D-SiO 2 (27B), a portion of the nitride film 26 is deteriorated to RO-SiO 2 (27A) through radical oxidation. For example, the nitride film is oxidized at the initial stage of deposition by radicals in the plasma. For this purpose, the nitride film is deteriorated to SiO 2 (27A) using oxygen and hydrogen under low pressure.

도 3b는 증착초기의 RO-SiO2가 형성된 상태를 도시한 도면이고, 도 3c는 D-SiO2(27B)이 증착된 상태를 도시한 도면으로서, 질화막(26)의 RO-SiO2(27A)로의 변 질은 D-SiO2(27B) 증착시 인시튜로 이루어진다. 여기서, RO-SiO2(27A)는 라디칼산화(Radical Oxidation; RO)에 의한 SiO2이고, D-SiO2(27B)는 증착반응(Deposition; D)에 의한 SiO2이다.FIG. 3B is a view showing a state in which RO-SiO 2 is formed at the beginning of deposition, and FIG. 3C is a view showing a state in which D-SiO 2 27B is deposited, and the RO-SiO 2 (27A) of the nitride film 26 is formed. The change to) takes place in situ during the deposition of D-SiO 2 (27B). Here, RO-SiO 2 (27A) is a radical oxidation; and SiO 2 by (Radical Oxidation RO), D- SiO 2 (27B) is the deposition reaction; the SiO 2 by (Deposition D).

자세히 살펴보면 다음과 같다. The following is a closer look.

D-SiO2(27B)의 증착은, 0.3∼1.5Torr의 압력과 400∼700℃의 온도를 유지하는 플라즈마 증착 챔버 내부에 사일렌(SiH4) 가스, H2, O2 및 헬륨(He) 가스를 공급한 후, 플라즈마 발생을 위해 전원을 인가하여 이루어진다. 여기서, 사일렌(SiH4) 가스는 40∼80sccm, 헬륨은 400∼500sccm, 산소와 수소는 각각 40∼100sccm으로 공급하고, 플라즈마 발생을 위한 탑측 RF 파워(Top RF power)는 3000∼4000W, 사이드측 파워(Side RF power)는 300∼1000W를 사용한다.The deposition of D-SiO 2 (27B) involves the production of xylene (SiH 4 ) gas, H 2 , O 2 and helium (He) in a plasma deposition chamber maintaining a pressure of 0.3-1.5 Torr and a temperature of 400-700 ° C. After supplying the gas, it is made by applying power for plasma generation. In this case, SiH 4 gas is supplied at 40 to 80 sccm, helium is 400 to 500 sccm, oxygen and hydrogen are supplied at 40 to 100 sccm, respectively. Top RF power for plasma generation is 3000 to 4000 W, side Side RF power is 300 ~ 1000W.

위와 같은 조건에 의해 발생된 플라즈마 내부의 사일렌 가스와 산소라디칼이 반응하여 층간절연을 위한 D-SiO2(27B)이 증착되는데, 본 발명에서는 D-SiO2(27B) 증착이 발생되기 전에 플라즈마 내 산소 라디칼(O radical)과 질화막(26) 내의 '실리콘(Si)'이 먼저 반응하여 'RO-SiO2(27A)'가 먼저 형성된다. 이처럼, 산소라디칼과 질화막(26) 내의 실리콘이 먼저 반응하는 이유는 수소(H2)를 사용하기 때문이며, 수소는 질화막(26)과 환원 반응을 일으키고, 환원반응에 의해 발생된 'Si'이 산소라디칼과 반응하여 질화막(26)이 RO-SiO2(27A)로 변질되는 것이다.Silence gas and oxygen radicals in the plasma generated by the above conditions react to deposit D-SiO 2 (27B) for interlayer insulation. In the present invention, before the D-SiO 2 (27B) deposition occurs, the plasma is deposited. O radicals and 'silicon (Si)' in the nitride layer 26 react first to form 'RO-SiO 2 (27A)' first. As such, the reason why the oxygen radicals and silicon in the nitride film 26 react first is because hydrogen (H 2 ) is used, and hydrogen causes a reduction reaction with the nitride film 26, and 'Si' generated by the reduction reaction is oxygen. The nitride film 26 is changed to RO-SiO 2 (27A) by reacting with radicals.

이와 같은 산화 반응을 '라디칼 산화(Radical oxidation)'라고 한다.This oxidation reaction is called 'radical oxidation'.

그리고, 일정 시간동안(이는 증착 초기)동안 라디칼 산화 반응이 계속 일어나고, 이후에는 사일렌 가스가 산소 라디칼이 반응하여 D-SiO2(27B) 증착이 진행된다. 즉, 질화막(26)이 50Å 정도의 두께로 증착된 경우, 라디칼산화 반응은 50Å 두께를 모두 소모될 때까지 진행되고, 이후에는 라디칼산화반응이 일어날 질화막이 존재하지 않으므로, 사일렌 가스가 산소 라디칼이 반응하여 D-SiO2(27B)이 증착되는 것이다.Then, the radical oxidation reaction continues for a certain time (which is the initial deposition), after which the xylene gas reacts with oxygen radicals to proceed with D-SiO 2 (27B) deposition. That is, in the case where the nitride film 26 is deposited to a thickness of about 50 ms, the radical oxidation reaction proceeds until the 50 ms thickness is exhausted, and since there is no nitride film in which the radical oxidation reaction occurs, the xylene gas is an oxygen radical. In this reaction, D-SiO 2 (27B) is deposited.

한편, 질화막의 두께가 50Å보다 두꺼운 경우에는, 라디칼 산화 반응이 계속 일어나는 것이 아니라, 50Å 두께까지만 라디칼산화 반응이 일어나고, 그보다 두꺼운 두께에서는 라디칼산화반응보다는 D-SiO2(27B) 증착을 위한 사일렌가스와 산소라디칼의 증착 반응이 일어나게 되어, 게이트 사이 반도체기판 상에 질화막이 여전히 잔류하게 된다.On the other hand, when the thickness of the nitride film is thicker than 50 GPa, the radical oxidation reaction does not continue to occur, but the radical oxidation reaction occurs only up to 50 GPa, and at thicker thicknesses, the silica for D-SiO 2 (27B) deposition is used rather than the radical oxidation reaction. The deposition reaction of gas and oxygen radicals occurs, and the nitride film still remains on the semiconductor substrate between the gates.

따라서, 본 발명은 게이트 사이 반도체기판(21) 표면 상에서 질화막(26)이 50Å 이하의 두께가 되도록 두께를 제어하는 것이 요구된다. 즉, 질화막(26)이 50Å 이하로 증착되어 있을 경우에만 RO-SiO2(27A)로 변질된다.Therefore, in the present invention, it is required to control the thickness so that the nitride film 26 is 50 mu m or less on the surface of the semiconductor substrate 21 between gates. In other words, the nitride film 26 is deteriorated to RO-SiO 2 27A only when 50 nm or less is deposited.

위와 같은 일련의 공정에 의해 게이트 사이 반도체기판 표면상의 질화막은 모두 RO-SiO2(27A)로 변질되며, 나머지 질화막(게이트 상부 및 게이트 측벽의 질화막)은 RO-SiO2(27A)와 질화막(26A)이 공존(특히, 질화막 위에 SiO2가 형성됨)하게 된다. Through the above process, the nitride film on the surface of the semiconductor substrate between the gates is changed to RO-SiO 2 (27A), and the remaining nitride film (nitride film on the gate and the sidewall of the gate) is RO-SiO 2 (27A) and nitride film 26A. ) Coexist (particularly, SiO 2 is formed on the nitride film).

이때, 게이트 상부의 RO-SiO2(27A)는 D-SiO2(27B)과 동일한 물질이므로, D-SiO2(27B)과 함께 층간절연막의 역할을 한다.In this case, the gate upper RO-SiO 2 (27A) serves as an interlayer insulating film with the D-SiO 2 because it is the same material as (27B), D-SiO 2 (27B).

전술한 바와 같이, 산화막 증착시에 증착초기에 질화막을 라디칼산화반응을 통해 RO-SiO2(27A)로 변질시키면, 질화막(26)을 별도로 식각할 필요가 없을 뿐만 아니라, 식각후 세정을 진행할 필요도 없다. 즉, 게이트 사이에는 질화막이 존재하는 것이 아니라, RO-SiO2(27A)가 존재하고, 이로써 RO-SiO2(27A)가 반도체기판(21)과 직접 접촉함에 따라 D-SiO2(27B) 및 RO-SiO2(27A) 내부의 불순물이 배출되는 통로가 제공된다.As described above, when the nitride film is changed to RO-SiO 2 (27A) through radical oxidation during the deposition of the oxide film, not only the nitride film 26 needs to be etched separately, but also the cleaning needs to be performed after etching. There is no. That is, there is no nitride film between the gates, but there is RO-SiO 2 (27A), whereby D-SiO 2 (27B) and RO-SiO 2 (27A) are in direct contact with the semiconductor substrate 21. A passage through which impurities inside the RO-SiO 2 27A are discharged is provided.

한편, RO-SiO2(27A) 형성시에 게이트 측벽의 질화막(26)도 일부 라디칼산화반응이 일어날 수 있는데, 이때 질화막(26) 내 실리콘이 침투해 들어오는 산소라디칼과 반응하므로, 메탈전극(24)이 산소라디칼에 의해 이상 산화되지는 않는다. Meanwhile, in the formation of RO-SiO 2 (27A), some radical oxidation may also occur in the nitride film 26 on the sidewall of the gate. At this time, since the silicon in the nitride film 26 reacts with oxygen radicals that enter, the metal electrode 24 ) Is not abnormally oxidized by oxygen radicals.

도 4는 본 발명의 실시예에 따른 산화막 증착시 질화막의 변질로 생성되는 SiO2를 나타낸 사진이다.Figure 4 is a photograph showing SiO 2 generated by the deterioration of the nitride film when the oxide film deposition according to an embodiment of the present invention.

도 4를 참조하면, 게이트 사이 반도체기판 상에는 질화막이 모두 산화되고, 게이트 측벽에서는 질화막이 잔류함을 알 수 있다.Referring to FIG. 4, it can be seen that the nitride film is oxidized on the semiconductor substrate between the gates and the nitride film remains on the gate sidewalls.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여 야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 메탈전극의 이상산화를 방지하면서도 장비의 수명에 영향을 주지 않으면서도 질화막 식각 및 식각후 세정 등의 공정이 필요하지 않으므로, TAT(Turn Around Time)를 감소시킬 수 있는 효과가 있다.The present invention described above does not require a process such as etching the nitride film and cleaning after etching without preventing the abnormal oxidation of the metal electrode without affecting the life of the equipment, there is an effect that can reduce the TAT (Turn Around Time) .

Claims (10)

반도체기판 상에 적어도 메탈전극을 포함하는 일정 간격으로 배치되는 복수의 패턴을 형성하는 단계;Forming a plurality of patterns disposed at regular intervals including at least a metal electrode on the semiconductor substrate; 상기 패턴들을 포함한 전면에 질화막을 형성하는 단계;Forming a nitride film over the entire surface including the patterns; 상기 패턴 사이 반도체기판 표면의 질화막을 제1산화막으로 변질시키는 단계; 및Altering the nitride film on the surface of the semiconductor substrate between the patterns with a first oxide film; And 상기 제1산화막 상에 상기 패턴 사이를 갭필하는 층간절연을 위한 제2산화막을 증착하는 단계Depositing a second oxide film for interlayer insulation to gap-fill the pattern on the first oxide film 를 포함하는 반도체소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 질화막을 제1산화막으로 변질시키는 단계와 상기 제2산화막을 증착하는 단계는 동일 플라즈마 증착 챔버 내에서 인시튜로 진행하는 반도체소자의 제조 방법.Deforming the nitride film to the first oxide film and depositing the second oxide film are performed in-situ in the same plasma deposition chamber. 제2항에 있어서,The method of claim 2, 상기 플라즈마 증착챔버의 내부는 0.3∼1.5Torr의 압력과 400∼700℃의 온도 를 유지하고, 상기 플라즈마 증착 챔버 내부에 사일렌(SiH4) 가스, O2 및 헬륨(He) 가스를 공급하여 진행하는 반도체소자의 제조 방법.The inside of the plasma deposition chamber maintains a pressure of 0.3-1.5 Torr and a temperature of 400-700 ° C., and proceeds by supplying a silene (SiH 4 ) gas, O 2 and helium (He) gas into the plasma deposition chamber. A method for manufacturing a semiconductor device. 제3항에 있어서,The method of claim 3, 상기 플라즈마증착챔버 내부에 상기 사일렌(SiH4) 가스/O2/헬륨(He) 가스와 함께 수소(H2) 가스를 혼합하여 공급하여, 상기 제2산화막 증착보다 상기 질화막의 제1산화막으로의 변질이 먼저 일어나도록 하는 반도체소자의 제조 방법.By supplying a mixture of hydrogen (H 2 ) gas together with the xylene (SiH 4 ) gas / O 2 / helium (He) gas inside the plasma deposition chamber, the first oxide film of the nitride film is deposited rather than the second oxide film deposition. Method of manufacturing a semiconductor device so that the alteration occurs first. 제4항에 있어서,The method of claim 4, wherein 상기 사일렌(SiH4) 가스는 40∼80sccm, 상기 헬륨은 400∼500sccm, 상기 산소와 수소는 각각 40∼100sccm으로 공급하는 반도체소자의 제조 방법.The method of manufacturing a semiconductor device wherein the xylene (SiH 4 ) gas is 40 to 80 sccm, the helium is 400 to 500 sccm, and the oxygen and hydrogen are supplied at 40 to 100 sccm, respectively. 제5항에 있어서,The method of claim 5, 상기 플라즈마처리 챔버 내부에 플라즈마를 발생시키기 위해 탑측 RF 파워를 3000∼4000W로 인가하고, 사이드측 파워를 300∼1000W로 인가하는 반도체소자의 제조 방법.And a top side RF power of 3000 to 4000 W and a side side power of 300 to 1000 W to generate plasma in the plasma processing chamber. 제1항 내지 제6항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 6, 상기 질화막을 형성하는 단계는,Forming the nitride film, 상기 패턴 상부 및 측벽에서는 두껍게 증착되고 상기 패턴 사이의 반도체기판의 표면 상에서는 얇게 증착되도록 단차피복성을 조절하는 반도체소자의 제조 방법.A method of manufacturing a semiconductor device for controlling the step coverage so as to be deposited thickly on the upper and sidewalls of the pattern and thinly deposited on the surface of the semiconductor substrate between the patterns. 제7항에 있어서,The method of claim 7, wherein 상기 질화막은, The nitride film, 상기 패턴 상부에서는 100∼200Å 두께로 증착하고, 상기 패턴 사이의 반도체기판 표면 상에서는 20∼50Å 두께로 증착하는 반도체소자의 제조 방법.And depositing a thickness of 100 to 200 kHz on the upper portion of the pattern, and depositing a thickness of 20 to 50 kHz on the surface of the semiconductor substrate between the patterns. 제8항에 있어서,The method of claim 8, 상기 질화막은, The nitride film, PECVD법을 이용하여 실리콘질화막으로 형성하는 반도체소자의 제조 방법.A method for manufacturing a semiconductor device, which is formed of a silicon nitride film using PECVD. 제1항에 있어서,The method of claim 1, 상기 메탈전극은, The metal electrode, W, Ti, Mo 및 Ni로 이루어진 그룹 중에서 선택된 어느 하나로 형성하는 반도체소자의 제조 방법.A method for manufacturing a semiconductor device, which is formed of any one selected from the group consisting of W, Ti, Mo, and Ni.
KR1020060061435A 2006-06-30 2006-06-30 Method of manufacturing semiconductor device prevented abnormal oxidation of metal electrode KR20080002548A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8822299B2 (en) 2010-03-03 2014-09-02 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US9123774B2 (en) 2013-01-23 2015-09-01 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8822299B2 (en) 2010-03-03 2014-09-02 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US9123774B2 (en) 2013-01-23 2015-09-01 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same

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