KR20020045264A - Method of forming a gate electrode in a semiconductor device - Google Patents
Method of forming a gate electrode in a semiconductor device Download PDFInfo
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- KR20020045264A KR20020045264A KR1020000074648A KR20000074648A KR20020045264A KR 20020045264 A KR20020045264 A KR 20020045264A KR 1020000074648 A KR1020000074648 A KR 1020000074648A KR 20000074648 A KR20000074648 A KR 20000074648A KR 20020045264 A KR20020045264 A KR 20020045264A
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- oxide film
- gate electrode
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- aluminum oxide
- film
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 238000000151 deposition Methods 0.000 claims description 27
- 230000008021 deposition Effects 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 239000012495 reaction gas Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000010926 purge Methods 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 3
- 229910021642 ultra pure water Inorganic materials 0.000 claims description 3
- 239000012498 ultrapure water Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000006227 byproduct Substances 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000002156 mixing Methods 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 230000004913 activation Effects 0.000 claims 1
- 239000000376 reactant Substances 0.000 claims 1
- 238000000231 atomic layer deposition Methods 0.000 abstract 3
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 abstract 2
- 229910000457 iridium oxide Inorganic materials 0.000 abstract 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Abstract
Description
본 발명은 반도체 소자의 게이트 전극 형성 방법에 관한 것으로, 특히 게이트 산화막을 결정화하는 과정에서 유효 산화막 두께가 증가하는 것을 방지할 수 있는 반도체 소자의 게이트 전극 형성 방법에 관한 것이다.The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly to a method of forming a gate electrode of a semiconductor device capable of preventing the increase in the effective oxide film thickness in the process of crystallizing the gate oxide film.
최근 들어, 디자인 룰이 축소됨에 따라 게이트 유효 산화막(Effective thickness)의 두께는 점차 낮아지고 있으며, 기존의 SiO2막으로 누설 전류 특성을 만족하는 3nm 이하의 게이트 산화막을 형성하는 것이 어려워졌다. 이에, 높은 유전율을 갖는 Ta2O5, HfO2, ZrO2등이 그 대안으로 제시되고 있다. 그러나, 이들 물질을 게이트 산화막으로 사용하게 되면 산소 분위기의 증착 조건 및 결정화를 위한 열공정을 실시해야 하는데, 이러한 과정에서 반도체 기판이 산화되면서 저유전율막인 SiO2가 형성되어 유효 산화막 두께를 증가시키게 된다. 뿐만 아니라, 게이트 산화막을 이들 물질의 단일막으로 사용하게 되면, 유효 산화막 두께의 조건이 2 내지 3nm인 경우에는 지나치게 높은 누설 전류로 인하여 소자 특성을 만족하지 못하는 문제점이 있다.In recent years, as the design rule is reduced, the thickness of the gate effective oxide film is gradually lowered, and it is difficult to form a gate oxide film of 3 nm or less that satisfies the leakage current characteristic using the existing SiO 2 film. Accordingly, Ta 2 O 5 , HfO 2 , ZrO 2 , and the like having high dielectric constants have been proposed as alternatives. However, when these materials are used as gate oxide films, thermal processes for deposition conditions and crystallization of an oxygen atmosphere have to be performed. During this process, as the semiconductor substrate is oxidized, a low dielectric constant film SiO 2 is formed to increase the effective oxide film thickness. do. In addition, when the gate oxide film is used as a single film of these materials, there is a problem that the device characteristics are not satisfied due to an excessively high leakage current when the condition of the effective oxide film thickness is 2 to 3 nm.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 단원자 증착법으로 산소 확산을 방지할 수 있는 Al2O3막을 증착한 후 Y2O3막을 증착해 이중막으로 이루어지는 게이트 산화막을 형성함으로써 유효 산화막 두께를 낮추고 누설 전류 특성을 향상시킬 수 있는 반도체 소자의 게이트 전극 형성 방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problem, the present invention is to deposit an Al 2 O 3 film capable of preventing oxygen diffusion by monoatomic deposition and then deposit a Y 2 O 3 film to form a gate oxide film formed of a double layer, thereby forming an effective oxide film thickness. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of lowering and improving leakage current characteristics.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 게이트 전극 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도.1A to 1D are cross-sectional views of devices sequentially shown to explain a method of forming a gate electrode of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1 : 반도체 기판2 : 알루미늄 산화막DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2: Aluminum oxide film
3 : Y2O5막23 : 게이트 산화막3: Y 2 O 5 film 23: gate oxide film
4 : 폴리실리콘층5 : 게이트 전극4: polysilicon layer 5: gate electrode
본 발명에 따른 반도체 소자의 게이트 전극 형성 방법은 반도체 기판 상에 단원자 증착법을 이용해 알루미늄 산화막을 증착하는 단계, 알루미늄 산화막 상에 Y2O3막을 증착하여 이중 구조의 게이트 산화막을 형성하는 단계, Y2O3막 상에 폴리실리콘층을 증착하는 단계 및 게이트 전극 마스크를 식각 마스크로 하는 식각 공정으로 폴리실리콘층, Y2O3막 및 알루미늄 산화막을 패터닝하여 게이트 전극을 형성하는 단계로 이루어진다.In the method of forming a gate electrode of a semiconductor device according to the present invention, the method may include: depositing an aluminum oxide layer on a semiconductor substrate using monoatomic deposition; depositing a Y 2 O 3 layer on the aluminum oxide layer to form a gate oxide layer having a dual structure; Forming a gate electrode by patterning a polysilicon layer, a Y 2 O 3 film, and an aluminum oxide film in a process of depositing a polysilicon layer on a 2 O 3 film and an etching process using the gate electrode mask as an etch mask.
알루미늄 산화막을 증착하기 전에 100 : 1 내지 500 : 1의 범위로 초순수(DI water)와 혼합하여 희석된 HF를 이용해 반도체 기판을 세정한다.Before depositing the aluminum oxide film, the semiconductor substrate is washed with diluted HF by mixing with ultrapure water (DI water) in the range of 100: 1 to 500: 1.
단원자 증착법은 알루미늄 산화막이 목표 두께로 증착될 때까지 반복 실시하며, 반도체 기판을 200 내지 300℃의 온도를 유지한 상태에서 알루미늄 소오스로는 TMA 즉 (CH3)3Al을 사용하고, 퍼지 가스는 N2가스를 사용하며, 산소 반응 가스로는 H2O를 사용하여 실시한다. 알루미늄 산화막의 목표 두께는 1 내지 2nm로 한다.The monoatomic vapor deposition method is repeatedly performed until the aluminum oxide film is deposited to a target thickness, and TMA, or (CH 3 ) 3 Al, is used as the aluminum source while the semiconductor substrate is maintained at a temperature of 200 to 300 ° C., and a purge gas N 2 gas is used, and H 2 O is used as the oxygen reaction gas. The target thickness of the aluminum oxide film is 1 to 2 nm.
Y2O3막은 CVD법 ICBD법 또는 스퍼터링으로 5 내지 10nm의 두께로 형성한다.The Y 2 O 3 film is formed to a thickness of 5 to 10 nm by CVD ICBD method or sputtering.
폴리실리콘층은 상기 반도체 기판을 500 내지 650℃의 온도로 유지한 상태에서 열분해법으로 증착하며, 100 내지 200nm의 두께로 증착한다.The polysilicon layer is deposited by thermal decomposition while maintaining the semiconductor substrate at a temperature of 500 to 650 ° C., and is deposited to a thickness of 100 to 200 nm.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 게이트 전극 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of devices sequentially shown to explain a method of forming a gate electrode of a semiconductor device according to the present invention.
도 1a를 참조하면, HF로 세정 공정을 실시한 반도체 기판(1) 상에 단원자 증착법(Automic Layer Deposition; ALD)으로 1내지 2nm의 알루미늄 산화막(Al2O3;2)을 증착한다.Referring to FIG. 1A, an aluminum oxide film (Al 2 O 3 ; 2) having a thickness of 1 to 2 nm is deposited on a semiconductor substrate 1 subjected to a cleaning process with HF by an automatic layer deposition (ALD).
HF는 100 : 1 내지 500 : 1로 초순수(DI water)와 희석시켜 사용한다.HF is used diluted with ultrapure water (DI water) from 100: 1 to 500: 1.
유전율이 약 8 정도 되는 알루미늄 산화막(2)을 증착하는 ALD법은, 알루미늄 소오스 및 활성화 가스를 반도체 기판(1)이 장착된 증착 장비로 공급하여 흡착시키는 제 1 단계, 퍼지 가스를 이용해 미반응 알루미늄 소오스를 증착 장비에서 제거하는 제 2 단계, 산소 반응 가스를 증착 장비로 공급하여 알루미늄 산화막을 형성하는 제 3 단계 및 미반응 산소 반응 가스 및 반응 부산물을 증착 챔버에서 제거하는 제 4 단계로 이루어진다. ALD법은 제 1 내지 제 4 단계를 알루미늄 산화막(2) 증착 공정의 1 싸이클로 하고, 알루미늄 산화막(2)이 목표 두께로 증착될 때까지 1 싸이클을 수차례 반복 실시한다. 이때, 반도체 기판은 200 내지 300℃의 온도를 유지한 상태에서 알루미늄 소오스로는 TMA 즉 (CH3)3Al을 사용하며, 퍼지 가스로는 N2가스를 사용한다. 또한, 산소 반응 가스로는 H2O를 사용한다.The ALD method of depositing an aluminum oxide film 2 having a dielectric constant of about 8 is a first step of supplying and adsorbing an aluminum source and an activating gas to a deposition apparatus equipped with a semiconductor substrate 1, unreacted aluminum using purge gas. The second step of removing the source from the deposition equipment, the third step of supplying the oxygen reaction gas to the deposition equipment to form an aluminum oxide film and the fourth step of removing the unreacted oxygen reaction gas and reaction by-products from the deposition chamber. In the ALD method, the first to fourth steps are taken as one cycle of the aluminum oxide film 2 deposition step, and one cycle is repeated several times until the aluminum oxide film 2 is deposited to a target thickness. At this time, the semiconductor substrate uses TMA, that is, (CH 3 ) 3 Al as an aluminum source and N 2 gas as a purge gas while maintaining a temperature of 200 to 300 ° C. In addition, H 2 O is used as the oxygen reaction gas.
ALD법을 이용하여 알루미늄 산화막(2)을 증착하게 되면, H2O 분위기에서 펄스 방식으로 증착하므로 반도체 기판(1)이 산화되지 않아 저유전율막인 SiO2이 형성되는 것을 방지한다.When the aluminum oxide film 2 is deposited using the ALD method, the semiconductor substrate 1 is prevented from being oxidized and SiO 2, which is a low dielectric constant film, is prevented from being formed by the pulse deposition in the H 2 O atmosphere.
도 1b를 참조하면, 알루미늄 산화막(2) 상에 CVD법, ICBD(Ionized Cluster Beam Deposition)법 또는 스퍼터링으로 Y2O3막(3)을 5 내지 10nm의 두께로 증착하여 이중 구조의 게이트 산화막(23)을 형성한다.Referring to FIG. 1B, a Y 2 O 3 film 3 is deposited to a thickness of 5 to 10 nm by CVD, ionized cluster beam deposition (ICBD), or sputtering on an aluminum oxide film 2. 23).
Y2O3막(3)의 두께는 소자에서 요구하는 유효 산화막 두께에 따라 조절할 수 있다. Y2O3막(3)을 증착하는 과정에서, 알루미늄 산화막(2)이 산소 확산 방지막의 역할을 해주며, 증착된 Y2O3막(3)은 고유전율막으로써 게이트 산화막의 유효 산화막 두께를 줄이는 역할을 한다.The thickness of the Y 2 O 3 film 3 can be adjusted according to the effective oxide film thickness required by the device. In the process of depositing the Y 2 O 3 film 3, the aluminum oxide film 2 serves as an oxygen diffusion barrier, and the deposited Y 2 O 3 film 3 is a high dielectric constant film and has an effective oxide film thickness of the gate oxide film. It serves to reduce.
도 1c를 참조하면, 게이트 산화막(23) 상에 폴리실리콘층(4) 100 내지 200nm의 두께로 증착한다.Referring to FIG. 1C, a thickness of 100 to 200 nm of the polysilicon layer 4 is deposited on the gate oxide layer 23.
이때, 폴리실리콘층(4)은 반도체 기판(1)을 500 내지 650℃의 온도로 유지하면서, 열분해법으로 증착한다.At this time, the polysilicon layer 4 is deposited by thermal decomposition while maintaining the semiconductor substrate 1 at a temperature of 500 to 650 ° C.
도 1d를 참조하면, 게이트 전극 마스크를 식각 마스크로 하는 식각 공정으로 폴리실리콘층(4), Y2O3막(3) 및 알루미늄 산화막(2)을 패터닝하여 게이트 전극(5)을 형성한다.Referring to FIG. 1D, the polysilicon layer 4, the Y 2 O 3 film 3, and the aluminum oxide film 2 are patterned in an etching process using the gate electrode mask as an etching mask to form the gate electrode 5.
이후, 도시하고 있지는 않지만 일반적으로 공지된 기술을 이용하여 게이트 전극 스페이서, LDD 구조의 소오스/드레인을 형성하여 트랜지스터를 제조한다.Subsequently, although not shown, a transistor is manufactured by forming a source / drain of a gate electrode spacer and an LDD structure using a generally known technique.
상기의 공정에서 형성한 이중 구조의 게이트 산화막은 커패시터의 유전체막으로 사용할 수도 있다.The gate oxide film of the dual structure formed in the above process can also be used as a dielectric film of a capacitor.
상술한 바와 같이, 본 발명은 게이트 산화막을 알루미늄 산화막 및 Y2O3막으로 이루어진 이중 구조로 형성함으로써 소자의 유효 산화막 두께를 낮추고 누설 전류를 줄여줌으로써 반도체 소자의 전기적 특성을 향상시키는 효과가 있다.As described above, the present invention has the effect of improving the electrical characteristics of the semiconductor device by forming a gate oxide film having a double structure consisting of an aluminum oxide film and a Y 2 O 3 film to reduce the effective oxide film thickness of the device and reduce the leakage current.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100447979B1 (en) * | 2002-12-09 | 2004-09-10 | 주식회사 하이닉스반도체 | Method for forming gate of semiconductor device |
| KR101381324B1 (en) * | 2011-10-28 | 2014-04-04 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Method for fabricating oxide/semiconductor interface |
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| KR101407289B1 (en) * | 2007-04-30 | 2014-06-13 | 엘지디스플레이 주식회사 | Thin film transistor substrate and method of manufacturing the same |
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| JPH01270591A (en) * | 1988-04-20 | 1989-10-27 | Seiko Epson Corp | Process for forming dielectric film |
| JP2816192B2 (en) * | 1989-08-16 | 1998-10-27 | 株式会社日立製作所 | Method for manufacturing semiconductor device |
| JP2940051B2 (en) * | 1990-02-09 | 1999-08-25 | 富士通株式会社 | Method of forming insulating thin film |
| KR930012120B1 (en) * | 1991-07-03 | 1993-12-24 | 삼성전자 주식회사 | Semicondcutor device and fabricating method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100447979B1 (en) * | 2002-12-09 | 2004-09-10 | 주식회사 하이닉스반도체 | Method for forming gate of semiconductor device |
| KR101381324B1 (en) * | 2011-10-28 | 2014-04-04 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Method for fabricating oxide/semiconductor interface |
| US9087785B2 (en) | 2011-10-28 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating oxides/semiconductor interfaces |
| US10615028B2 (en) | 2011-10-28 | 2020-04-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating oxides/semiconductor interfaces |
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