KR20080061524A - Method for forming a insulating film in a semiconductor device - Google Patents

Method for forming a insulating film in a semiconductor device Download PDF

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Publication number
KR20080061524A
KR20080061524A KR1020060136363A KR20060136363A KR20080061524A KR 20080061524 A KR20080061524 A KR 20080061524A KR 1020060136363 A KR1020060136363 A KR 1020060136363A KR 20060136363 A KR20060136363 A KR 20060136363A KR 20080061524 A KR20080061524 A KR 20080061524A
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KR
South Korea
Prior art keywords
film
dielectric film
semiconductor device
crystal line
oxide film
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KR1020060136363A
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Korean (ko)
Inventor
홍권
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020060136363A priority Critical patent/KR20080061524A/en
Publication of KR20080061524A publication Critical patent/KR20080061524A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a dielectric film of a semiconductor device. The dielectric material of a semiconductor device having a high dielectric constant and low gate leakage current characteristics is formed by forming a sandwich structure in which crystal lines, oxide films, and crystal lines, which are high dielectric materials, are sequentially stacked. Provided are a film forming method.

Description

Method for forming a insulating film in a semiconductor device

1 to 6 are cross-sectional views of devices for describing a method of forming a dielectric film of a semiconductor device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 101 first oxide film

102: first crystal line film 103: second oxide film

104: high dielectric film 105: polysilicon film

The present invention relates to a method for forming a dielectric film of a semiconductor device, and more particularly to a method for forming a dielectric film having a high dielectric constant.

Recently, semiconductor devices are designed to provide high integration and high performance, and in particular, dielectric films used for MOS transistors and capacitors are formed as thin as possible. This is because the driving current of the MOS transistor increases as the thickness of the gate dielectric film of the MOS transistor decreases, and the storage capacitance increases as the thickness of the dielectric film of the capacitor decreases. Therefore, in order to improve the performance of the device, it is increasingly important to form a dielectric film that is not only extremely thin but also reliable and has few defects.

Conventionally, a silicon oxide film has been used as the gate dielectric film. This is because the process is simple and very stable since the silicon substrate is formed by oxidizing. However, since the silicon oxide film has a low dielectric constant of about 3.9, there is a limit in reducing the thickness of the gate dielectric film made of the silicon oxide film. In addition, in the case where the gate dielectric layer is formed very thin using the silicon oxide layer, a tunnel current flows through the gate dielectric layer, thereby increasing leakage current. Accordingly, a method of forming the gate dielectric layer using a high dielectric material has been developed. When the gate dielectric layer is formed of a high dielectric material, the same capacitance as that of the silicon oxide may be obtained while being formed thicker than that of the silicon oxide. Accordingly, metal oxides having a higher dielectric constant than silicon oxide have been proposed as alternative dielectric materials for gate dielectric films or capacitor dielectric films.

In addition, the silicon substrate surface easily reacts with the high dielectric metal oxide or is easily oxidized during the deposition or subsequent thermal process of the high dielectric metal oxide. Thus, a boundary film such as a silicon oxide film is formed between the silicon substrate and the metal oxide film. As a result, the equivalent oxide film (EOT) thickness is increased to deteriorate the performance of the device.

In addition, when polysilicon is used as the gate electrode, dopants in the polysilicon are diffused, thereby degrading the characteristics of the transistor.

SUMMARY OF THE INVENTION The present invention provides a method for forming a dielectric film of a semiconductor device having a high dielectric constant and low gate leakage current by forming a sandwich structure in which crystal lines, oxide films, and crystal lines, which are high dielectric constants, are sequentially stacked. .

A dielectric film forming method of a semiconductor device according to an embodiment of the present invention comprises the steps of sequentially depositing a first oxide film, a first crystal line film, a second oxide film, a high dielectric film, and a polysilicon film on a semiconductor substrate, and heat treatment Performing a process to form the high dielectric film as a second crystal line film, and an etching process using a hard mask pattern, and the polysilicon film, the second crystal line film, the second oxide film, and the first crystal line film. And patterning the first oxide film to form a gate dielectric film.

The first oxide film is formed of a SiO 2 film having a thickness of 1 to 10 GPa, and the first oxide film is formed at a temperature of 650 to 900 ° C.

The first crystal line film is formed to crystallize when deposited by PVD, ALD or MOCVD method, the first crystal line film is formed by crystallizing one of HfO2, ZrO, La2O3, Ta2O5, TiO2 dielectric, the first crystal line The film is formed to a thickness of 40 to 60 kPa at a temperature of 300 to 350 ℃ source of the amide (amide) precursor and O 2 gas.

The second oxide film is formed of an Al 2 O 3 or SiO 2 film by using an ALD method, and the second oxide film is formed to a thickness of 1 to 10 Å.

The high-k dielectric film is formed using an amorphous material, the high-k dielectric film is formed of one of HfO2, ZrO, La2O3, Ta2O5, TiO2 dielectric, the high-k dielectric film is formed to a thickness of 20 to 40Å by ALD method.

The heat treatment process is carried out at a high temperature of 900 to 1300 ℃ by the RTP method.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1 to 6 are cross-sectional views of devices for describing a method of forming a dielectric film of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, first, a cleaning process is performed to remove impurities from the surface of the semiconductor substrate 100. The washing process is preferably to use HF solution diluted with water to 100: 1. The first oxide film 101 is formed on the semiconductor substrate 100. The first oxide film 101 is preferably formed using RTO or wet oxidation. In addition, the first oxide film 101 is preferably formed of an SiO 2 film. The SiO 2 film is preferably formed to a thickness of 1 to 10 GPa. The first oxide film 101 is preferably formed at a temperature of 650 to 900 ℃.

Referring to FIG. 2, the first crystal line layer 102 is formed on the entire structure including the first oxide layer 101. The first crystal line film 102 is formed to a thickness that is crystallized upon deposition by PVD, ALD or MOCVD. The first crystal line film 102 is preferably formed of one of HfO 2, ZrO, La 2 O 3, Ta 2 O 5, and TiO 2 dielectric. In addition, the first crystal line film 102 is preferably formed to a thickness of 40 ~ 60Å. The first crystal line layer 102 is preferably formed at an temperature of 300 to 350 ° C. using an amide precursor and an O 2 gas as a source.

Referring to FIG. 3, a second oxide film 103 is formed on the entire structure including the first crystal line film 102. The second oxide film 103 is preferably formed of an Al 2 O 3 or SiO 2 film using an ALD method. The Al 2 O 3 or SiO 2 film is preferably formed to a thickness of 1 to 10 kPa. The second oxide film 103 is used as a film to block a current path by causing a grain boundary mismatch between the second crystal line and the first crystal line 102 that are subsequently formed.

Referring to FIG. 4, a high dielectric film 104 is formed on the entire structure including the second oxide film 103. The high dielectric film 104 is preferably formed using an amorphous material. The high dielectric film 104 is preferably formed of one of HfO2, ZrO, La2O3, Ta2O5, and TiO2 dielectrics. The high dielectric film 104 is preferably formed to a thickness of 20 to 40Å by ALD method.

Referring to FIG. 5, a polysilicon film 105 is formed on the entire structure including the high dielectric film 104.

Referring to FIG. 6, a heat treatment process is performed to form FIG. 4 to crystallize the high dielectric film 104 to form a second crystal line 104 ′. The heat treatment step is preferably carried out at a high temperature of 900 to 1300 ℃ by the RTP method.

 Subsequently, although not shown in the drawings, an etching process using a hard mask pattern may be performed to form the polysilicon film 105, the second crystal line 104 ′, the second oxide film 103, the first crystal line 102, and the like. The first oxide film 101 is etched to form a gate dielectric.

 As described above, the dielectric film is formed in the sandwich structure of the first crystal line 102, the second oxide film 103, and the second crystal line 104 ', which is a high dielectric film, so that a low EOT and a low The gate leakage current characteristics can be obtained to form a highly integrated, high performance gate dielectric film.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, by forming a sandwich structure in which crystal lines, oxide films, and crystal lines, which are high dielectric materials, are sequentially stacked, a dielectric film of a semiconductor device having a high dielectric constant and low gate leakage current characteristics may be formed. .

Claims (12)

Sequentially stacking a first oxide film, a first crystal line film, a second oxide film, a high dielectric film, and a polysilicon film on a semiconductor substrate; Performing a heat treatment process to form the high dielectric film as a second crystal line film; And Patterning the polysilicon film, the second crystal line film, the second oxide film, the first crystal line film, and the first oxide film by an etching process using a hard mask pattern to form a gate dielectric film Method for forming a dielectric film of a device. The method of claim 1, And the first oxide film is formed of a SiO 2 film having a thickness of 1 to 10 GPa. The method of claim 1, The first oxide film is a dielectric film forming method of a semiconductor device formed at a temperature of 650 ~ 900 ℃. The method of claim 1, The first crystal line film is a method of forming a dielectric film of a semiconductor device to be formed to crystallize upon deposition by PVD, ALD or MOCVD method. The method of claim 1, And the first crystal line layer is formed by crystallizing one of HfO 2, ZrO, La 2 O 3, Ta 2 O 5, and TiO 2 dielectrics. The method of claim 1, The first crystal line film is a dielectric film formation method of a semiconductor device to form a thickness of 40 to 60 Å at a temperature of 300 to 350 ℃ source of amide (amide) precursor and O2 gas as a source. The method of claim 1, And the second oxide film is formed of an Al 2 O 3 or SiO 2 film using an ALD method. The method of claim 1, And the second oxide film is formed to a thickness of 1 to 10 로. The method of claim 1, The high dielectric film is a dielectric film forming method of a semiconductor device formed using an amorphous material. The method of claim 1, And the high dielectric film is formed of one of HfO2, ZrO, La2O3, Ta2O5, and TiO2 dielectrics. The method of claim 1, The high dielectric film is a dielectric film forming method of a semiconductor device to form a thickness of 20 to 40 내지 by using the ALD method. The method of claim 1, The heat treatment step is a dielectric film forming method of a semiconductor device that proceeds at a high temperature of 900 to 1300 ℃ by RTP method.
KR1020060136363A 2006-12-28 2006-12-28 Method for forming a insulating film in a semiconductor device KR20080061524A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101125567B1 (en) * 2009-12-24 2012-03-22 삼성모바일디스플레이주식회사 Polymer substrate and method of manufacturing the same and display device including the polymer substrate and method of manufacturing the display device
US11522082B2 (en) 2019-09-18 2022-12-06 Samsung Electronics Co., Ltd. Electronic device and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101125567B1 (en) * 2009-12-24 2012-03-22 삼성모바일디스플레이주식회사 Polymer substrate and method of manufacturing the same and display device including the polymer substrate and method of manufacturing the display device
US11522082B2 (en) 2019-09-18 2022-12-06 Samsung Electronics Co., Ltd. Electronic device and method of manufacturing the same
US11824118B2 (en) 2019-09-18 2023-11-21 Samsung Electronics Co., Ltd. Electronic device and method of manufacturing the same

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