KR100680971B1 - Method for forming recessed gate of semiconductor device - Google Patents

Method for forming recessed gate of semiconductor device Download PDF

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KR100680971B1
KR100680971B1 KR1020050092043A KR20050092043A KR100680971B1 KR 100680971 B1 KR100680971 B1 KR 100680971B1 KR 1020050092043 A KR1020050092043 A KR 1020050092043A KR 20050092043 A KR20050092043 A KR 20050092043A KR 100680971 B1 KR100680971 B1 KR 100680971B1
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tungsten silicide
layer
film
gate
forming
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김준기
김수현
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

A method for forming a recessed gate of a semiconductor device is provided to deposit a tungsten silicide layer on a polysilicon layer without seams regardless of the generation of horns on the polysilicon layer using two-step tungsten silicide forming processes. An isolation layer(22) for defining an active region is formed on a semiconductor substrate(21). A groove(25) is formed on the resultant structure by etching a gate forming region of the active region. A gate insulating layer(26) is formed on the active region. A polysilicon layer(27), a tungsten silicide layer(28a,28b) and a hard mask layer are sequentially formed on the resultant structure to fill the groove. Then, an etching process is performed on the resultant structure. The tungsten silicide layer is formed by using two-step tungsten silicide forming processes under different gas conditions.

Description

반도체 소자의 리세스 게이트 형성방법{Method for forming recessed gate of semiconductor device}Method for forming recessed gate of semiconductor device

도 1a 내지 도 1d는 종래의 반도체 소자의 리세스 게이트 형성방법을 설명하기 위한 공정별 단면도.1A to 1D are cross-sectional views illustrating processes for forming a recess gate of a conventional semiconductor device.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 리세스 게이트 형성방법을 설명하기 위한 공정별 단면도.2A to 2D are cross-sectional views illustrating processes of forming a recess gate in a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21: 반도체 기판 22: 소자분리막21: semiconductor substrate 22: device isolation film

23: 희생산화막 24: 하드마스크 폴리실리콘막23: sacrificial oxide film 24: hard mask polysilicon film

25: 홈 26: 게이트절연막25: groove 26: gate insulating film

27: 폴리실리콘막 28a: 1차로 증착된 텅스텐실리사이드막27: polysilicon film 28a: firstly deposited tungsten silicide film

28b: 2차로 증착된 텅스텐실리사이드막28b: secondary deposited tungsten silicide film

29: 하드마스크막 30: 리세스 게이트29: hard mask layer 30: recess gate

100: 1차 및 2차로 증착된 텅스텐실리사이드막100: primary and secondary deposited tungsten silicide film

본 발명은 반도체 소자의 리세스 게이트(recessed gate) 형성방법에 관한 것으로, 보다 상세하게는 텅스텐실리사이드막 형성시 발생하는 균열(seam)을 방지할 수 있는 반도체 소자의 리세스 게이트 형성방법에 관한 것이다.The present invention relates to a method of forming a recessed gate of a semiconductor device, and more particularly, to a method of forming a recessed gate of a semiconductor device capable of preventing a crack generated when a tungsten silicide film is formed. .

반도체 소자의 집적도가 증가함에 따라 트랜지스터의 채널길이(channel length)가 매우 짧아지고 있다. 트랜지스터의 채널길이가 짧아짐에 따라, 트랜지스터의 문턱전압(threshold voltage)이 급격히 낮아지는 이른바 단채널효과(short channel effect)가 심해지는 문제점이 발생하게 되는데, 그 결과로, 트랜지스터의 채널을 통한 누설전류(leakage current)가 증가한다. 이로 인해, DRAM의 capacitor에 저장된 전하가 빠져나가게 되어 데이타가 소실되는 문제점이 발생한다.As the degree of integration of semiconductor devices increases, the channel length of the transistor becomes very short. As the channel length of the transistor is shortened, a problem arises in that a so-called short channel effect, in which the threshold voltage of the transistor is drastically lowered, results in a leakage current through the channel of the transistor. (leakage current) increases. As a result, the charge stored in the capacitor of the DRAM is released, causing a problem of data loss.

이에, 트랜지스터의 단채널효과를 방지하기 위해서 실리콘기판에 홈을 형성한 후, 상기 홈 상에 게이트를 형성시키는 리세스 게이트(recessd gate)에 대한 연구가 활발하게 진행되고 있다. 이러한, 리세스 게이트에 따르면, 홈 상에 게이트를 형성하는 것에 의해 채널길이를 증가시킬 수 있으므로 평면형(plannar) 게이트 구조와 비교해서 단채널효과를 줄일 수 있다.Accordingly, research has been actively conducted on recessed gates in which a groove is formed on a silicon substrate and then a gate is formed on the groove to prevent short channel effects of the transistor. According to the recess gate, the channel length can be increased by forming the gate on the groove, so that the short channel effect can be reduced as compared with the planar gate structure.

한편, 소자의 집적도가 증가함에 따라 게이트 물질로써 저항이 매우 낮은 물질을 요구하고 있다. 이에, 게이트의 전극 저항 감소를 위해 텅스텐 게이트 물질로서 사용하게 되었다.On the other hand, as the degree of integration of devices increases, a material having a very low resistance is required as a gate material. Thus, it has been used as a tungsten gate material to reduce the electrode resistance of the gate.

여기서, 현재 수행되고 있는 반도체 소자의 리세스 게이트 형성방법을 도 1a 내지 도 1c를 참조하여 간략하게 설명하도록 한다.Here, a method of forming a recess gate of a semiconductor device currently being performed will be briefly described with reference to FIGS. 1A to 1C.

도 1a를 참조하면, 반도체기판(1) 내에 액티브영역을 한정하는 소자분리막 (2)을 형성한다. 그런다음, 상기 기판(1) 상에 리세스 게이트를 형성하기 위한 식각장벽막으로서 희생산화막(3)과 하드마스크 폴리실리콘막(4)을 차례로 형성한 후, 하드마스크 폴리실리콘막(4) 및 희생산화막(3)을 차례로 식각하여 기판(1)의 게이트 형성 영역을 노출시킨다. Referring to FIG. 1A, an isolation layer 2 is formed in the semiconductor substrate 1 to define an active region. Then, the sacrificial oxide film 3 and the hard mask polysilicon film 4 are sequentially formed as an etch barrier film for forming the recess gate on the substrate 1, and then the hard mask polysilicon film 4 and The sacrificial oxide film 3 is sequentially etched to expose the gate formation region of the substrate 1.

도 1b 참조하면, 상기 식각된 하드마스크 폴리실리콘막(4)을 식각마스크로 이용하여 노출된 기판 부분을 식각하여 홈(5)을 형성한다. 그런다음, 상기 하드마스크 폴리실리콘막 및 희생산화막을 차례로 제거한 후, 상기 홈(5)을 포함한 기판 액티브영역에 게이트절연막(6)을 형성한다. 그런다음, 상기 게이트절연막(6) 상에 폴리실리콘막(7), 텅스텐실리사이드막(8) 및 하드마스크막(9)을 차례로 증착한다. 일반적으로, 상기 텅스텐실리사이드막(8)은 환원가스와 소스가스의 유량비를 고 유량비로 구성하여 형성한다. 여기서, 상기 환원가스와 소스가스의 유량비는 소스가스의 유량을 환원가스의 유량으로 나눈(환원가스÷소스가스= 유량비) 값을 뜻한다.Referring to FIG. 1B, the exposed substrate portion is etched using the etched hard mask polysilicon layer 4 as an etch mask to form a groove 5. After that, the hard mask polysilicon film and the sacrificial oxide film are sequentially removed, and then a gate insulating film 6 is formed in the substrate active region including the grooves 5. Then, a polysilicon film 7, a tungsten silicide film 8, and a hard mask film 9 are sequentially deposited on the gate insulating film 6. In general, the tungsten silicide film 8 is formed by forming a flow rate ratio of reducing gas and source gas at a high flow rate ratio. Here, the flow rate ratio of the reducing gas and the source gas means a value obtained by dividing the flow rate of the source gas by the flow rate of the reducing gas (reduction gas ÷ source gas = flow rate ratio).

그리고, 상기 폴리실리콘막(7) 형성시 상기 홈(5)으로 인해 폴리실리콘막 표면에 첨점(cusp)이 발생하게 되는데, 이러한, 첨점으로 인해 텅스텐실리사이드막 형성시 상기 텅스텐실리사이드막(8)에 균열(seam)이 발생한다.In addition, when the polysilicon layer 7 is formed, a cusp may be generated on the surface of the polysilicon layer due to the grooves 5. As a result, the tungsten silicide layer 8 may be formed when the tungsten silicide layer is formed. A crack occurs.

도 1c를 참조하면, 공지의 포토 및 식각공정을 통해 상기 하드마스크막(9), 텅스텐실리사이드막(8), 폴리실리콘막(7) 및 게이트절연막(6)을 식각하여 리세스 게이트(10)를 형성한다.Referring to FIG. 1C, the hard mask layer 9, the tungsten silicide layer 8, the polysilicon layer 7, and the gate insulating layer 6 may be etched through a well-known photo and etching process. To form.

그러나, 전술한 바와 같이, 리세스 게이트 형성방법은 다음과 같은 문제점이 있다.However, as described above, the recess gate forming method has the following problems.

첨점이 발생된 폴리실리콘막(7) 상에 텅스텐실리사이드막(8) 형성시 첨점의 안쪽에는 텅스텐실리사이드(WSix)의 증착가스의 양이 부족하여 WSix의 핵이 형성되기가 어렵다. 이로 인해, 상기 텅스텐실리사이드막(8)은 폴리실리콘막(7)의 양쪽에서 부터 증착하게 되어 결과적으로 텅스텐실리이드막(8)에 균열이 발생하게 된다. When the tungsten silicide film 8 is formed on the polysilicon film 7, in which the dew points are generated, the amount of the deposition gas of the tungsten silicide (WSix) is insufficient in the inside of the dew point, making it difficult to form the nucleus of the WSix. As a result, the tungsten silicide film 8 is deposited from both sides of the polysilicon film 7, resulting in cracking of the tungsten silicide film 8.

도 1d를 참조하면, 게이트 형성시 게이트와 채널간에 오정렬(mis-align)이 발생했을 경우, 게이트 식각 공정 후, 식각 데미지를 제거하기 위해 산화분위기에서 열처리를 수행하는 공정인, 게이트 재산화(gate re-oxidation) 공정시, 텅스텐실리사이드막(8)에 발생된 균열을 기준으로 WSix의 부피가 적은 쪽(①)의 텅스텐실리사이드막(8) 측벽에 비정상적으로 산화막(A)이 형성하는 이상산화 현상이 발생한다. 결국, 이러한 원인으로 소자의 특성을 악화시킨다.Referring to FIG. 1D, when mis-alignment occurs between a gate and a channel when forming a gate, a gate reoxidation process is performed after heat treatment in an oxidizing atmosphere to remove etch damage after the gate etching process. An abnormal oxidation phenomenon in which an oxide film (A) is abnormally formed on the side wall of the tungsten silicide film 8 of the lower volume of WSix (①) based on the crack generated in the tungsten silicide film 8 during the re-oxidation process. This happens. As a result, these characteristics deteriorate the characteristics of the device.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로써, 텅스텐실리사이드막에 발생하는 균열을 방지할 수 있는 반도체 소자의 리세스 게이트 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of forming a recess gate of a semiconductor device capable of preventing a crack occurring in a tungsten silicide film, which is devised to solve the above conventional problems.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 액티브영역을 한정하는 소자분리막이 구비된 반도체기판을 마련하는 단계; 상기 기판 액티브영역의 게이트 형성 영역을 식각하여 홈을 형성하는 단계; 상기 홈을 포함한 기판 액티브영역 상에 게이트절연막을 형성하는 단계; 상기 게이트절연막을 포함한 기판 상에 홈을 매립하도록 폴리실리콘막, 텅스텐실리사이드막 및 하드마스크막을 차례로 형성하는 단계; 및 상기 하드마스크막, 텅스텐실리사이드막, 폴리실리콘막 및 게이트절연막을 식각하는 단계;를 포함하는 반도체 소자의 리세스 게이트 형성방법에 있어서,In order to achieve the above object, the present invention comprises the steps of providing a semiconductor substrate having a device isolation film defining an active region; Etching a gate forming region of the substrate active region to form a groove; Forming a gate insulating film on the substrate active region including the groove; Sequentially forming a polysilicon film, a tungsten silicide film, and a hard mask film to fill a groove on the substrate including the gate insulating film; And etching the hard mask layer, the tungsten silicide layer, the polysilicon layer, and the gate insulating layer.

상기 텅스텐실리사이드막은 환원가스와 소스가스의 유량비가 2∼180인 저(low) 유량비로 1차 증착하고, 환원가스와 소스가스의 유량비가 150∼250인 고(high) 유량비로 2차 증착하여 형성하는 것을 특징으로 한다.The tungsten silicide film is formed by first deposition at a low flow rate ratio of a flow rate of reducing gas and a source gas of 2 to 180, and second deposition at a high flow rate ratio of 150 to 250 flow rate ratio of a reducing gas and a source gas. Characterized in that.

여기서, 상기 텅스텐실리사이드막의 1차 및 2차 증착은 소스가스로 1∼30sccm의 WF6를 사용하며, 환원가스로 50∼500sccm의 SiH4 또는 SiH2Cl2로 사용하는 것을 특징으로 하며, 상기 텅스텐실리사이드막의 1차 및 2차 증착은 300∼600℃의 온도 및 0.1∼5Torr인 압력인 조건에서 수행하는 것을 특징으로 한다. Here, the first and second deposition of the tungsten silicide film is WF6 of 1 to 30 sccm as the source gas, 50 to 500 sccm of SiH4 or SiH2Cl2 as the reducing gas, characterized in that the first and second of the tungsten silicide film Secondary deposition is characterized in that it is carried out under the conditions of the temperature of 300 to 600 ℃ and the pressure of 0.1 to 5 Torr.

또한, 상기 텅스텐실리사이드막의 1차 및 2차 증착은 전체 두께합이 800∼1500Å이 되도록 형성하는 것을 특징으로 한다.In addition, the first and second deposition of the tungsten silicide film is characterized in that the total thickness is formed to 800 ~ 15001.

상기 텅스텐실리사이드막의 1차 증착은 전체 텅스텐실리사이드막 형성 두께의 1/20∼1/2 두께로 수행하는 것을 특징으로 한다.The first deposition of the tungsten silicide film is characterized in that the thickness of 1/20 to 1/2 of the total thickness of the tungsten silicide film formed.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 리세스 게이트 형성방법을 설명하기 위한 공정별 단면도이다.2A to 2D are cross-sectional views illustrating processes of forming a recess gate in a semiconductor device according to the present invention.

도 2a를 참조하면, 반도체 기판(21) 내에 액티브 영역을 한정하는 소자분리막(22)을 STI(Shallow Trench Isolation) 공정을 통해 형성한다. 그런다음, 상기 기판(21) 상에 희생산화막(23)과 하드마스크 폴리실리콘막(24)을 차례로 형성한 후, 하드마스크 폴리실리콘막(24)과 희생산화막(23)을 식각하여 기판(21)의 게이트 형성 영역을 노출시킨다. 다음으로, 상기 식각된 하드마스크 폴리실리콘막(24)을 식각마스크로 이용하여 노출된 기판 부분을 식각하여 홈(25)을 형성한다. Referring to FIG. 2A, an isolation layer 22 defining an active region in the semiconductor substrate 21 is formed through a shallow trench isolation (STI) process. Then, the sacrificial oxide film 23 and the hard mask polysilicon film 24 are sequentially formed on the substrate 21, and then the hard mask polysilicon film 24 and the sacrificial oxide film 23 are etched to form the substrate 21. ) To expose the gate formation region. Next, the exposed portion of the substrate is etched using the etched hard mask polysilicon layer 24 as an etch mask to form the groove 25.

도 2b 참조하면, 상기 하드마스크 폴리실리콘막 및 희생산화막을 차례로 제거한 후, 상기 홈(25)을 포함한 기판 액티브영역에 게이트절연막(26)을 형성한다. 그런다음, 상기 게이트절연막(26) 상에 홈이 매립하도록 폴리실리콘막(27)을 증착한다. 여기서, 상기 폴리실리콘막(27) 형성시 상기 홈(25)으로 인해 폴리실리콘막(27) 표면에 첨점(cusp)이 발생한다.Referring to FIG. 2B, after the hard mask polysilicon layer and the sacrificial oxide layer are sequentially removed, a gate insulating layer 26 is formed in the substrate active region including the groove 25. Then, a polysilicon film 27 is deposited on the gate insulating film 26 to fill the groove. Herein, when the polysilicon layer 27 is formed, a cusp may be generated on the surface of the polysilicon layer 27 due to the groove 25.

다음으로, 상기 폴리실리콘막(27) 상에 환원가스와 소스가스의 유량비가 2∼180인 저 유량비로 텅스텐실리사이드막(28a)을 1차로 증착한다. 여기서, 상기 텅스텐실리사이드막(28a) 1차 증착은 소스가스로 1∼30sccm의 WF6를 사용하며, 환원가스로 50∼500sccm의 SiH4 또는 SiH2Cl2을 사용하여 수행하며, 300∼600℃의 온도 및 100∼500mTorr인 압력에서 수행한다. 또한, 상기 텅스텐실리실리사이드막(28a) 1차 증착은 전체 텅스텐실리사이드막(100) 형성 두께의 1/20∼1/2 두께로 수행한다.Next, a tungsten silicide film 28a is first deposited on the polysilicon film 27 at a low flow rate ratio of a flow rate of reducing gas and source gas of 2 to 180. Here, the first deposition of the tungsten silicide layer 28a is performed using 1 to 30 sccm of WF6 as the source gas, 50 to 500 sccm of SiH4 or SiH2Cl2 as the reducing gas, and a temperature of 300 to 600 ° C. and 100 to It is performed at a pressure of 500 mTorr. In addition, the first deposition of the tungsten silicide film 28a is performed at a thickness of 1/20 to 1/2 of the thickness of the entire tungsten silicide film 100.

도 2c를 참조하면, 상기 1차로 증착된 텅스텐실리사이드막(28a) 상에 환원가스와 소스가스의 유량비가 150∼250인 고 유량비로 텅스텐실리사이드막(28b)을 2차로 증착한다. 여기서, 상기 텅스텐실리사이드막(28b) 2차 증착은 상기 텅스텐실리사이드막(28a) 1차 증착 조건과 동일한 조건으로 소스가스로 1∼30sccm의 WF6를 사 용하며, 환원가스로 50∼500sccm의 SiH4 또는 SiH2Cl2을 사용하여 수행하며, 300∼600℃의 온도 및 100∼500mTorr인 압력에서 수행한다. 여기서, 상기 텅스텐실리사이드막(28a, 28b)의 1차 및 2차 증착은 전체 텅스텐실리사이드막(100) 두께 합이 800∼1500Å이 되도록 형성한다.Referring to FIG. 2C, the tungsten silicide layer 28b is secondarily deposited on the first deposited tungsten silicide layer 28a at a high flow rate ratio of a reduction gas and a source gas of 150 to 250. Here, the tungsten silicide film 28b secondary deposition uses 1 to 30 sccm WF6 as the source gas and 50 to 500 sccm SiH4 as the reducing gas under the same conditions as the primary deposition conditions for the tungsten silicide film 28a. SiH 2 Cl 2 is used and the temperature is 300-600 ° C. and 100-500 mTorr. Here, the first and second depositions of the tungsten silicide films 28a and 28b are formed such that the total thickness of the entire tungsten silicide films 100 is 800 to 1500 mW.

여기서, 본 발명은, 본 발명은 텅스텐실리사이드막(28a)을 1차로 환원가스와 소스가스의 유량비가 2∼180인 저 유량비로 증착하고, 2차로 환원가스와 소스가스의 유량비가 150∼250인 고 유량비로 텅스텐실리사이드막(28b)을 증착함으로 인하여, 폴리실리콘막(27) 표면에 첨점이 발생하여도 텅스텐실리사이드막(100)은 폴리실리콘막(27) 상에 균열없이 균일하게 증착할 수 있다. In the present invention, in the present invention, the tungsten silicide film 28a is first deposited at a low flow rate ratio of the flow rate of the reducing gas and the source gas of 2 to 180, and the flow rate ratio of the reducing gas and the source gas of the secondary gas is 150 to 250. By depositing the tungsten silicide film 28b at a high flow rate, the tungsten silicide film 100 can be uniformly deposited on the polysilicon film 27 without cracking even if a peak is generated on the surface of the polysilicon film 27. .

도 2d를 참조하면, 상기 2차로 증착된 텅스텐실리사이드막(28b) 상에 하드마스크막(29)을 증착한 후, 상기 하드마스크막(29), 2차 및 1차로 증착된 텅스텐실리사이드막(28b, 28a), 폴리실리콘막(27) 및 게이트절연막(26)을 식각하여 본 발명에 따른 리세스 게이트(30)를 형성한다.Referring to FIG. 2D, after the hard mask layer 29 is deposited on the second deposited tungsten silicide layer 28b, the hard mask layer 29, the second and first deposited tungsten silicide layers 28b are formed. , 28a), the polysilicon layer 27 and the gate insulating layer 26 are etched to form a recess gate 30 according to the present invention.

전술한 바와 같이, 본 발명은 텅스텐실리사이드막 형성시 환원가스와 소스가스의 유량비가 2∼180인 저 유량비를 갖는 텅스텐실리사이드막(28a)을 1차 증착함으로써, 스텝 커버러지 특성이 좋아 폴리실리콘막(27) 표면에 발생된 첨점을 채우는 능력을 개선시켜 후속 2차로 증착하는 텅스텐실리사이드막(28b) 증착시 균열없이 증착할 수 있다. As described above, in the present invention, a polysilicon film having good step coverage characteristics is formed by first depositing a tungsten silicide film 28a having a low flow rate ratio of reducing gas and source gas having a flow rate ratio of 2 to 180 when forming a tungsten silicide film. (27) It is possible to deposit without cracking during the deposition of the tungsten silicide film 28b which is subsequently deposited on the surface by improving the ability to fill in the fine points generated on the surface.

또한, 본 발명은 상기 텅스텐실리사이드막(28a) 1차 증착을 얇게 증착하기 때문에 하부 폴리실리콘막으로 부터 Si이 공급되어 산화에 참여함으써 후속 게이트 재산화 공정시 W(텅스텐)의 산화가 최소화 되어 텅스텐실리사이드막(100) 측벽에 비정상적인 산화막이 형성되지 않는다.In addition, in the present invention, since the first deposition of the tungsten silicide layer 28a is thinly deposited, Si is supplied from the lower polysilicon layer to participate in oxidation, thereby minimizing the oxidation of W (tungsten) during the subsequent gate reoxidation process. Abnormal oxide film is not formed on the side wall of the tungsten silicide film 100.

게다가, 환원가스와 소스가스의 유량비가 150∼250인 고 유량비를 갖는 텅스텐실리사이드막(28b)을 2차 증착함으로써, 후속 게이트 재산화 공정시 Si(실리콘)과 W이 안정적인 화학 결합을 하여 텅스텐실리사이드막(100) 측벽에 비정상적인 산화막이 형성되지 않는다. In addition, by depositing a second tungsten silicide film 28b having a high flow rate ratio of reducing gas and source gas having a flow rate of 150 to 250, Si (silicon) and W are stably chemically bonded to tungsten silicide in a subsequent gate reoxidation process. No abnormal oxide film is formed on the sidewall of the film 100.

이상에서와 같이, 본 발명은 텅스텐실리사이드막을 1차로 환원가스와 소스가스의 저 유량비로 증착하고, 2차로 환원가스와 소스가스의 고 유량비로 텅스텐실리사이드막을 증착함으로 인하여, 폴리실리콘막 표면에 첨점이 발생하여도 텅스텐실리사이드막은 폴리실리콘막 상에 균열(seam)없이 균일하게 증착할 수 있다. As described above, the present invention deposits a tungsten silicide film at a low flow rate ratio of a reducing gas and a source gas first, and a tungsten silicide film is deposited at a high flow rate ratio of a reducing gas and a source gas in a second manner. Even if it occurs, the tungsten silicide film can be uniformly deposited on the polysilicon film without cracking.

따라서, 본 발명은 텅스텐실리사이드막에 발생된 균열에 따른 결함 발생을 근본적으로 해결할 수 있어 소자의 수율 향상을 기대할 수 있다.Therefore, the present invention can fundamentally solve the defect occurrence due to the crack generated in the tungsten silicide film, and thus can improve the yield of the device.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified to

Claims (5)

액티브영역을 한정하는 소자분리막이 구비된 반도체기판을 마련하는 단계; 상기 기판 액티브영역의 게이트 형성 영역을 식각하여 홈을 형성하는 단계; 상기 홈을 포함한 기판 액티브영역 상에 게이트절연막을 형성하는 단계; 상기 게이트절연막을 포함한 기판 상에 홈을 매립하도록 폴리실리콘막, 텅스텐실리사이드막 및 하드마스크막을 차례로 형성하는 단계; 및 상기 하드마스크막, 텅스텐실리사이드막, 폴리실리콘막 및 게이트절연막을 식각하는 단계;를 포함하는 반도체 소자의 리세스 게이트 형성방법에 있어서,Providing a semiconductor substrate having an isolation layer defining an active region; Etching a gate forming region of the substrate active region to form a groove; Forming a gate insulating film on the substrate active region including the groove; Sequentially forming a polysilicon film, a tungsten silicide film, and a hard mask film to fill a groove on the substrate including the gate insulating film; And etching the hard mask layer, the tungsten silicide layer, the polysilicon layer, and the gate insulating layer. 상기 텅스텐실리사이드막은 환원가스와 소스가스의 유량비가 2∼180인 저 유량비로 1차 증착하고, 환원가스와 소스가스의 유량비가 150∼250인 고 유량비로 2차 증착하여 형성하는 것을 특징으로 하는 반도체 소자의 리세스 게이트 형성방법.The tungsten silicide film is formed by first depositing at a low flow rate ratio of a flow rate of reducing gas and a source gas of 2 to 180, and second deposition of a tungsten silicide film at a high flow rate ratio of a flow rate of reducing gas and a source gas of 150 to 250. Method of forming recess gate of device. 제 1 항에 있어서, 상기 텅스텐실리사이드막의 1차 및 2차 증착은 소스가스로 1∼30sccm의 WF6를 사용하며, 환원가스로 50∼500sccm의 SiH4 또는 SiH2Cl2로 사용하는 것을 특징으로 하는 반도체 소자의 리세스 게이트 형성방법.The semiconductor device of claim 1, wherein the first and second depositions of the tungsten silicide layer use 1 to 30 sccm of WF 6 as a source gas and 50 to 500 sccm of SiH 4 or SiH 2 Cl 2 as a reducing gas. A method of forming a set gate. 제 1 항에 있어서, 상기 텅스텐실리사이드막의 1차 및 2차 증착은 300∼600℃의 온도 및 0.1∼5Torr인 압력인 조건에서 수행하는 것을 특징으로 하는 반도체 소자의 리세스 게이트 형성방법.The method of claim 1, wherein the first and second depositions of the tungsten silicide layer are performed at a temperature of 300 to 600 ° C. and a pressure of 0.1 to 5 Torr. 제 1 항에 있어서, 상기 텅스텐실리사이드막의 1차 및 2차 증착은 전체 두께합이 800∼1500Å이 되도록 형성하는 것을 특징으로 하는 반도체 소자의 리세스 게이트 형성방법.The method of claim 1, wherein the first and second depositions of the tungsten silicide layer are formed such that the total thickness is 800 to 1500 Å. 제 1 항에 있어서, 상기 텅스텐실리사이드막의 1차 증착은 전체 텅스텐실리사이드막 형성 두께의 1/20∼1/2 두께로 수행하는 것을 특징으로 하는 반도체 소자의 리세스 게이트 형성방법.The method of claim 1, wherein the first deposition of the tungsten silicide layer is performed at a thickness of 1/20 to 1/2 of the total thickness of the tungsten silicide layer.
KR1020050092043A 2005-09-30 2005-09-30 Method for forming recessed gate of semiconductor device KR100680971B1 (en)

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