KR20010008428A - Method for forming gate electrode - Google Patents
Method for forming gate electrode Download PDFInfo
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- KR20010008428A KR20010008428A KR1019980062506A KR19980062506A KR20010008428A KR 20010008428 A KR20010008428 A KR 20010008428A KR 1019980062506 A KR1019980062506 A KR 1019980062506A KR 19980062506 A KR19980062506 A KR 19980062506A KR 20010008428 A KR20010008428 A KR 20010008428A
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- South Korea
- Prior art keywords
- oxide film
- oxygen gas
- forming
- temperature
- gate electrode
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 37
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 25
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 9
- 239000007789 gas Substances 0.000 claims abstract description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229940110728 nitrogen / oxygen Drugs 0.000 claims 1
- 230000000630 rising effect Effects 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 15
- 230000007547 defect Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002498 deadly effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
Description
본 발명은 반도체소자의 게이트전극에 관한 것으로, 특히, 반도체기판에 게이트 산화막, 폴리실리콘층 및 텅스텐실리사이드층을 적층한 후 텅스텐실리사이드층에 산화막을 증착할 때, 웨이퍼를 산화에 필요한 온도까지 상승시킨 후 질소가 함유된 묽은 산소가스로 얇은 두께의 산화막을 형성한 후 다시 산소가스만으로 옥시데이션공정을 수행하여 일정한 균일도를 유지하는 산화막을 형성하도록 하는 게이트전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate electrode of a semiconductor device. In particular, when a gate oxide film, a polysilicon layer, and a tungsten silicide layer are laminated on a semiconductor substrate and an oxide film is deposited on the tungsten silicide layer, the wafer is raised to a temperature necessary for oxidation. After forming a thin oxide film with a thin oxygen gas containing nitrogen after the oxidation process is performed only with oxygen gas again to form an oxide film to maintain a constant uniformity.
일반적으로, 트랜지스터의 게이트를 형성하면서 기판 상에 게이트산화막을 적층하고, 연속하여 폴리실리콘층 및 텅스텐실리사이드층을 적층한 후 감광막으로 패터닝하여 산화막을 적층한다. 이후 후속공정에서 이온 임플랜테이션공정을 진행할 때 개방된 액티브영역에 이온이 주입되는 경우 이 산화막은 장벽층(Barrier Layer)으로서 역할을 수행하게 되는 것이다.In general, a gate oxide film is laminated on a substrate while forming a gate of a transistor, a polysilicon layer and a tungsten silicide layer are successively stacked, and then patterned with a photosensitive film to deposit an oxide film. Subsequently, when ions are implanted in the open active region during the ion implantation process in the subsequent process, the oxide film serves as a barrier layer.
종래에 텅스텐실리사이드층에 산화막을 형성하는 공정은 게이트 패터닝 후에 LPCVD 산화막을 증착한 이후 블랭킷에치(Blanket Etch)를 실시하여 일정한 두께의 산화막을 남기는 방법과 건식 옥시데이션공정(Dry Oxidation)을 사용하여 일정한 두께의 산화막층을 형성하는 방법을 사용하고 있다.Conventionally, a process of forming an oxide film on a tungsten silicide layer is performed by depositing an LPCVD oxide film after gate patterning, followed by blanket etching to leave an oxide film having a constant thickness, and using a dry oxidation process (Dry Oxidation). The method of forming the oxide film layer of fixed thickness is used.
도 1 내지 도 4는 일반적인 반도체소자에서 게이트를 형성하는 공정을 순차적으로 보인 도면이다.1 to 4 are diagrams sequentially illustrating a process of forming a gate in a general semiconductor device.
도 1 및 도 2는 반도체기판(10)에 게이트산화막(20) 및 폴리실리콘층(30)을 적층한 상태를 도시하고 있다.1 and 2 illustrate a state in which the gate oxide film 20 and the polysilicon layer 30 are stacked on the semiconductor substrate 10.
도 3은 상기 폴리실리콘층(30) 상에 텅스텐실리사이드층(40)을 적층한 후 게이트전극이 형성될 부위에 감광막(50)을 적층한 후 도 4에서와 같이 식각으로 패턴을 형성하고, 그 위에 산화막(60)을 적층하게 된다.3, after the tungsten silicide layer 40 is stacked on the polysilicon layer 30, the photoresist film 50 is laminated on the portion where the gate electrode is to be formed, and a pattern is formed by etching as shown in FIG. The oxide film 60 is laminated on it.
한편, 전자의 방법은 건식식각의 빠른 식각특성으로 인하여 웨이퍼내에서 균일한 산화막층의 확보가 불가능하여 사용하지 않고 있으며, 후자의 방법은 건식 옥시데이션공정시 승온 단계에서 하부층에 있는 텅스텐실리사이드층의 측벽(Side Wall)과 산소가 비정상적인 반응으로 인하여 도 5와 같이, 사이드 월 블로업 디펙트(Side Wall Blow-Up Defect)가 발생되어 묽은 산소가스(Diluted O2Gas)를 사용할 수 없게 된다.On the other hand, the former method is not used because it is impossible to secure a uniform oxide layer in the wafer due to the fast etching characteristics of dry etching, and the latter method does not use the tungsten silicide layer in the lower layer during the temperature rising step during the dry oxidization process. Due to an abnormal reaction between the side wall and the oxygen, as shown in FIG. 5, a side wall blow-up defect is generated, and thus, diluted O 2 gas cannot be used.
따라서, 상기한 사이드월 블로업 디펙트가 발생하게 되면, 필림의 리프팅 현상이 발생하거나 후속 임플랜테이션(Implantation)공정에서 개방된 활성영역(Active Region)으로 도핑되는 도펀트에 대하여 장벽층으로서 역할을 하게 되어 반도체장치의 전기적인 특성에 치명적으로 작용하게 된다. 즉, 디펙트의 발생을 막기위하여 승온과정에서 묽은 산소가스를 사용하지 않으면, 웨이퍼내에서의 두께의 균일도가 5 ∼ 20 % 정도로 악화되어 균일한 임플랜테이션 장벽층으로서의 역할을 수행하지 못하는 문제점을 지니고 있었다.Therefore, when the sidewall blow-up defect occurs, the film may be lifted or may serve as a barrier layer for the dopant doped into an open active region in a subsequent implantation process. As a result, the electrical properties of the semiconductor device can be deadly. In other words, if dilute oxygen gas is not used during the temperature increase process to prevent the occurrence of defects, the uniformity of the thickness in the wafer may deteriorate to about 5 to 20%, which may not serve as a uniform implantation barrier layer. there was.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판에 게이트 산화막, 폴리실리콘층 및 텅스텐실리사이드층을 적층한 후 텅스텐실리사이드층에 산화막을 증착할 때, 웨이퍼를 산화에 필요한 온도까지 상승시킨 후 질소가 함유된 묽은 산소가스로 얇은 두께의 산화막을 형성한 후 다시 산소가스만으로 옥시데이션공정을 수행하여 일정한 균일도를 유지하는 산화막을 형성하는 것이 목적이다.The present invention has been made in view of this point, and when a gate oxide film, a polysilicon layer, and a tungsten silicide layer are laminated on a semiconductor substrate and an oxide film is deposited on the tungsten silicide layer, the wafer is raised to a temperature necessary for oxidation and then nitrogen. The purpose of the present invention is to form an oxide film having a uniform uniformity by forming an oxide film having a thin thickness with dilute oxygen gas containing and then performing an oxidation process with only oxygen gas.
도 1 내지 도 4는 일반적인 반도체소자에서 게이트를 형성하는 공정을 순차적으로 보인 도면이고,1 to 4 are views sequentially showing a process of forming a gate in a general semiconductor device,
도 5는 일반적으로 게이트의 측벽면에 블로-업 결함(Side Blow-Up Defect)을 보인 도면.FIG. 5 generally shows a Side Blow-Up Defect on the sidewall surface of the gate. FIG.
도 6은 웨이퍼의 두께를 측정하는 위치를 보인 도면.6 is a view showing a position for measuring the thickness of the wafer.
도 7은 종래와 본 발명에 따른 산화막 공정후에 모니터링 웨이퍼의 두꼐 균일도를 보인 표.Figure 7 is a table showing the thickness uniformity of the monitoring wafer after the oxide film process according to the prior art and the present invention.
-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing
10 : 반도체기판 20 : 게이트산화막10: semiconductor substrate 20: gate oxide film
30 : 폴리실리콘층 40 : 텅스텐실리사이드층30 polysilicon layer 40 tungsten silicide layer
50 : 감광막 60 : 산화막50: photosensitive film 60: oxide film
이러한 목적은 반도체기판 상에 게이트산화막, 폴리실리콘층 및 텅스텐실리사이드층을 순차적으로 적층한 후 감광막으로 식각하여 패터닝하는 단계와; 상기 단계 후에 상기 결과물을 확산로에서 적정한 온도까지 승온하는 단계와; 상기 단계 후에 질소가스와 산소가스를 적절한 비율로 하여 얇은 두께의 제1산화막을 형성하는 단계와; 상기 단계 후에 동일한 온도에서 산소가스만으로 옥시데이션공정을 진행하여 균일하고 두꺼운 제2산화막을 형성하는 단계를 포함하는 게이트전극 형성방법을 제공함으로써 달성된다.This object comprises the steps of sequentially depositing a gate oxide film, a polysilicon layer and a tungsten silicide layer on a semiconductor substrate and etching and patterning with a photosensitive film; Heating the resultant to an appropriate temperature in the diffusion furnace after the step; Forming a first oxide film having a thin thickness using an appropriate ratio of nitrogen gas and oxygen gas after the step; After the step is achieved by providing a gate electrode forming method comprising the step of performing an oxidation process with oxygen gas only at the same temperature to form a uniform and thick second oxide film.
그리고, 상기 승온범위는 1℃/min ∼ 50℃/min이고, 상기 제1산화막을 형성하는 공정은 750 ∼ 900℃의 온도범위에서 진행하고, 15Å ∼ 30Å의 두께로 형성하도록 한다.The temperature rising range is 1 ° C./min to 50 ° C./min, and the step of forming the first oxide film is performed in a temperature range of 750 ° C. to 900 ° C. to form a thickness of 15 Pa to 30 Pa.
또한, 상기 제1산화막을 형성할 때 사용하는 질소(N2)가스 대신에 아르곤(Argon) 혹은 헬륨(Helium)가스를 사용하도록 한다.In addition, argon or helium gas may be used instead of nitrogen (N 2 ) gas used to form the first oxide film.
그리고, 상기 제2산화막을 형성할 때 산소가스만으로 10Å ∼100Å의 두께로 산화막을 형성하고, 제1,제2산화막의 최종두께는 20Å ∼150Å의 범위로 형성하도록 한다.When the second oxide film is formed, an oxide film is formed with a thickness of 10 kPa to 100 kPa only with oxygen gas, and the final thickness of the first and second oxide films is in the range of 20 kPa to 150 kPa.
그리고, 상기 제1,제2산화막을 형성할 때 사용되는 질소가스 및 산소가스의 유량은 1slpm ∼ 30slpm의 량으로 사용하도록 한다.In addition, the flow rates of nitrogen gas and oxygen gas used when forming the first and second oxide films are used in an amount of 1slpm to 30slpm.
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 일실시예에 대하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명의 일싱예의 설명은 종래의 도면을 이용하여 설명하도록 한다.Description of one example of the present invention will be described using the conventional drawings.
도 1내지 도 3은 반도체기판(10) 상에 게이트산화막(20), 폴리실리콘층(30) 및 텅스텐실리사이드층(40)을 순차적으로 적층한 후 감광막(50)으로 식각하여 패터닝하는 상태를 도시하고 있다.1 to 3 illustrate a state in which the gate oxide film 20, the polysilicon layer 30, and the tungsten silicide layer 40 are sequentially stacked on the semiconductor substrate 10 and then etched and patterned with the photoresist film 50. Doing.
그리고, 상기 단계 후에 상기 결과물을 확산로(Diffusion Furnace)에서 적정한 온도까지 점차적으로 1℃/min ∼ 50℃/min의 범위로 승온하도록 한다.After the step, the resultant is gradually heated to an appropriate temperature in a diffusion furnace (Diffusion Furnace) in the range of 1 ° C./min to 50 ° C./min.
그리고, 도 4에서와 같이, 상기 단계 후에 질소가스와 산소가스를 적절한 비율(바람직하게는 N2/O2= 5 ∼ 100%)로 하여 얇은 두께의 제1산화막을 형성하도록 한다.As shown in FIG. 4, after the step, the first oxide film having a thin thickness is formed at an appropriate ratio (preferably N 2 / O 2 = 5 to 100%) of nitrogen gas and oxygen gas.
이때, 상기 제1산화막을 형성하는 공정은 750 ∼ 900℃의 온도범위에서 진행하고, 15Å ∼ 30Å의 두께로 형성하며, 상기 제1산화막을 형성할 때 사용하는 질소가스 대신에 아르곤 혹은 헬륨가스를 사용하도록 한다.At this time, the step of forming the first oxide film is carried out in a temperature range of 750 ~ 900 ℃, and formed to a thickness of 15 ~ 30 ℃, argon or helium gas in place of the nitrogen gas used when forming the first oxide film Use it.
그리고, 상기 단계 후에 동일한 온도에서 산소가스만으로 옥시데이션공정을 진행하여 균일하고 두꺼운 제2산화막을 형성하도록 한다.After the step, the oxidation process is performed using only oxygen gas at the same temperature to form a uniform and thick second oxide film.
그리고, 상기 제2산화막을 형성할 때 산소가스만으로 10Å ∼100Å의 두께로 산화막을 형성하므로 제1,제2산화막의 최종두께는 20Å ∼150Å정도가 되도록 하고, 상기 제1,제2산화막을 형성할 때 사용되는 질소가스 및 산소가스의 유량은 1slpm ∼ 30slpm의 량으로 공급하여 사용하도록 한다.When the second oxide film is formed, an oxide film is formed with a thickness of 10 kPa to 100 kPa only with oxygen gas, so that the final thickness of the first and second oxide films is about 20 kPa to about 150 kPa, and the first and second oxide films are formed. The flow rate of nitrogen gas and oxygen gas used in the case of 1slpm ~ 30slpm is to be used.
한편, 도 6은 웨이퍼를 보인 도면으로서, P1 ∼ P9은 웨이퍼의 두께를 측정하는 위치를 도시한 것으로서, 종래의 공정을 거친 웨이퍼의 두께와 본 공정을 거친 웨이퍼의 균일도를 도 7에 도시된 표를 이용하여 나타내도록 한다.FIG. 6 is a view showing a wafer, and P1 to P9 show positions at which the thickness of the wafer is measured, and the thickness of the wafer which has been subjected to a conventional process and the uniformity of the wafer which has been subjected to this process are shown in FIG. 7. To display.
즉, 1회에서 8회에 걸쳐 측정한 것은 종래의 방식으로 형성한 웨이퍼를 우치에 따라서 측정한 균일도(%)를 우측에 표시하였으며, 9회에서 16회에 걸쳐 측정한 본 발명의 공정으로 형성한 웨이퍼의 두께를 측정하여 균일도를 우측에 표시한 것이다.That is, one to eight measurements were made on the right side of the wafer formed in the conventional manner, and the uniformity (%) measured in accordance with the tooth value was formed on the right side, and formed by the process of the present invention measured nine to 16 times. The thickness of one wafer is measured and the uniformity is shown on the right.
이와 같이, 종래의 공정을 거친 웨이퍼의 두께 균일도와 본 발명의 공정을 거친 웨이퍼의 두께 균일도를 비교하여 보면, 본 발명의 공정으로 형성된 웨이퍼가 종래에 비하여 현저하게 균일도가 증가한 것을 알 수 있다. 즉, 균일도 % 수치가 작을수록 오차가 작은 것을 나타낸다.Thus, comparing the thickness uniformity of the wafers subjected to the conventional process and the thickness uniformity of the wafers subjected to the process of the present invention, it can be seen that the wafers formed by the process of the present invention have significantly increased uniformity compared to the conventional ones. In other words, the smaller the uniformity% value, the smaller the error.
따라서, 상기한 바와 같이 본 발명에 따른 게이트전극 형성방법을 이용하게 되면, 반도체기판에 게이트 산화막, 폴리실리콘층 및 텅스텐실리사이드층을 적층한 후 텅스텐실리사이드층에 산화막을 증착하 때, 웨이퍼를 산화에 필요한 온도까지 상승시킨 후 질소가 함유된 묽은 산소가스로 얇은 두께의 제1산화막을 형성한 후 다시 산소가스만으로 옥시데이션공정을 수행하여 일정한 균일도를 유지하는 제2산화막을 형성하므로 후속 임플랜테이션공정에서 균일한 임플랜테이션 깊이를 확보하여 소자의 동작특성을 안정화시키도록 하는 매우 유용하고 효과적인 발명인 것이다.Therefore, when the gate electrode forming method according to the present invention is used as described above, when the oxide film is deposited on the tungsten silicide layer after laminating the gate oxide film, the polysilicon layer and the tungsten silicide layer on the semiconductor substrate, After raising to the required temperature, a thin oxide first oxide film was formed with dilute oxygen gas containing nitrogen, followed by oxidation process with only oxygen gas to form a second oxide film maintaining a constant uniformity. It is a very useful and effective invention to stabilize the operating characteristics of the device by ensuring a uniform implant depth.
Claims (6)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100425666B1 (en) * | 2001-07-28 | 2004-04-03 | 삼성전자주식회사 | Method of forming gete electrode in semiconductor device and method of forming cell gete electrode in non-volatile memory device by using the same |
| US6903567B2 (en) | 2002-09-26 | 2005-06-07 | Samsung Electronics Co., Ltd. | Test apparatus having multiple test sites at one handler and its test method |
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| JPH04155967A (en) * | 1990-10-19 | 1992-05-28 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH04207034A (en) * | 1990-11-30 | 1992-07-29 | Toshiba Corp | Manufacture of semiconductor device |
| KR940008071A (en) * | 1992-09-26 | 1994-04-28 | 김광호 | Manufacturing Method of Semiconductor Device |
| US5756392A (en) * | 1997-01-22 | 1998-05-26 | Taiwan Semiconductor Manuacturing Company, Ltd. | Method of formation of polycide in a semiconductor IC device |
| KR19980026845A (en) * | 1996-10-11 | 1998-07-15 | 김광호 | Heat treatment method of semiconductor process |
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| JPH04155967A (en) * | 1990-10-19 | 1992-05-28 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH04207034A (en) * | 1990-11-30 | 1992-07-29 | Toshiba Corp | Manufacture of semiconductor device |
| KR940008071A (en) * | 1992-09-26 | 1994-04-28 | 김광호 | Manufacturing Method of Semiconductor Device |
| KR19980026845A (en) * | 1996-10-11 | 1998-07-15 | 김광호 | Heat treatment method of semiconductor process |
| US5756392A (en) * | 1997-01-22 | 1998-05-26 | Taiwan Semiconductor Manuacturing Company, Ltd. | Method of formation of polycide in a semiconductor IC device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100425666B1 (en) * | 2001-07-28 | 2004-04-03 | 삼성전자주식회사 | Method of forming gete electrode in semiconductor device and method of forming cell gete electrode in non-volatile memory device by using the same |
| US6903567B2 (en) | 2002-09-26 | 2005-06-07 | Samsung Electronics Co., Ltd. | Test apparatus having multiple test sites at one handler and its test method |
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