KR100298428B1 - Method for fabricating dielectric layer of capacitor - Google Patents

Method for fabricating dielectric layer of capacitor Download PDF

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Publication number
KR100298428B1
KR100298428B1 KR1019960073485A KR19960073485A KR100298428B1 KR 100298428 B1 KR100298428 B1 KR 100298428B1 KR 1019960073485 A KR1019960073485 A KR 1019960073485A KR 19960073485 A KR19960073485 A KR 19960073485A KR 100298428 B1 KR100298428 B1 KR 100298428B1
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South Korea
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dielectric film
capacitor
ta2o5
layer
heat treatment
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KR1019960073485A
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Korean (ko)
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KR19980054337A (en
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조복원
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김영환
현대반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

PURPOSE: A method for fabricating a dielectric layer of a capacitor is provided to improve an electrical characteristic, by more effectively compensating for oxygen vacancies in a Ta2O5 dielectric layer when a deposition process and an annealing process are twice performed to form the Ta2O5 dielectric layer. CONSTITUTION: The first Ta2O5 layer(24a) is formed on a semiconductor substrate. A heat treatment process is performed regarding the first Ta2O5 layer. The second Ta2O5 layer(24b) is deposited on the first Ta2O5 layer. A heat treatment process is performed regarding the second Ta2O5 layer to crystallize the Ta2O5 layer.

Description

커패시터 유전체막 제조방법Capacitor dielectric film manufacturing method

본 발명은 커패시터에 관한 것으로, 특히 Ta2O5의 전기적 특성을 개선 시킬 수 있는 커패시터 유전체막 제조방법에 관한 것이다.The present invention relates to a capacitor, and more particularly, to a method of manufacturing a capacitor dielectric film capable of improving electrical characteristics of Ta 2 O 5 .

일반적으로 소자가 고집적화됨에 따라 특히 256M 디램급 이상의 유전체막으로 쓰이기 위해서는 좀더 높은 유전율을 갖으며 표면이 매끈하여 막의 물리적, 전기적 특성을 향상 시킬 수 있는 유전체막의 개발이 필요하게 되었다.In general, as the device is highly integrated, in order to be used as a dielectric film of 256M DRAM or more, it is necessary to develop a dielectric film having a higher dielectric constant and having a smooth surface to improve the physical and electrical properties of the film.

이하, 첨부된 도면을 참조하여 종래의 커패시터 유전체막 제조방법에 대하여 설명하면 다음과 같다.Hereinafter, a conventional capacitor dielectric film manufacturing method will be described with reference to the accompanying drawings.

제1(a)도 내지 제1(c)도는 종래의 커패시터 유전체막 제조방법을 나타낸 공정 단면도이다.1 (a) to 1 (c) are cross-sectional views showing a conventional method for manufacturing a capacitor dielectric film.

먼저, 제1(a)도에 도시한 바와같이 반도체 기판(1)상에 절연층(2)을 형성한 후, 상기 절연층(2)을 기판(1) 표면이 소정부분 노출되도록 선택적으로 식각하여 콘택홀을 형성 한다.First, as shown in FIG. 1 (a), after forming the insulating layer 2 on the semiconductor substrate 1, the insulating layer 2 is selectively etched so that the surface of the substrate 1 is partially exposed. Form a contact hole.

그리고 에치백 공정을 이용하여 상기 콘택흘내에 폴리 실리콘 플러그(3)를 형성하고, 상기 폴리 실리콘 플러그(3)상의 커패시터가 형성될 영역에 하부전극(4)을 형성 한다.The polysilicon plug 3 is formed in the contact flow using an etch back process, and the lower electrode 4 is formed in a region where a capacitor on the polysilicon plug 3 is to be formed.

이어, 제1(b)도에 도시한 바와같이 하부전극(4)상에 고유전 상수()를 갖는 Ta2O5의 유전체막(5)을 형성한다. 이때, Ta2O5유전체막(5)는 Ta 소오스로 Ta(OC2H5)5(Tantalum Ethoxide)와 O2기체를 사용하여 LPCVD(Low Pressure Chemical Vapour Deposition) 또는 PACVD(Plasma Assosted CVD)방법을 이용하여 상기 Ta2O5의 유전체막(5)을 형성한다.Next, as shown in FIG. 1 (b), a dielectric film 5 of Ta 2 O 5 having a high dielectric constant () is formed on the lower electrode 4. At this time, the Ta 2 O 5 dielectric film 5 is a low pressure chemical vapor deposition (LPCVD) or plasma assisted CVD (PACVD) method using Ta (OC 2 H 5 ) 5 (Tantalum Ethoxide) and O 2 gas as a Ta source. To form the dielectric film 5 of Ta 2 O 5 .

이어서, 제1(c)도에 도시한 바와같이 Ta2O5의 유전체막(5)상에 상부전극(6)을 형성하여 커패시터를 완성한다.Subsequently, as shown in FIG. 1 (c), the upper electrode 6 is formed on the dielectric film 5 of Ta 2 O 5 to complete the capacitor.

그러나 상기와 같은 좁래의 커패시터 유전체막 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, the above-described method for manufacturing a narrow capacitor dielectric film has the following problems.

Ta2O5의 유전체막 내부에는 산소결핍(Oxygen-Vacancy) 또는 하이드로우-카본(Hydro-Carbon)등과 같은 결함을 가지고 있어, Ta2O5의 유전체막을 O2또는 자외선의 O3분위기에서 열처리하거나, O2플라즈마 처리등을 사용하여 상기 Ta2O5의 유전체막을 개선 시킬 수 있다. 그러나 산소결핍을 효과적으로 보완해줄 수 있는 방법이 필요하다.The dielectric film of Ta 2 O 5 has defects such as oxygen-vacancy or hydrocarbon-carbon, so that the Ta 2 O 5 dielectric film is heat-treated in O 2 or ultraviolet O 3 atmosphere. Alternatively, the Ta 2 O 5 dielectric film may be improved by using an O 2 plasma treatment or the like. However, there is a need for a method that can effectively compensate for oxygen deficiency.

한편, 상기 Ta2O5는 600℃ 이상의 고온공정에서는 상기 Ta2O5의 결정화로 인해 전기적 특성이 문제가 되기 때문에 Ta2O5증착 이후에는 600℃ 이하의 저온 공정이 요구된다.On the other hand, the Ta 2 O 5, is because the high-temperature process in the above 600 ℃ the electrical properties due to crystallization of the Ta 2 O 5, Ta 2 O issue after 5 deposition is required for the low temperature process below 600 ℃.

따라서 Ta2O5증착후 600℃ 이상의 고온 열처리 또는 고온공정에 노출되면 비정질 Ta2O5이 결정와 되면서 누설전류 특성을 열화 시킨다.Therefore, when Ta 2 O 5 is exposed to high temperature heat treatment or high temperature process of 600 ° C. or higher, Ta 2 O 5 becomes crystallized and degrades leakage current characteristics.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 제 1, 제 2 Ta2O5을 증착하고 열처리하여 Ta2O5의 전기적 특성 개선 및 커패시터 형성 이후의 고온공정에서도 안정한 전기적 특성을 유지찰 수 있도록 한 커패시티 유전체막 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems by depositing and heat-treating the first and second Ta 2 O 5 to improve the electrical properties of Ta 2 O 5 and to maintain stable electrical properties even in high temperature process after capacitor formation It is an object of the present invention to provide a method for manufacturing a capacitance dielectric film.

제1(a)도 내지 제1(c)도는 종래의 커패시터 유전체막 제조방법을 나타낸 공정 단면도.1 (a) to 1 (c) are cross-sectional views showing a conventional method for manufacturing a capacitor dielectric film.

제2(a)도 내지 제2(c)도는 본 발명의 커패시터 옥전체막 제조방법을 나타낸 공정.2 (a) to 2 (c) are steps showing a method for manufacturing a capacitor dielectric film of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

20 : 기판 21 : 절연층20: substrate 21: insulating layer

22 : 폴리 실리콘 플러그 23 : 하부전극22 polysilicon plug 23 lower electrode

24a : 제 1 Ta2O5유전체막 24 : 제 2 Ta2O5유전체막24a: First Ta 2 O 5 Dielectric Film 24: Second Ta 2 O 5 Dielectric Film

25 : 상부전극25: upper electrode

상기와 같은 목적을 달성하기 위한 본 발명의 커패시터 유전체막 제조방법은 기판상에 제1 Ta2O5를 증착하는 단계 상기 제1 Ta2O5를 열처리하는 단계, 상기 열처리된 제 1 Ta2O5상에 제 2 Ta2O5를 증착하는 단계, 상기 제 2 Ta2O5를 열처리하는 단계를 포함하여 상기 Ta2O5를 결정화 시킴을 특징으로 한다.In the capacitor dielectric film manufacturing method of the present invention for achieving the above object, the step of depositing a first Ta 2 O 5 on a substrate heat-treating the first Ta 2 O 5 , the heat-treated first Ta 2 O depositing a Ta 2 O 5 on claim 2 5, including the step of heat-treating the claim 2 Ta 2 O 5 is characterized in the crystallization Sikkim the Ta 2 O 5.

이하, 첨부된 도면을 참조하여 본 발명의 커패시터 유전체막 제조방법에 대하여 보다 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a capacitor dielectric film according to the present invention will be described in detail with reference to the accompanying drawings.

제2(a)도 내지 제2(c)도는 본 발명의 커패시터 유전체막 제조방법을 나타낸 공정 단면도이다.2 (a) to 2 (c) are cross-sectional views illustrating a method of manufacturing the capacitor dielectric film of the present invention.

제2(a)도에 도시한 바와같이 반도체 기판(20)상에 절연충(21)을 형성한 후, 상기 절연충(21)을 기판(20) 표면이 소정부분 노출되도록 선택적으로 식각하여 콘택홀을 형성 한다.As shown in FIG. 2 (a), after the insulating worms 21 are formed on the semiconductor substrate 20, the insulating worms 21 are selectively etched to expose a predetermined portion of the surface of the substrate 20. Form a hole.

그리고 에치백 공정을 이용하여 상기 콘택홀내에 폴리 실리콘 플러그(22)를 형성하고, 상기 폴리 실리콘 플러그(22)상의 커패시터가 형성될 영역에 하부전극(23)을 형성 한다.The polysilicon plug 22 is formed in the contact hole using an etch back process, and the lower electrode 23 is formed in the region where the capacitor on the polysilicon plug 22 is to be formed.

이어, 제2(b)도에 도시한 바와같이 하부전극(23)상에 제 1 Ta2O5유전체막(24a)를 증착한 후, 상기 제 1 Ta2O5유전체막(24a)를 열처리한다. 그리고 상기 열처리된 제 1 Ta2O5유전체막(24a)상에 제 2 Ta2O5유전체막(24b)를 증착한 후, 상기 제 2 Ta2O5유전체막(24b)를 열처리한다. 이때, 상기 열처리는 O2또는 N2O의 분위기에서 600℃이상으로 열처리 한다.Subsequently, as shown in FIG. 2 (b), after depositing the first Ta 2 O 5 dielectric film 24a on the lower electrode 23, the first Ta 2 O 5 dielectric film 24a is heat-treated. do. After the second Ta 2 O 5 dielectric film 24b is deposited on the heat treated first Ta 2 O 5 dielectric film 24a, the second Ta 2 O 5 dielectric film 24b is heat-treated. At this time, the heat treatment is heat treatment at 600 ℃ or more in the atmosphere of O 2 or N 2 O.

그리고 상기 제 1, 제 2 Ta2O5유전체막(24a)(24b)는 Ta(OC2H5)와 O2가스를 소오스로 하여 증착하며, 상기 Ta2O5증착과 열처리 단계를 3회 이상 반복 할 수도 있다.The first and second Ta 2 O 5 dielectric films 24a and 24b are deposited using Ta (OC 2 H 5 ) and O 2 gas as a source, and the Ta 2 O 5 deposition and heat treatment steps are performed three times. You can also repeat the above.

이어서 제2(c)도에 도시한 바와같이 제 2 Ta2O5유전체막(24b)상에 상부전극(25)을 형성하여 커패시터를 완성한다.Subsequently, as shown in FIG. 2 (c), the upper electrode 25 is formed on the second Ta 2 O 5 dielectric film 24b to complete the capacitor.

이상에서 설명한 바와같이 본 발명의 커패시터 유전체막 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the capacitor dielectric film manufacturing method of the present invention has the following effects.

첫째, Ta2O5유전체막 형성시 2번의 증착과 열처리 과정에서 Ta2O5유전체막내 산소결핍을 보다 효과적으로 보충해줄 수 있어 전기적 특성이 개선 시킬 수 있다.Firstly, Ta 2 O 5 dielectric layer formed upon it can do more than supplement effectively the Ta 2 O 5 dielectric membrane oxygen deficiency in the second single deposition and heat treatment may improve the electrical characteristics.

둘째 두번에 걸친 고온 O2열처리 과정에서 Ta2O5의 결정화가 두번에 걸쳐 이루어지기 때문에 두개의 Ta2O5층의 경계면 및 결정방향의 미스마치(Mismatch) 효과에 의해 누설전류 특성을 개선 시킬 수 있다.Second, since Ta 2 O 5 is crystallized twice in two high temperature O 2 heat treatment processes, leakage current characteristics can be improved by the mismatch effect of the interface and crystal directions of two Ta 2 O 5 layers. Can be.

세째, Ta2O5가 이미 결정화 되었기 때문애 커패시터 형성이후, 고온공정에서도 전기적으로 안정된 구조를 유지할 수 있다.Third, since Ta 2 O 5 is already crystallized, it is possible to maintain an electrically stable structure even after the capacitor is formed at a high temperature process.

Claims (5)

기판상에 제 1 Ta2O5를 증착하는 단계; 상기 제 1 Ta2O5를 열처리하는 단계; 상기 열처리된 제 1 Ta2O5상에 제 2 Ta2O5를 증착하는 단계; 상기 제 2 Ta2O5를 열처리하는 단계를 포함하여 상기 Ta2O5를 결정화 시킴을 특징으로 커패시터 유전체막 제조방법.Depositing a first Ta 2 O 5 on the substrate; Heat-treating the first Ta 2 O 5 ; Depositing a second Ta 2 O 5 on the heat treated first Ta 2 O 5 ; Wherein the 2 Ta 2 O characterized by comprising the step of heat-treating 5 to Sikkim crystallize the Ta 2 O 5 as a capacitor dielectric film manufacturing method. 제1항에 있어서, 상기 열처리는 600℃이상으로 열처리함을 특징으로 하는 커패시터 유전체막 제조방법.The method of claim 1, wherein the heat treatment is performed at 600 ° C. or higher. 제2항에 있어서, 상기 열처리는 O2또는 N2O의 분위기에서 열처리함을 특징으로 하는 커패시터 유전체막 제조방법.The method of claim 2, wherein the heat treatment is a capacitor dielectric film manufacturing method characterized in that the heat treatment in the atmosphere of O 2 or N 2 O. 제1항에 있어서, 제 1, 제 2 Ta2O5는 Ta(OC2H5)와 O2가스를 소오스로 하여 증착함을 특징으로 하는 커패시터 유전체막 제조방법.The method of claim 1, wherein the first and second Ta 2 O 5 are deposited using Ta (OC 2 H 5 ) and O 2 gas as a source. 제1항에 있어서, 상기 Ta2O5증착과 열처리 단계를 3회 이상 반복함을 특징으로 하는 커패시터 유전체막 제조방법.The method of claim 1, wherein the Ta 2 O 5 deposition and heat treatment are repeated three or more times.
KR1019960073485A 1996-12-27 1996-12-27 Method for fabricating dielectric layer of capacitor KR100298428B1 (en)

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KR1019960073485A KR100298428B1 (en) 1996-12-27 1996-12-27 Method for fabricating dielectric layer of capacitor

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Citations (1)

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Publication number Priority date Publication date Assignee Title
KR940016791A (en) * 1992-12-19 1994-07-25 문정환 Capacitor Structure and Manufacturing Method of Semiconductor Memory Device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940016791A (en) * 1992-12-19 1994-07-25 문정환 Capacitor Structure and Manufacturing Method of Semiconductor Memory Device

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