KR20020011229A - Method of forming a capacitor - Google Patents

Method of forming a capacitor Download PDF

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Publication number
KR20020011229A
KR20020011229A KR1020000044605A KR20000044605A KR20020011229A KR 20020011229 A KR20020011229 A KR 20020011229A KR 1020000044605 A KR1020000044605 A KR 1020000044605A KR 20000044605 A KR20000044605 A KR 20000044605A KR 20020011229 A KR20020011229 A KR 20020011229A
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South Korea
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film
gas
range
dielectric film
capacitor
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KR1020000044605A
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Korean (ko)
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김경민
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000044605A priority Critical patent/KR20020011229A/en
Publication of KR20020011229A publication Critical patent/KR20020011229A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Abstract

PURPOSE: A method for fabricating a high dielectric capacitor having a metal-insulator-metal structure is provided to improve electrical characteristics of the capacitor by removing carbon from a Ta2O5 dielectric layer and further preventing an oxygen deficiency in the Ta2O5 dielectric layer. CONSTITUTION: A polysilicon layer(2) for a contact plug and a diffusion barrier(3) are formed in a contact hole of an interlayer dielectric on a semiconductor substrate(1). Next, a lower electrode(4) is formed on the diffusion barrier(3), and the Ta2O5 dielectric layer(5) is formed thereon. The Ta2O5 dielectric layer(5) is then subjected to a heat treatment at a high temperature. Subsequently, the Ta2O5 dielectric layer(5) is subjected to an ozone plasma treatment to remove carbon therefrom and also prevent the oxygen deficiency therein. Thereafter, an upper electrode(6) is formed on the Ta2O5 dielectric layer(5).

Description

커패시터 제조 방법{Method of forming a capacitor}Method of forming a capacitor

본 발명은 커패시터의 제조 방법에 관한 것으로, 특히 Ta2O5유전체막의 탄소 성분을 제거하고, 산소 결핍을 방지하여 커패시터의 전기적 특성을 향상시킬 수 있는 커패시터의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor, and more particularly, to a method of manufacturing a capacitor capable of removing the carbon component of a Ta 2 O 5 dielectric film and preventing oxygen deficiency to improve electrical characteristics of the capacitor.

종래의 Ta2O5유전체막을 이용한 커패시터의 하부 전극은 일반적으로 RTN 표면 처리된 Poly-Si를 사용하여 왔다. 그러나, 소자가 점점 고집적화 됨에 따라 안정된 소자 동작을 위해 필요한 셀당 커패시턴스(Capacitance)를 만족하기 위해서는 Poly-Si을 하부 전극으로 하는 Ta2O5커패시터 구조는 한계에 도달하게 된다. 이러한 문제를 해결하기 위해 최근 가장 활발하게 연구가 진행되고 있는 것은 금속 하부 전극을 도입해 Ta2O5유전체막의 두께를 낮추는 방법이다.The lower electrode of a capacitor using a conventional Ta 2 O 5 dielectric film has generally used Poly-Si surface-treated with RTN. However, as the device becomes more integrated, the Ta 2 O 5 capacitor structure with Poly-Si as the lower electrode reaches its limit in order to satisfy the per-cell capacitance required for stable device operation. In order to solve this problem, the most active research is recently introduced a method of reducing the thickness of the Ta 2 O 5 dielectric film by introducing a metal lower electrode.

금속 하부 전극을 도입할 경우, Ta2O5증착 후 후속 열공정으로 저온에서 N2O 또는 O2가스에 플라즈마를 여기시켜 Ta2O5박막 내에 존재하는 탄소제거 및 산소 결핍을 억제하고, 다시 고온에서 퍼니스 어닐링(Furnace Anneal)하여 Ta2O5유전체막을 결정화시켰다. 하지만, 고온에서 어닐링하는 경우 Ta2O5유전체막 내에 제거되지 않은 탄소가 산소와 반응하여 CO 또는 CO2로 탈리되어 Ta2O5유전체막 내에 산소 결핍을 증가시켜 커패시터의 누설 전류 특성을 저하시키는 문제점이 있다.When the metal lower electrode is introduced, plasma is excited to N 2 O or O 2 gas at a low temperature by a subsequent thermal process after Ta 2 O 5 deposition to suppress carbon removal and oxygen deficiency present in the Ta 2 O 5 thin film, and again Furnace Anneal at high temperature to crystallize the Ta 2 O 5 dielectric film. However, when annealed at a high temperature, the carbon not removed in the Ta 2 O 5 dielectric film reacts with oxygen to be desorbed to CO or CO 2 to increase oxygen deficiency in the Ta 2 O 5 dielectric film, thereby lowering the leakage current characteristics of the capacitor. There is a problem.

따라서, 본 발명은 Ta2O5유전체막을 증착한 후 미리 고온에서 어닐링하여 Ta2O5유전체막에 존재하는 불순물을 제거하는 동시에 Ta2O5유전체막을 결정화시키고, 다시 반응성이 우수한 O3가스에 플라즈마를 여기시켜 후처리하므로써 Ta2O5유전체막 내에 존재하는 탄소를 완전히 제거하고, 산소 결핍을 방지하여 커패시터의 전기적 특성을 향상시킬 수 있는 커패시터의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is Ta 2 O 5 dielectric annealing at a high temperature in advance one after the deposited film was crystallized Ta 2 O 5 at the same time to eliminate the impurities present in the dielectric film Ta 2 O 5 dielectric film and excellent reactivity O 3 gas again It is an object of the present invention to provide a method of manufacturing a capacitor capable of improving the electrical characteristics of the capacitor by completely removing carbon present in the Ta 2 O 5 dielectric film and preventing oxygen deficiency by exciting the plasma.

도 1은 본 발명에 따른 커패시터 제조 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도.1 is a cross-sectional view of the device sequentially shown in order to explain a capacitor manufacturing method according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

1 : 반도체 기판 2 : 콘택 플러그용 폴리실리콘층DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Polysilicon layer for contact plug

3 : 확산 방지막 4 : 하부 전극3: diffusion barrier film 4: lower electrode

5 : Ta2O5유전체막 6 : 상부 전극5 Ta 2 O 5 dielectric film 6 Upper electrode

본 발명에 따른 커패시터의 제조 방법은 콘택 플러그용 폴리실리콘층 및 확산 방지막을 매립한 콘택홀을 포함하는 층간 절연막이 형성된 반도체 기판이 제공되는 단계, 확산 방지막 상에 하부 전극을 형성하는 단계, 하부 전극을 포함한 전체 상부에 유전체막을 형성하는 단계, 유전체막을 고온 열처리하는 단계, 유전체막을 O3플라즈마 처리하는 단계, 및 유전체막 상에 상부전극을 형성하는 단계를 포함하여 이루어진다.In the method of manufacturing a capacitor according to the present invention, there is provided a semiconductor substrate having an interlayer insulating film including a polysilicon layer for contact plugs and a contact hole having a diffusion barrier layer, forming a lower electrode on the diffusion barrier layer, and a lower electrode. Forming a dielectric film over the whole, including the step of performing a high temperature heat treatment of the dielectric film, O 3 plasma treatment of the dielectric film, and forming an upper electrode on the dielectric film.

상기의 단계에서, 콘택 플러그용 폴리실리콘층을 형성한 후에는 HF 또는 BOE를 이용하여 자연 산화막을 제거한다.In the above step, after forming the polysilicon layer for the contact plug, the native oxide film is removed using HF or BOE.

확산 방지막은 Ti/TiN막으로 형성한다.The diffusion barrier is formed of a Ti / TiN film.

하부 전극은 Ru 등과 같은 귀금속으로 형성한다. 이때, Ru막은 반응로의 압력을 1m 내지 9 Torr의 범위로 유지하고, 상기 반도체 기판을 200 내지 350℃ 범위의 온도로 유지한 상태에서, 10 내지 900sccm의 O2가스 및 200 내지 250℃로 가열된 기화기로 기화시킨 Tris(2,4-octanedionato)Ruthenium을 상기 반응로로 공급하여 형성한다.The lower electrode is formed of a noble metal such as Ru. At this time, the Ru film is maintained in the pressure of the reaction furnace in the range of 1m to 9 Torr, and heated to 10 to 900sccm O 2 gas and 200 to 250 ℃ while maintaining the semiconductor substrate at a temperature in the range of 200 to 350 ℃. It is formed by feeding Tris (2,4-octanedionato) Ruthenium vaporized with a vaporized gasifier into the reactor.

유전체막은 Ta2O5막등과 같은 고유전체 물질을 이용하여 형성한다. 이때, Ta2O5막은 반응로의 압력을 0.1 내지 2 Torr의 범위로 유지하고, 상기 반도체 기판을 300 내지 400℃ 범위의 온도로 유지한 상태에서, 10 내지 1000sccm의 O2가스 및 170 내지 190℃로 가열된 기화기로 기화시킨 Ta(OC2H5)5를 상기 반응로로 공급하여 형성한다.The dielectric film is formed using a high dielectric material such as a Ta 2 O 5 film. At this time, the Ta 2 O 5 film maintains the pressure of the reactor in the range of 0.1 to 2 Torr, while maintaining the semiconductor substrate at a temperature in the range of 300 to 400 ℃, 10 to 1000 sccm O 2 gas and 170 to 190 Ta (OC 2 H 5 ) 5 vaporized with a vaporizer heated to ° C is formed by feeding to the reactor.

고온 열처리는 500 내지 650℃ 범위의 온도에서 O2가스 또는 N2가스를 이용한 급속 열처리 어닐링 또는 퍼니스 어닐링한다.The high temperature heat treatment is a rapid heat annealing or furnace annealing with O 2 gas or N 2 gas at a temperature in the range from 500 to 650 ° C.

O3플라즈마 처리 공정은 10 내지 900Torr 범위의 압력, 300 내지 400℃ 범위의 서브 히터 온도 및 50 내지 400Watt 범위의 R.F 전력으로 O3및 NH3가스를 이용하여 1 내지 20분 동안 실시한다. 이때, O3가스의 유량은 10000 내지 200000ppm으로 하며, R.F 전력을 샤워 헤드에 인가하고, 서브 히터를 접지시킨다. O3가스 대신에 N2O 가스 또는 O2가스를 이용할 수도 있다.The O 3 plasma treatment process is carried out for 1 to 20 minutes using O 3 and NH 3 gas at a pressure ranging from 10 to 900 Torr, a sub heater temperature ranging from 300 to 400 ° C., and an RF power ranging from 50 to 400 Watts. At this time, the flow rate of the O 3 gas is 10000 to 200000 ppm, RF power is applied to the shower head, and the sub heater is grounded. N 2 O gas or O 2 gas may be used instead of O 3 gas.

O3플라즈마 처리 대신에 자외선/오존 처리를 실시할 수도 있다.Ultraviolet / ozone treatment may be performed instead of the O 3 plasma treatment.

상부 전극은 TiN막 또는 Ru막 등과 같은 귀금속으로 형성한다.The upper electrode is made of a noble metal such as a TiN film or a Ru film.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

도 1a 내지 도 1d는 본 발명에 따른 커패시터의 제조 방법을 설명하기 위하여 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of devices shown for explaining a method of manufacturing a capacitor according to the present invention.

도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(1) 상에 콘택 플러그용 폴리실리콘층(2)을 형성하고, 확산 방지막(3)을 형성한다. 일반적으로 콘택 플러그용 폴리실리콘층(2) 및 확산 방지막(3)은 하부층과 상부층과의 절연을 위한 층간 절연막(도시되지 않음)에 형성된 콘택홀을 매립하는 형태로 형성된다. 이후, 하부층과의 수직 배선을 위해 콘택홀에 형성된 플러그(2 및 3) 상에 하부 전극(4)을 형성한다.Referring to FIG. 1A, a polysilicon layer 2 for a contact plug is formed on a semiconductor substrate 1 on which various elements for forming a semiconductor element are formed, and a diffusion barrier layer 3 is formed. In general, the contact plug polysilicon layer 2 and the diffusion barrier 3 are formed to fill contact holes formed in an interlayer insulating film (not shown) for insulating the lower layer and the upper layer. Thereafter, the lower electrode 4 is formed on the plugs 2 and 3 formed in the contact holes for vertical wiring with the lower layer.

콘택 플러그용 폴리실리콘층(2)을 형성한 후에는 표면을 HF 또는 BOE(Buffer oxide etchant)로 식각하여 자연 산화막을 제거한다. 확산 방지막(3)은 상부층과의 기생 반응을 방지하기 위하여 형성되며, Ti/TiN을 증착하여 형성한다. 하부 전극(4)은 귀금속류를 이용하여 형성하며, 본 발명에서는 Ru을 이용하여 형성한다. 하부 전극(4)을 형성하는 Ru막은 반응로의 압력을 1m 내지 9 Torr의 범위로 유지하고, 반도체 기판을 200 내지 350℃ 범위의 온도로 유지한 상태에서, 10 내지 900sccm의 O2가스 및 200 내지 250℃로 가열된 기화기로 기화시킨 Tris(2,4-octanedionato)Ruthenium을 반응로로 공급하여 형성한다.After forming the polysilicon layer 2 for the contact plug, the surface is etched with HF or BOE (Buffer oxide etchant) to remove the native oxide film. The diffusion barrier 3 is formed to prevent parasitic reaction with the upper layer, and is formed by depositing Ti / TiN. The lower electrode 4 is formed using noble metals, and is formed using Ru in the present invention. The Ru film forming the lower electrode 4 maintains the pressure of the reaction furnace in the range of 1 m to 9 Torr and maintains the semiconductor substrate at a temperature in the range of 200 to 350 ° C., with 10 to 900 sccm of O 2 gas and 200 It is formed by feeding Tris (2,4-octanedionato) Ruthenium vaporized with a vaporizer heated to 250 ° C. to a reactor.

도 1b를 참조하면, 전체 상부에 유전체막(5)을 형성한다.Referring to FIG. 1B, the dielectric film 5 is formed over the entire surface.

유전체막(5)은 고유전율값을 가지는 유전체를 이용하여 형성하며, 본 발명에서는 Ta2O5로 유전체막(5)을 형성한다. Ta2O5유전체막(5)은 반응로의 압력을 0.1 내지 2 Torr의 범위로 유지하고, 반도체 기판을 300 내지 400℃ 범위의 온도로 유지한 상태에서, 10 내지 1000sccm의 O2가스 및 170 내지 190℃로 가열된 기화기로 기화시킨 Ta(OC2H5)5를 반응로로 공급하여 형성한다.The dielectric film 5 is formed using a dielectric having a high dielectric constant value, and in the present invention, the dielectric film 5 is formed of Ta 2 O 5 . The Ta 2 O 5 dielectric film 5 maintains the pressure of the reaction furnace in the range of 0.1 to 2 Torr and maintains the semiconductor substrate at a temperature in the range of 300 to 400 ° C., and the O 2 gas and 170 of 10 to 1000 sccm. To Ta (OC 2 H 5 ) 5 vaporized with a vaporizer heated to 190 ℃ to form a reactor.

도 1c를 참조하면, 유전체막(5)을 형성한 후 고온 열처리한다. 이후, 유전체막(5) 내에 존재하는 탄소 성분을 제거하고 산소 결핍을 방지하기 위하여 O3플라즈마 처리를 한다.Referring to FIG. 1C, the dielectric film 5 is formed and then subjected to high temperature heat treatment. Thereafter, an O 3 plasma treatment is performed to remove the carbon component present in the dielectric film 5 and to prevent oxygen deficiency.

유전체막(5) 내부의 불순물을 제거하고 결정화시키기 위하여 실시하는 고온 열처리는 500 내지 650℃ 범위의 온도에서 O2가스 또는 N2가스를 이용한 급속 열처리 어닐링 또는 퍼니스 어닐링으로 실시한다.The high temperature heat treatment performed to remove and crystallize impurities in the dielectric film 5 is performed by rapid heat treatment annealing or furnace annealing using O 2 gas or N 2 gas at a temperature in the range of 500 to 650 ° C.

유전체막(5)의 불순물을 제거하고 결정화시키기 위하여 고온 열처리를 하지만, 유전체막(5) 내에는 탄소 성분이 잔류하게 된다. 이렇게 잔류하는 탄소 성분은 후속 열공정에서 유전체막(5) 내의 산소 성분과 반응하여 CO 또는 CO2로 탈리되어, 유전체막(5) 내의 산소 성분이 저하된다. 이러한 산소 성분 결핍은 커패시터의 누설 전류 특성 등과 같은 전기적 특성을 저하시키는 원인이 되며, 이를 방지하기 위하여 반응성이 우수한 O3가스에 플라즈마를 여기시켜 유전체막 O3플라즈마 처리를 한다. O3플라즈마 처리를 하게 되면, 산소 성분이 유전체막(5) 내에 존재하는 탄소와 반응하여 탄소 성분을 제거함과 동시에, 유전체막(5)에 산소 성분을 충분히 공급하여 산소 결핍을 방지해 전기적 특성을 향상시킬 수 있다.A high temperature heat treatment is performed to remove impurities from the dielectric film 5 and to crystallize it, but carbon components remain in the dielectric film 5. The remaining carbon component reacts with the oxygen component in the dielectric film 5 in the subsequent thermal process and is released to CO or CO 2, so that the oxygen component in the dielectric film 5 is lowered. This oxygen component deficiency causes electrical characteristics such as leakage current characteristics of the capacitor to be deteriorated. In order to prevent this, the dielectric film O 3 plasma treatment is performed by exciting the plasma with a highly reactive O 3 gas. When the O 3 plasma treatment is performed, the oxygen component reacts with the carbon present in the dielectric film 5 to remove the carbon component, while supplying sufficient oxygen components to the dielectric film 5 to prevent oxygen deficiency, thereby improving electrical characteristics. Can be improved.

이러한 O3플라즈마 처리 공정은 10 내지 900Torr 범위의 압력, 300 내지 400℃ 범위의 서브 히터 온도 및 50 내지 400Watt 범위의 R.F 전력으로 O3및 NH3가스를 이용하여 1 내지 20분 동안 실시한다. 이때, O3가스의 유량은 10000 내지 200000ppm으로 하며, R.F 전력은 샤워 헤드에 인가하고, 서브 히터를 접지시킨다. 또한, O3가스 대신에 N2O 가스 또는 O2가스를 이용할 수도 있다.This O 3 plasma treatment process is performed for 1 to 20 minutes using O 3 and NH 3 gas at a pressure in the range of 10 to 900 Torr, a sub heater temperature in the range of 300 to 400 ° C., and an RF power in the range of 50 to 400 Watts. At this time, the flow rate of the O 3 gas is 10000 to 200000ppm, RF power is applied to the shower head, and the sub heater is grounded. In addition, instead of O 3 gas, N 2 O gas or O 2 gas may be used.

O3플라즈마 처리 대신에 자외선/오존 처리를 할 수도 있다.Ultraviolet / ozone treatment may be used instead of O 3 plasma treatment.

도 1d를 참조하면, 유전체막(5) 상에 상부 전극(6)을 형성하여 커패시터를 제조한다. 상부 전극(6)은 하부 전극(4)과 마찬가지로 귀금속류를 이용하여 형성하며, 본 발명에서는 TiN막 또는 Ru막을 이용해 형성한다.Referring to FIG. 1D, a capacitor is manufactured by forming the upper electrode 6 on the dielectric film 5. Like the lower electrode 4, the upper electrode 6 is formed using noble metals, and in the present invention, is formed using a TiN film or a Ru film.

상술한 바와 같이, 본 발명은 유전체막을 형성하고 결정화시킨 뒤 O3플라즈마 처리 공정을 추가하여 유전체막 내에 존재하는 탄소 성분을 완전히 제거하고, 산소 성분을 충분히 공급하여 산소 결핍을 방지하므로써 커패시터의 전기적 특성을 향상시키는 효과가 있다.As described above, in the present invention, the dielectric film is formed and crystallized, and then an O 3 plasma treatment process is added to completely remove the carbon component present in the dielectric film, and the oxygen component is sufficiently supplied to prevent oxygen shortage. Has the effect of improving.

Claims (14)

콘택 플러그용 폴리실리콘층 및 확산 방지막을 매립한 콘택홀을 포함하는 층간 절연막이 형성된 반도체 기판이 제공되는 단계;Providing a semiconductor substrate having an interlayer insulating film including a contact hole having a polysilicon layer for contact plug and a contact hole filled with a diffusion barrier film; 상기 확산 방지막 상에 하부 전극을 형성하는 단계;Forming a lower electrode on the diffusion barrier layer; 상기 하부 전극을 포함한 전체 상부에 유전체막을 형성하는 단계;Forming a dielectric film over the entire top of the lower electrode; 상기 유전체막을 고온 열처리하는 단계;High temperature heat treatment of the dielectric film; 상기 유전체막을 O3플라즈마 처리하는 단계; 및O 3 plasma treatment of the dielectric film; And 상기 유전체막 상에 상부전극을 형성하는 단계로 이루어지는 것을 특징으로 하는 커패시터의 제조 방법.And forming an upper electrode on the dielectric film. 제 1 항에 있어서,The method of claim 1, 상기 콘택 플러그용 폴리실리콘층을 형성한 후 HF 또는 BOE를 이용하여 자연 산화막을 제거하는 것을 특징으로 하는 커패시터 제조 방법.After forming the polysilicon layer for the contact plug capacitor manufacturing method characterized in that to remove the natural oxide film using HF or BOE. 제 1 항에 있어서,The method of claim 1, 상기 확산 방지막은 Ti/TiN막으로 형성하는 것을 특징으로 하는 커패시터 제조 방법.The diffusion barrier is a capacitor manufacturing method, characterized in that formed of Ti / TiN film. 제 1 항에 있어서,The method of claim 1, 상기 하부 전극은 Ru막으로 형성하는 것을 특징으로 하는 커패시터 제조 방법.And the lower electrode is formed of a Ru film. 제 4 항에 있어서,The method of claim 4, wherein 상기 Ru막은 반응로의 압력을 1m 내지 9 Torr의 범위로 유지하고, 상기 반도체 기판을 200 내지 350℃ 범위의 온도로 유지한 상태에서, 10 내지 900sccm의 O2가스 및 200 내지 250℃로 가열된 기화기로 기화시킨 Tris(2,4-octanedionato)Ruthenium을 상기 반응로로 공급하여 형성하는 것을 특징으로 하는 커패시터 제조 방법.The Ru film is heated to 10 to 900 sccm O 2 gas and 200 to 250 ℃ while maintaining the pressure of the reactor in the range of 1m to 9 Torr, and maintaining the semiconductor substrate at a temperature in the range of 200 to 350 ℃ A method for producing a capacitor, characterized in that formed by supplying Tris (2,4-octanedionato) Ruthenium vaporized with a vaporizer to the reactor. 제 1 항에 있어서,The method of claim 1, 상기 유전체막은 Ta2O5막으로 형성하는 것을 특징으로 하는 커패시터 제조 방법.And the dielectric film is formed of a Ta 2 O 5 film. 제 6 항에 있어서,The method of claim 6, 상기 Ta2O5막은 반응로의 압력을 0.1 내지 2 Torr의 범위로 유지하고, 상기 반도체 기판을 300 내지 400℃ 범위의 온도로 유지한 상태에서, 10 내지 1000sccm의 O2가스 및 170 내지 190℃로 가열된 기화기로 기화시킨 Ta(OC2H5)5를 상기 반응로로 공급하여 형성하는 것을 특징으로 하는 커패시터 제조 방법.The Ta 2 O 5 film maintains the pressure of the reactor in the range of 0.1 to 2 Torr, and maintains the semiconductor substrate at a temperature in the range of 300 to 400 ℃, 10 to 1000 sccm O 2 gas and 170 to 190 ℃ A method for producing a capacitor, characterized in that formed by supplying Ta (OC 2 H 5 ) 5 vaporized with a vaporizer heated by the reactor. 제 1 항에 있어서,The method of claim 1, 상기 고온 열처리는 500 내지 650℃ 범위의 온도에서 O2가스 또는 N2가스를 이용한 급속 열처리 어닐링 또는 퍼니스 어닐링으로 실시하는 것을 특징으로 하는 커패시터 제조 방법.The high temperature heat treatment is a capacitor manufacturing method, characterized in that carried out by rapid heat treatment annealing or furnace annealing using O 2 gas or N 2 gas at a temperature in the range of 500 to 650 ℃. 제 1 항에 있어서,The method of claim 1, 상기 O3플라즈마 처리 공정은 10 내지 900Torr 범위의 압력, 300 내지 400℃ 범위의 서브 히터 온도 및 50 내지 400Watt 범위의 R.F 전력으로 O3및 NH3가스를 이용하여 1 내지 20분 동안 실시하는 것을 특징으로 하는 커패시터 제조 방법.The O 3 plasma treatment process is performed for 1 to 20 minutes using O 3 and NH 3 gas at a pressure in the range of 10 to 900 Torr, a sub heater temperature in the range of 300 to 400 ° C., and an RF power in the range of 50 to 400 Watts. Capacitor manufacturing method. 제 9 항에 있어서,The method of claim 9, 상기 O3가스의 유량은 10000 내지 200000ppm인 것을 특징으로 하는 커패시터 제조 방법.The flow rate of the O 3 gas is a capacitor manufacturing method, characterized in that 10000 to 200000ppm. 제 9 항에 있어서,The method of claim 9, 상기 O3플라즈마 처리 공정에서 상기 R.F 전력을 샤워 헤드에 인가하고, 서브 히터를 접지시키는 것을 특징으로 하는 커패시터 제조 방법.And applying the RF power to the shower head in the O 3 plasma treatment process and grounding the sub heater. 제 9 항에 있어서,The method of claim 9, 상기 O3가스 대신에 N2O 가스 또는 O2가스를 이용하는 것을 특징으로 하는 커패시터 제조 방법.N 2 O gas or O 2 gas in place of the O 3 gas, characterized in that the capacitor manufacturing method. 제 9 항에 있어서,The method of claim 9, 상기 O3플라즈마 처리 대신에 자외선/오존 처리하는 것을 특징으로 하는 커패시터 제조 방법.UV / ozone treatment instead of the O 3 plasma treatment. 제 1 항에 있어서,The method of claim 1, 상기 상부 전극은 TiN막 또는 Ru막 등과 같은 귀금속으로 형성하는 것을 특징으로 하는 커패시터 제조 방법.And the upper electrode is formed of a noble metal such as a TiN film or a Ru film.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100616187B1 (en) * 2004-10-07 2006-08-25 에스티마이크로일렉트로닉스 엔.브이. Method of forming a dielectric layer in a semiconductor device
US9275993B2 (en) 2012-09-07 2016-03-01 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100616187B1 (en) * 2004-10-07 2006-08-25 에스티마이크로일렉트로닉스 엔.브이. Method of forming a dielectric layer in a semiconductor device
US9275993B2 (en) 2012-09-07 2016-03-01 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same

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