KR20010017212A - Method of manufacturing a capacitor in a semiconductor device - Google Patents
Method of manufacturing a capacitor in a semiconductor device Download PDFInfo
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- KR20010017212A KR20010017212A KR1019990032599A KR19990032599A KR20010017212A KR 20010017212 A KR20010017212 A KR 20010017212A KR 1019990032599 A KR1019990032599 A KR 1019990032599A KR 19990032599 A KR19990032599 A KR 19990032599A KR 20010017212 A KR20010017212 A KR 20010017212A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
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Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 특히 Ta2O5막과 TiO2막의 이중막 구조를 캐패시터의 유전체막으로 적용함에 있어, TiO2막의 증착 공정을 개선하여 우수한 유전체막의 특성을 확보할 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, in applying a double layer structure of a Ta 2 O 5 film and a TiO 2 film as a dielectric film of a capacitor, the deposition process of the TiO 2 film is improved, thereby ensuring excellent dielectric film characteristics. The present invention relates to a method for producing a capacitor of a semiconductor device.
일반적으로, 반도체 소자가 고집적화 및 소형화되어감에 따라 캐패시터가 차지하는 면적 또한 줄어들고 있는 추세이다. 캐패시터의 면적이 줄어들고 있음에도 불구하고 소자의 동작에 필요한 캐패시터의 정전 용량은 확보되어야 한다. 정전 용량을 확보하기 위해 하부 전극을 3차원 구조로 형성하여 유효 표면적을 증대시키고 있으나, 이 방법 역시 한계에 도달하여 더 이상의 고집적 반도체 소자에는 적용할 수 없는 실정이다. 정전 용량을 확보하기 위한 다른 방법은 높은 유전율을 갖는 유전체를 사용하여 캐패시터를 제조하는 것이다.In general, as semiconductor devices are highly integrated and miniaturized, the area occupied by capacitors is also decreasing. Although the area of the capacitor is decreasing, the capacitance of the capacitor required for the operation of the device must be secured. In order to secure the capacitance, the lower electrode is formed in a three-dimensional structure to increase the effective surface area, but this method also reaches a limit and cannot be applied to any more highly integrated semiconductor device. Another way to ensure capacitance is to manufacture a capacitor using a dielectric having a high dielectric constant.
유전율 상수값이 25 내지 27이면서 7MV/cm2이상의 높은 절연파괴 전압 특성을 갖는 Ta2O5를 캐패시터의 유전체막으로 사용하고 있으나, 반도체 소자가 고집적화 및 소형화되어 감에 따라 Ta2O5유전체막이 갖는 유전율로는 충분한 정전 용량을 확보할 수 없어 반도체 소자의 고집적화 실현에 한계가 있다. 이를 해결하기 위해서는 Ta2O5보다 유전율 상수값이 큰 물질을 사용해야만 한다. Ta2O5보다 유전율 상수값이 큰 물질로 유전율 상수값이 40 내지 60으로 매우 큰 TiO2가 있는데, TiO2는 높은 유전율 상수값을 갖는 장점에도 불구하고, 누설 전류 특성이 매우 열악하여 캐패시터의 유전체막으로 사용하기에는 적합하지 않다. 따라서, 유전율 상수값을 Ta2O5보다 크게하면서 TiO2의 누설 전류 특성을 보완할 수 있도록 캐패시터의 유전체막으로 Ta2O5막과 TiO2막의 이중막 구조가 개발되고 있다.Ta 2 O 5 , which has a dielectric constant constant of 25 to 27 and high dielectric breakdown voltage characteristic of 7 MV / cm 2 or more, is used as the dielectric film of the capacitor, but as the semiconductor device becomes more integrated and smaller, the Ta 2 O 5 dielectric film becomes The permittivity does not ensure sufficient capacitance, and thus there is a limit to the realization of high integration of semiconductor devices. To solve this problem, a material having a higher dielectric constant than Ta 2 O 5 must be used. There is Ta 2 O 5 than the dielectric constant value of the dielectric constant as a material is very large as 40 to 60 TiO 2, TiO 2, despite the advantages of having a high permittivity constant, and the leakage current characteristic is very poor and the capacitor It is not suitable for use as a dielectric film. Therefore, there is a Ta 2 O 5 film as the dielectric film of the capacitor and the TiO 2 film is a double film structure is developed so that while increasing the dielectric constant value greater than Ta 2 O 5 can compensate for the leakage current characteristic of the TiO 2.
Ta2O5막과 TiO2막의 이중막 구조를 캐패시터의 유전체막으로 적용하는 종래 캐패시터 제조 방법을 도 1a 내지 도 1c를 참조하여 설명하면 다음과 같다.Referring to FIGS. 1A to 1C, a method of manufacturing a conventional capacitor in which a double layer structure of a Ta 2 O 5 film and a TiO 2 film is applied as a dielectric film of a capacitor is described below.
도 1a를 참조하면, 하부 전극(11)상에 저압화학기상증착법(LPCVD)으로 Ta2O5막(12)을 형성하고, Ta2O5막(12)상에 스퍼터(sputter)법으로 Ti막(13)을 증착한다.Referring to FIG. 1A, a Ta 2 O 5 film 12 is formed on a lower electrode 11 by low pressure chemical vapor deposition (LPCVD), and a sputtering method is performed on a Ta 2 O 5 film 12. A film 13 is deposited.
도 1b를 참조하면, 500℃이상의 온도 및 O2분위기에서 Ti막(13)을 급속 열처리하여 TiO2막(13a)을 형성하고, 이로 인하여 Ta2O5/TiO2막유전체막(123)이 형성된다.Referring to FIG. 1B, the Ti film 13 is rapidly heat-treated at a temperature of 500 ° C. or higher and an O 2 atmosphere to form a TiO 2 film 13a. As a result, the Ta 2 O 5 / TiO 2 film dielectric film 123 is formed. Is formed.
도 1c를 참조하면, Ta2O5/TiO2유전체막(123)상에 상부 전극(14)을 형성하여 캐패시터 제조를 완료한다.Referring to FIG. 1C, an upper electrode 14 is formed on a Ta 2 O 5 / TiO 2 dielectric layer 123 to complete capacitor manufacturing.
상기한 종래 방법에서, Ti막(13)을 충분히 산화시켜 TiO2막(13a)으로 만들기 위한 고온 급속 열처리 동안 Ta2O5막(12)의 O2가 Ti막(13)으로 확산되어 Ti막(13)의 Ti와 반응하게 되고, 이로 인하여 Ta2O5막(12)과 TiO2막(13a)과의 계면에 환원된 금속계의 Ta가 존재하게 되어 높은 누설 전류의 원인으로 작용한다. 따라서, Ta2O5/TiO2유전체막(123)의 특성이 저하되는 문제가 있다.In the conventional method, followed by sufficiently oxidizing the Ti film 13 during the high-temperature rapid heat treatment to make the TiO 2 film (13a) is O 2 of Ta 2 O 5 film 12 is diffused into the Ti film 13, a Ti film Reaction with Ti of (13) causes the reduced metallic Ta to exist at the interface between the Ta 2 O 5 film 12 and the TiO 2 film 13a, which acts as a cause of high leakage current. Therefore, there is a problem that the characteristics of the Ta 2 O 5 / TiO 2 dielectric film 123 are degraded.
따라서, 본 발명은 Ta2O5막과 TiO2막의 이중막 구조를 캐패시터의 유전체막으로 적용함에 있어, TiO2막의 증착 공정을 개선하여 우수한 유전체막의 특성을 확보할 수 있는 반도체 소자의 캐패시터 제조 방법을 제공함에 그 목적이 있다.Accordingly, in the present invention, in applying a double film structure of a Ta 2 O 5 film and a TiO 2 film as a dielectric film of a capacitor, a method of manufacturing a capacitor of a semiconductor device capable of securing excellent dielectric film characteristics by improving the deposition process of the TiO 2 film. The purpose is to provide.
이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조 방법은 기판상에 하부 전극을 형성한 후, Ta성분 화학증기와 반응 가스를 반응로에 공급하여 Ta2O5막을 증착하는 단계; 상기 Ta2O5막을 어닐링한 후, 제 1 Ti막을 증착하는 단계; 상기 제 1 Ti막을 제 1 저온 플라즈마 처리하여 제 1 TiO2막을 형성시키는 단계; 상기 제 1 TiO2막상에 제 2 Ti막을 증착하는 단계; 상기 제 2 Ti막을 제 2 저온 플라즈마 처리하여 제 2 TiO2막을 형성시키고, 이로 인하여 Ta2O5막/TiO2유전체막이 형성되는 단계; 및 상기 Ta2O5막/TiO2유전체막상에 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.Capacitor manufacturing method of a semiconductor device according to the present invention for achieving this objective is after forming the lower electrode on a substrate, depositing Ta 2 O 5 film and the Ta component supply chemical vapor and the reaction gas to the reactor; Annealing the Ta 2 O 5 film and then depositing a first Ti film; Forming a first TiO 2 film by performing a first low temperature plasma treatment on the first Ti film; Depositing a second Ti film on the first TiO 2 film; Performing a second low temperature plasma treatment on the second Ti film to form a second TiO 2 film, thereby forming a Ta 2 O 5 film / TiO 2 dielectric film; And forming an upper electrode on the Ta 2 O 5 film / TiO 2 dielectric film.
도 1a 내지 도 1c는 종래 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a capacitor of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명의 실시 예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of devices for describing a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
〈도면의 주 부분에 대한 부호의 설명〉<Explanation of symbols for main part of drawing>
11: 하부 전극 12: Ta2O5막11: lower electrode 12: Ta 2 O 5 film
13: Ti막 13a: TiO2막13: Ti film 13a: TiO 2 film
123: Ta2O5/TiO2유전체막 14: 상부 전극123: Ta 2 O 5 / TiO 2 dielectric film 14: the upper electrode
21: 하부 전극 22: 질화막21: lower electrode 22: nitride film
23: Ta2O5막 24: 제 1 Ti막23: Ta 2 O 5 film 24: First Ti film
24a: 제 1 TiO2막 25: 제 2 Ti막24a: first TiO 2 film 25: second Ti film
25a: 제 2 TiO2막 345: Ta2O5/TiO2유전체막25a: second TiO 2 film 345: Ta 2 O 5 / TiO 2 dielectric film
26: 상부 전극26: upper electrode
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 실시 예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 소자의 단면도이다.2A through 2E are cross-sectional views of devices for describing a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판이 제공되고, 제공된 기판상에 하부 전극(21)을 형성한다. HF 나 BOE(Buffer Oxide Etchant) 용액을 사용한 세정 공정으로 하부 전극(21)의 표면에 생성된 자연 산화막을 제거한다. 하부 전극(21)의 표면이 산화되는 것을 방지하기 위하여, 1 내지 5slm의 NH3가스 분위기에서 800 내지 950℃ 온도로 급속 열 질화(RTN: Rapid Thermal Nitridation) 처리하여 표면에 질화막(22)을 형성한다. Ta성분 화학증기와 반응 가스인 O2가스를 반응로에 공급하여 질화막(22)상에 Ta2O5막(23)을 증착한 후, Ta2O5막(23) 내에 존재하는 탄소화합물 및 불순물을 제거하기 위해 300 내지 500℃의 온도에서 N2O 플라즈마 어닐링을 실시한다. Ta2O5막(23)상에 CVD법 또는 스퍼터(Sputter)법으로 제 1 Ti막(24)을 증착한다.Referring to FIG. 2A, a substrate on which various elements for forming a semiconductor device are formed is provided, and the lower electrode 21 is formed on the provided substrate. The natural oxide film formed on the surface of the lower electrode 21 is removed by a cleaning process using HF or BOE (Buffer Oxide Etchant) solution. In order to prevent the surface of the lower electrode 21 from being oxidized, a rapid thermal nitriding (RTN) treatment is performed at a temperature of 800 to 950 ° C. in a NH 3 gas atmosphere of 1 to 5 slm to form the nitride film 22 on the surface. do. The Ta compound chemical vapor and O 2 gas, which is a reactant gas, were supplied to the reactor to deposit a Ta 2 O 5 film 23 on the nitride film 22, and thereafter, a carbon compound present in the Ta 2 O 5 film 23 and N 2 O plasma annealing is performed at a temperature of 300 to 500 ° C. to remove impurities. The first Ti film 24 is deposited on the Ta 2 O 5 film 23 by the CVD method or the sputtering method.
상기에서, 하부 전극(21)은 LP-CVD법, PE-CVD법, RF-마그네틱 스퍼터링법중 어느 하나의 방법을 이용하여 도프트 폴리실리콘(doped polysilicon), TiN, TiAlN, TaN, W, WN, WSi, Ru, RuO2, Ir, IrO2, Pt 등과 같은 전도성 물질을 사용하여 간단한 스택 구조(simple stacked structure), 원통형 구조(cylinder structure), 이들 이외에도 여러가지 3차원 구조로 형성한다.In the above, the lower electrode 21 is a doped polysilicon, TiN, TiAlN, TaN, W, WN using any one method of LP-CVD, PE-CVD, RF-magnetic sputtering Using a conductive material such as WSi, Ru, RuO 2 , Ir, IrO 2 , Pt, etc., a simple stacked structure, a cylindrical structure, and various other three-dimensional structures are formed.
Ta성분 화학증기는 Ta(OC2H5)5나 Ta(N(CH3)2))5와 같은 금속유기화합물 용액을 170 내지 190℃ 온도 범위로 유지되고 있는 기화기(vaporizer)에서 증발시켜 생성되며, 이렇게 생성된 Ta성분 화학증기를 10 내지 1000sccm의 O2가스와 함께 반응로에 공급하여 LP-CVD법이나 PE-CVD법에 의해 Ta2O5막(23)이 형성된다. Ta2O5막(23)을 LP-CVD법으로 증착할 경우, 반응로 내의 압력을 0.1 내지 10 torr 로 유지시키고, 웨이퍼의 온도를 350 내지 450℃로 유지시킨다. Ta2O5막(23)을 PE-CVD법으로 증착할 경우, RF 전력을 50 내지 500W로 한다.Ta-based chemical vapor is produced by evaporating a metal organic compound solution such as Ta (OC 2 H 5 ) 5 or Ta (N (CH 3 ) 2 )) 5 in a vaporizer maintained at a temperature ranging from 170 to 190 ° C. The Ta component chemical vapor thus generated is supplied to the reactor with 10 to 1000 sccm of O 2 gas to form a Ta 2 O 5 film 23 by LP-CVD or PE-CVD. When the Ta 2 O 5 film 23 is deposited by LP-CVD, the pressure in the reactor is maintained at 0.1 to 10 torr, and the temperature of the wafer is maintained at 350 to 450 ° C. When the Ta 2 O 5 film 23 is deposited by PE-CVD, the RF power is 50 to 500W.
도 2b를 참조하면, O2가스 또는 NO2가스에 플라즈마를 여기시켜 제 1 Ti막(24)을 플라즈마 처리하여 제 1 TiO2막(24a)을 형성한다.Referring to FIG. 2B, plasma is excited to O 2 gas or NO 2 gas to plasma-process the first Ti film 24 to form the first TiO 2 film 24a.
상기에서, 플라즈마 처리 공정은 반응로 내의 압력을 0.1 내지 10 Torr로 유지하고, 서브 히터(SUB HEATER)의 온도를 300 내지 500℃로 유지하며, RF 전력을 10 내지 500W로 인가하고, RF 전력 인가시 서브 히터를 그라운드(GROUND)로 하고 샤워 헤드(Shower head)를 전극(Electrode)으로 하며, 이러한 상태의 반응로에 20 내지 1000sccm의 O2가스 또는 N2O 가스를 공급하여 10sec 내지 1min 동안 실시한다.In the plasma treatment process, the pressure in the reactor is maintained at 0.1 to 10 Torr, the temperature of the sub heater (SUB HEATER) is maintained at 300 to 500 ° C, RF power is applied at 10 to 500W, and RF power is applied. Sea sub-heater as ground (GROUND) and shower head (Shower head) as an electrode (Electrode), and 20 to 1000sccm O 2 gas or N 2 O gas to the reactor in this state to carry out for 10sec to 1min do.
도 2c를 참조하면, 제 1 TiO2막(24a)상에 제 1 Ti막(24) 형성 공정과 동일한 공정으로 제 2 Ti막(25)을 형성한다.Referring to FIG. 2C, the second Ti film 25 is formed on the first TiO 2 film 24a by the same process as the process of forming the first Ti film 24.
도 2d를 참조하면, 제 1 Ti막(24)을 제 1 TiO2막(24a)으로 만드는 플라즈마 처리 공정과 동일한 공정으로 제 2 Ti막(25)을 플라즈마 처리하여 제 2 TiO2막(25a)을 형성하고, 이로 인하여 이중 구조의 Ta2O5/TiO2유전체막(345)이 형성된다.Referring to FIG. 2D, the second Ti film 25 is subjected to plasma treatment in the same process as the plasma treatment process of making the first Ti film 24 into the first TiO 2 film 24a, thereby forming the second TiO 2 film 25a. , Thereby forming a double structure Ta 2 O 5 / TiO 2 dielectric film 345.
상기에서, 제 1 TiO2막(24a) 및 제 2 TiO2막(25a)은 인-시튜(In-situ)공정으로 형성할 수 있다.In the above, the first TiO 2 film 24a and the second TiO 2 film 25a may be formed by an in-situ process.
도 2e를 참조하면, Ta2O5/TiO2유전체막(345)상에 상부 전극(26)을 형성하여 본 발명의 캐패시터가 완성된다.Referring to FIG. 2E, the capacitor of the present invention is completed by forming the upper electrode 26 on the Ta 2 O 5 / TiO 2 dielectric layer 345.
상기에서, 상부 전극(26)은 LP-CVD법, PE-CVD법, RF-마그네틱 스퍼터링법중 어느 하나의 방법을 이용하여 도프트 폴리실리콘(doped polysilicon), TiN, TiAlN, TaN, W, WN, WSi, Ru, RuO2, Ir, IrO2, Pt 등과 같은 전도성 물질을 사용하여 형성된다.In the above, the upper electrode 26 is doped polysilicon, TiN, TiAlN, TaN, W, WN using any one of the LP-CVD method, PE-CVD method, RF-magnetic sputtering method , WSi, Ru, RuO 2 , Ir, IrO 2 , Pt and the like is formed using a conductive material.
상기한 본 발명의 실시 예에 따른 Ta2O5/TiO2유전체막(345)은 Ta2O5막(23)상에 제 1 Ti막(24)을 증착한 후, 500℃이하의 온도에서 O2가스 또는 NO2가스에 플라즈마를 여기시켜 제 1 Ti막(24)을 플라즈마 처리하여 제 1 TiO2막(24a)을 형성하고, 제 1 TiO2막(24a)상에 제 2 Ti막(25)을 형성한 후, 동일한 플라즈마 처리를 실시하여 제 2 TiO2막(25a)을 형성하여 완성된다. 이와 같이 Ta2O5막상에 TiO2막을 형성하기 위한 종래 고온 급속 열처리 방법과는 달리 본 발명은 저온 플라즈마 처리 방법을 적어도 2단계로 나누어 실시하므로 Ta2O5막의 O2가 Ti막과 반응하는 것이 억제되어 Ta2O5막과 TiO2막과의 계면에 Ta가 존재하는 것을 방지할 수 있는 기술이다.In the Ta 2 O 5 / TiO 2 dielectric film 345 according to the embodiment of the present invention, the first Ti film 24 is deposited on the Ta 2 O 5 film 23, and then, at a temperature of 500 ° C. or less. O 2 claim 2 Ti film on the gas or of claim 1 Ti film 24 to plasma treatment to form a claim 1 TiO 2 film (24a), and claim 1 TiO 2 film (24a) to excite a plasma in the NO 2 gas ( After forming 25, the same plasma treatment is performed to form a second TiO 2 film 25a. As described above, unlike the conventional high temperature rapid heat treatment method for forming the TiO 2 film on the Ta 2 O 5 film, the present invention is carried out by dividing the low temperature plasma treatment method into at least two stages so that the O 2 of the Ta 2 O 5 film reacts with the Ti film. it is a technique that can suppress is prevented Ta is present at the interface between the Ta 2 O 5 film and a TiO 2 film.
상술한 바와 같이, 본 발명은 Ta2O5막을 형성한 후에 적어도 2단계의 저온 플라즈마 처리 방법으로 TiO2막을 형성하므로, Ta2O5막과 TiO2막과의 계면에 환원된 금속계의 Ta가 존재하지 않는 Ta2O5/TiO2유전체막을 얻을 수 있어, 소자의 집적화에 따른 캐패시터의 정전용량과 낮은 누설 전류를 동시에 확보할 수 있는 탁월한 효과가 있다.As described above, in the present invention, since the TiO 2 film is formed by the low temperature plasma treatment method of at least two stages after the Ta 2 O 5 film is formed, the metallic Ta reduced at the interface between the Ta 2 O 5 film and the TiO 2 film is Since a Ta 2 O 5 / TiO 2 dielectric film that does not exist can be obtained, the capacitor has an excellent effect of simultaneously acquiring a capacitor's capacitance and a low leakage current.
Claims (7)
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100418580B1 (en) * | 2001-06-12 | 2004-02-21 | 주식회사 하이닉스반도체 | Method of forming a capacitor of a semiconductor device |
| KR100440073B1 (en) * | 2001-12-10 | 2004-07-14 | 주식회사 하이닉스반도체 | A method for forming a capacitor of a semiconductor device |
| US6995071B2 (en) | 2003-05-09 | 2006-02-07 | Samsung Electronics Co., Ltd. | Methods of forming MIM type capacitor structures using low temperature plasma processing |
| US7314806B2 (en) | 2004-04-12 | 2008-01-01 | Samsung Electronics Co., Ltd. | Methods of forming metal-insulator-metal (MIM) capacitors with separate seed |
| EP2365494A1 (en) * | 2010-03-09 | 2011-09-14 | TDK Corporation | Ceramic electronic component and method of manufacturing ceramic electronic component |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0144405B1 (en) * | 1994-07-18 | 1998-07-01 | 김주용 | Capacitor Manufacturing Method of Semiconductor Device |
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1999
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100418580B1 (en) * | 2001-06-12 | 2004-02-21 | 주식회사 하이닉스반도체 | Method of forming a capacitor of a semiconductor device |
| KR100440073B1 (en) * | 2001-12-10 | 2004-07-14 | 주식회사 하이닉스반도체 | A method for forming a capacitor of a semiconductor device |
| US6995071B2 (en) | 2003-05-09 | 2006-02-07 | Samsung Electronics Co., Ltd. | Methods of forming MIM type capacitor structures using low temperature plasma processing |
| US7314806B2 (en) | 2004-04-12 | 2008-01-01 | Samsung Electronics Co., Ltd. | Methods of forming metal-insulator-metal (MIM) capacitors with separate seed |
| EP2365494A1 (en) * | 2010-03-09 | 2011-09-14 | TDK Corporation | Ceramic electronic component and method of manufacturing ceramic electronic component |
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