KR20010060565A - Method of manufacturing a capacitor in a semiconductor device - Google Patents
Method of manufacturing a capacitor in a semiconductor device Download PDFInfo
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- KR20010060565A KR20010060565A KR1019990062962A KR19990062962A KR20010060565A KR 20010060565 A KR20010060565 A KR 20010060565A KR 1019990062962 A KR1019990062962 A KR 1019990062962A KR 19990062962 A KR19990062962 A KR 19990062962A KR 20010060565 A KR20010060565 A KR 20010060565A
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- lower electrode
- layer
- semiconductor device
- contact hole
- capacitor
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 소자의 동작 속도를 향상시키고 공정 과정을 단순화하기 위한 반도페 소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device to improve the operation speed of a device and to simplify a process.
일반적으로 DRAM용 BST 캐패시터나 FeRAM용 SBT, PZT 캐패시터에서는 실리콘 기판과 하부전극의 수직 배선을 위하여 도프트 폴리실리콘을 콘택 플러그로 사용하고 있다. 그러나 도프트 폴리실리콘의 비저항은 수천 μΩ㎝로 소자의 속도를 증가시키는데 한계를 갖고 있다. 또한 도프트 폴리실리콘을 콘택홀에 플러그 형태로 매립하기 위해서는 화학기상증착법으로 증착한 후 전면식각하거나 연마하는 공정이 요구되고, 그 후 고유전체 박막의 하부전극인 플래티늄(Pt), 이리디움(Ir), 루테늄(Ru) 등의 금속과의 오믹 접촉(Ohmic contact)을 위하여 티타늄 실리사이드 등을 이용하여 접착층을 형성한 후, 하부전극과 실리사이드와의 반응을 억제하기 위하여 티타늄 나이트라이드 등과 같은 질화물을 이용하여 확산 방지막을 형성하는 등 복잡한 공정을 실시해야 하는 문제점이 있다.In general, dopant polysilicon is used as a contact plug for vertical wiring of a silicon substrate and a lower electrode in a DRAM BST capacitor, an FeRAM SBT, and a PZT capacitor. However, the resistivity of doped polysilicon is limited to increasing the speed of the device to thousands of microns. In addition, in order to fill the doped polysilicon into the contact hole in the form of a plug, a process of depositing or polishing the surface by chemical vapor deposition is required, and then platinum (Pt) and iridium (Ir), which are lower electrodes of the high-k dielectric film, are deposited. ) To form an adhesive layer using titanium silicide or the like for ohmic contact with a metal such as ruthenium (Ru), and then use a nitride such as titanium nitride to suppress the reaction between the lower electrode and the silicide. Therefore, there is a problem in that a complicated process such as forming a diffusion barrier film must be performed.
따라서, 본 발명은 캐패시터 플러그용 콘택홀의 저부에 코발트 실리사이드(CoSix)를 형성하여 접착층으로 사용하고, 코발트 실리사이드와 반응성이 없는 이리디움(Ir)을 캐패시터 플러그로 사용하는 동시에 하부전극으로 가공하므로써, 공정을 단순화할 수 있고 고온 열공정을 안정적으로 실시할 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.Therefore, the present invention forms cobalt silicide (CoSi x ) at the bottom of the capacitor plug contact hole and uses it as an adhesive layer, and by using irrium (Ir) which is not reactive with cobalt silicide as the capacitor plug and processing it as a lower electrode, It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device capable of simplifying the process and stably performing a high temperature thermal process.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조방법은 하부구조가 형성된 기판 상에 절연막 및 질화막을 순차적으로 형성한 후, 상기 질화막과 절연막의 선택된 부분을 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀 저부의 노출된 기판 상에 코발트 실리사이드를 이용하여 접촉층을 형성하는 단계; 상기 접촉층이 형성된 콘택홀을 포함하는 전체구조 상에 콘택 플러그 및 하부전극으로 사용될 물질을 증착하는 단계; 상기 하부전극 물질층의 선택된 영역을 식각하여 하부전극을 완성하는 단계; 및 상기 하부전극이 형성된 전체구조 상에 유전체막 및 상부전극을 순차적으로 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In the method of manufacturing a capacitor of a semiconductor device according to the present invention for achieving the above object, the insulating film and the nitride film are sequentially formed on a substrate on which a lower structure is formed, and then the contact holes are formed by etching selected portions of the nitride film and the insulating film. step; Forming a contact layer using cobalt silicide on the exposed substrate at the bottom of the contact hole; Depositing a material to be used as a contact plug and a lower electrode on the entire structure including the contact hole in which the contact layer is formed; Etching the selected region of the lower electrode material layer to complete the lower electrode; And sequentially forming a dielectric film and an upper electrode on the entire structure in which the lower electrode is formed.
도 1a 내지 1d는 본 발명에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.1A to 1D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 기판 12 : 절연막11 substrate 12 insulating film
13 : 질화막 14 : 콘택홀13 nitride film 14 contact hole
15 : 접촉층 16 : 하부전극15 contact layer 16 lower electrode
17 : 유전체막 18 : 상부전극17 dielectric film 18 upper electrode
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
도 1a 내지 1d는 본 발명에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 1a를 참조하여, 하부구조가 형성된 기판(11) 상에 산화물을 이용하여 절연막(12) 및 절연막(12)과 식각 선택비가 높은 질화막(13)을 순차적으로 형성한 후, 기판(11)과 캐패시터 사이의 수직 배선을 위하여 질화막(13)과 절연막(12)의 선택된 부분을 식각하여 콘택홀(14)을 형성한다. 이후, 콘택홀(14) 저부의 노출된 기판(11) 상에 오믹 접촉(Ohmic contact)을 위한 접촉층(15)으로서 코발트 실리사이드(CoSix)를 증착한다.Referring to FIG. 1A, after forming the insulating film 12, the insulating film 12, and the nitride film 13 having a high etching selectivity using an oxide on the substrate 11 on which the lower structure is formed, the substrate 11 and The contact hole 14 is formed by etching the selected portion of the nitride film 13 and the insulating film 12 for the vertical wiring between the capacitors. Thereafter, cobalt silicide (CoSi x ) is deposited as a contact layer 15 for ohmic contact on the exposed substrate 11 at the bottom of the contact hole 14.
도 1b를 참조하여, 저부에 접촉층(15)이 형성된 콘택홀(14)을 포함하는 전체구조 상에 이리디움(Ir) 또는 루테늄(Ru)을 이용하여 콘택 플러그 및 하부전극 물질층을 형성한다. 여기에서, 하부전극 물질은 화학기상증착법으로 이리디움(Ir) 또는 루테늄(Ru)을 3000 내지 10000Å의 두께로 증착하여 형성한다.Referring to FIG. 1B, a contact plug and a lower electrode material layer are formed by using iridium (Ir) or ruthenium (Ru) on an entire structure including a contact hole 14 having a contact layer 15 formed at a bottom thereof. . Here, the lower electrode material is formed by depositing iridium (Ir) or ruthenium (Ru) to a thickness of 3000 to 10000 kPa by chemical vapor deposition.
도 1c를 참조하여, 마스크를 이용한 사진 및 식각 공정에 의해 이리디움(Ir)막의 선택된 영역을 제거하여 하부전극(16)을 완성한다. 여기에서, 하부전극(16) 식각시의 하드 마스크(Hard mask)로는 티타늄 나이트라이드(TiN) 또는 실리콘 산화막(SiO2)을 사용한다.Referring to FIG. 1C, the selected region of the iridium (Ir) film is removed by a photolithography and an etching process using a mask to complete the lower electrode 16. Here, titanium nitride (TiN) or silicon oxide film (SiO 2 ) is used as a hard mask for etching the lower electrode 16.
도 1d를 참조하여, 하부전극(16)이 형성된 전체구조 상에 유전체막(17)을 형성하고 유전체막(17)을 결정화하기 위하여 열처리 공정을 실시한다. 이후, 유전체막(17) 상에 상부전극(18)을 형성하고 유전체막(17)과의 계면을 안정화시키기 위한 열처리 공정을 실시한다. 여기에서, 유전체막(17)은 고유전 박막인 BST를 150 내지 500Å의 두께로 증착하여 형성한다. 유전체막(17) 형성 후의 열처리 공정은 산소와 질소 또는 산소와 아르곤 가스 분위기로 450 내지 800℃의 온도에서 5 내지 300초 동안 급속 열처리 하는 것으로 진행한다. 또한, 상부전극(18)은 화학기상증착법으로 플래티늄(Pt) 또는 이리디움(Ir)을 500 내지 2500Å의 두께로 증착하여 형성한다. 상부전극(18) 형성 후의 열처리 공정은 산소와 질소 또는 산소와 아르곤 혼합 기체 분위기로 450 내지 800℃의 온도에서 진행한다.Referring to FIG. 1D, a heat treatment process is performed to form the dielectric film 17 on the entire structure in which the lower electrode 16 is formed and to crystallize the dielectric film 17. Thereafter, an upper electrode 18 is formed on the dielectric film 17 and a heat treatment process for stabilizing an interface with the dielectric film 17 is performed. Here, the dielectric film 17 is formed by depositing BST, which is a high dielectric thin film, at a thickness of 150 to 500 Å. After the dielectric film 17 is formed, the heat treatment step proceeds by rapid heat treatment for 5 to 300 seconds at a temperature of 450 to 800 ° C. in an oxygen and nitrogen or oxygen and argon gas atmosphere. In addition, the upper electrode 18 is formed by depositing platinum (Pt) or iridium (Ir) to a thickness of 500 to 2500Å by chemical vapor deposition. The heat treatment process after the formation of the upper electrode 18 is performed at a temperature of 450 to 800 ° C. in an oxygen and nitrogen or oxygen and argon mixed gas atmosphere.
이와 같은 방법으로 형성된 캐패시터는 충분한 정전용량 및 우수한 누설전류 특성을 가지며, 빠른 동작 속도를 갖는다.Capacitors formed in this way have sufficient capacitance and excellent leakage current characteristics, and have fast operating speeds.
상술한 바와 같이, 본 발명에 의하면 비저항이 높은 폴리실리콘을 사용하지 않고 코발트 실리사이드(CoSix)를 이용하여 콘택홀 저부에 접촉층을 형성하고, 코발트 실리사이드와 반응성이 없는 금속(Ir 또는 Ru)을 이용하여 콘택 플러그 및 하부전극을 형성하므로써, 공정을 단순화할 수 있다. 또한, 고온 열공정을 진행하면서도 충분한 정전용량 및 우수한 누설전류 특성을 확보할 수 있으며, 소자의 동작 속도를 향상시킬 수 있다.As described above, according to the present invention, a contact layer is formed on the bottom of the contact hole using cobalt silicide (CoSi x ) without using polysilicon having a high resistivity, and a metal (Ir or Ru) which is not reactive with cobalt silicide is formed. By forming the contact plug and the lower electrode by using the step, the process can be simplified. In addition, while performing a high temperature thermal process, it is possible to secure sufficient capacitance and excellent leakage current characteristics, and improve the operation speed of the device.
Claims (7)
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Cited By (1)
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KR100487519B1 (en) * | 2002-02-05 | 2005-05-03 | 삼성전자주식회사 | Capacitor Of Semiconductor Device And Method Of Fabricating The Same |
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CN102403218B (en) * | 2010-09-09 | 2013-07-24 | 上海华虹Nec电子有限公司 | Etching method for contact holes |
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KR100487519B1 (en) * | 2002-02-05 | 2005-05-03 | 삼성전자주식회사 | Capacitor Of Semiconductor Device And Method Of Fabricating The Same |
US7163859B2 (en) | 2002-02-05 | 2007-01-16 | Samsung Electronics Co., Ltd. | Method of manufacturing capacitors for semiconductor devices |
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