KR100404481B1 - Method for manufacturing capacitor semiconductor device - Google Patents
Method for manufacturing capacitor semiconductor device Download PDFInfo
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- KR100404481B1 KR100404481B1 KR10-2001-0038500A KR20010038500A KR100404481B1 KR 100404481 B1 KR100404481 B1 KR 100404481B1 KR 20010038500 A KR20010038500 A KR 20010038500A KR 100404481 B1 KR100404481 B1 KR 100404481B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 238000009832 plasma treatment Methods 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 238000005121 nitriding Methods 0.000 claims abstract description 5
- 238000007598 dipping method Methods 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 15
- 229910010282 TiON Inorganic materials 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- 239000007772 electrode material Substances 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000012495 reaction gas Substances 0.000 claims description 3
- 239000007983 Tris buffer Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- LENZDBCJOHFCAS-UHFFFAOYSA-N tris Chemical compound OCC(N)(CO)CO LENZDBCJOHFCAS-UHFFFAOYSA-N 0.000 claims description 2
- 239000006200 vaporizer Substances 0.000 claims description 2
- 239000000872 buffer Substances 0.000 claims 1
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 커패시터 전극층을 형성하기 전에 하부층의 표면을 질화시켜 전극을 형성하기 위한 박막의 균일도 및 전기적 특성을 향상시킬 수 있도록한 MIM(Metal-Insulator-Metal)구조를 갖는 반도체 소자의 커패시터 제조 방법에 관한 것으로, 콘택홀을 갖는 배선간 층간 절연층을 형성하는 단계;상기 콘택홀내에 플러그층,베리어 메탈층을 차례로 형성하는 단계;전면에 캡 산화막층을 형성하고 선택적으로 식각하여 커패시터 형성 영역을 정의하는 단계;후속되는 하부 전극 형성용 물질층의 막질을 개선하기 위하여 노출된 표면을 플라즈마 트리트먼트 공정으로 질화시키는 단계;전면에 하부 전극 형성용 물질층을 형성하고 캡 산화막을 딥 아웃하여 하부 전극을 형성하는 단계;상기 하부 전극상에 유전체층,상부 전극을 차례로 형성하는 단계를 포함한다.The present invention relates to a method of manufacturing a capacitor of a semiconductor device having a metal-insulator-metal (MIM) structure to improve the uniformity and electrical properties of a thin film for forming an electrode by nitriding the surface of the lower layer before forming the capacitor electrode layer. A method of manufacturing a semiconductor device, the method comprising: forming an interlayer insulating layer having a contact hole; sequentially forming a plug layer and a barrier metal layer in the contact hole; forming a cap oxide layer on the front surface and selectively etching to define a capacitor formation region Nitriding the exposed surface by a plasma treatment process to improve film quality of the subsequent lower electrode forming material layer; forming a lower electrode forming material layer on the front surface, and dipping out the cap oxide layer to form a lower electrode. Forming a dielectric layer and an upper electrode on the lower electrode in order.
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 특히 커패시터 전극층을 형성하기 전에 하부층의 표면을 질화시켜 전극을 형성하기 위한 박막의 균일도 및 전기적 특성을 향상시킬 수 있도록한 MIM(Metal-Insulator-Metal)구조를 갖는 반도체 소자의 커패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fabrication of semiconductor devices. In particular, a metal-insulator-metal (MIM) structure is provided to improve the uniformity and electrical properties of a thin film for forming an electrode by nitriding a surface of a lower layer before forming a capacitor electrode layer. It relates to a capacitor manufacturing method of a semiconductor device having a.
MIM 구조의 커패시터 형성시에 주로 사용되는 Ru는 전기 전도성이 좋고 고온 산화분위기에 노출되어도 전도성을 잃지 않는 특성을 가지고 있는 물질이다.Ru, which is mainly used in forming capacitors of MIM structure, is a material having good electrical conductivity and not losing its conductivity even when exposed to high temperature oxidation atmosphere.
이와 같은 특성은 향후 DRAM 커패시터의 주류를 이루게 될 MIS(Metal-Insulator-Silicon) 및 MIM 구조의 커패시터 금속 전극으로써 유용하게 활용 될 수 있을 것으로 기대되고 있다.Such characteristics are expected to be useful as capacitor metal electrodes of MIS (Metal-Insulator-Silicon) and MIM structures, which will become mainstream DRAM capacitors in the future.
즉, 차세대 커패시터 재료로서 주목을 받고 있는 TaO 나 BST용 전극 재료로 아주 적합하다.That is, it is very suitable as an electrode material for TaO or BST, which is attracting attention as a next generation capacitor material.
커패시터 전극 재료로 Ru에 요구되는 특성은 낮은 저항값 이외에도, 복잡하고 미세한 패턴상에 균일한 표면을 가지면서 좋은 스텝 커버리지로 증착되어야 한다는 것이다.The characteristic required for Ru as a capacitor electrode material is that in addition to low resistance values, it must be deposited with good step coverage while having a uniform surface on complex and fine patterns.
소자의 고집적화에 따라 MIS 구조의 TiON 커패시터에서 정전용량을 확보하기 위해서는 TiON 두께를 낮추어 확보하는 방법이 있으나, 이는 누설전류 증가의 원인이 된다.In order to secure the capacitance in the MIS-structured TiON capacitor according to the high integration of the device, there is a method of reducing the thickness of TiON, but this causes a leakage current increase.
이러한 문제점을 해결하기 위해서 메탈 하부전극을 도입해 두께를 낮추어 정전용량을 확보함과 동시에 누설전류도 확보하는 방법이 시도되고 있다.In order to solve this problem, a method of securing a leakage current while securing a capacitance by introducing a metal lower electrode to reduce the thickness has been attempted.
메탈 하부전극을 도입할 경우, 하부전극의 막질에 따라 전기적 특성에 큰 영향을 미친다.When the metal lower electrode is introduced, the electrical characteristics are greatly affected by the film quality of the lower electrode.
CVD법으로 Ru를 증착하는 경우 Ru 박막의 막질에 따라 TiON 커패시터의 전기적 특성이 크게 좌우된다. 이를 해결하기 위해서는 Ru 박막의 표면 처리나, 고온에서 어닐(Anneal)하는 방법이 필요하다.In the case of depositing Ru by CVD, the electrical characteristics of the TiON capacitor largely depend on the film quality of the Ru thin film. In order to solve this problem, a surface treatment of the Ru thin film or a method of annealing at high temperature is required.
그러나 이와 같은 종래 기술의 MIM 구조의 커패시터 전극 형성에 있어서는 다음과 같은 문제가 있다.However, there is a problem in forming a capacitor electrode of such a prior art MIM structure.
TiON 커패시터에서 정전용량을 확보하기 위해서는 TiON 두께를 낮추어 확보하는 방법이 있으나, 이는 누설전류 증가의 원인이 된다.In order to secure the capacitance in the TiON capacitor, there is a method of reducing the thickness of TiON, but this causes the leakage current to increase.
또한, 하부전극의 막질에 따라 전기적 특성에 큰 영향을 미침에도 불구하고 Ru를 증착하는 경우 이를 해결하기 위한 방법이 제시되지 않고 있다.In addition, despite the great effect on the electrical properties according to the film quality of the lower electrode has not been proposed a method for solving the case of Ru deposition.
막질 개선을 위하여 Ru 박막의 표면 처리나, 고온에서 어닐(Anneal)하는 방법을 사용하는데, 이는 충분한 막질을 제공하지 못하고 공정을 복잡하게 한다.In order to improve the film quality, surface treatment of the Ru thin film or annealing at high temperature is used, which does not provide sufficient film quality and complicates the process.
본 발명은 이와 같은 종래 기술의 MIM 커패시터 형성 공정의 문제를 해결하기 위한 것으로, 커패시터 전극층을 형성하기 전에 하부층의 표면을 질화시켜 전극을 형성하기 위한 박막의 균일도 및 전기적 특성을 향상시킬 수 있도록한 MIM(Metal-Insulator-Metal)구조를 갖는 반도체 소자의 커패시터 제조 방법을 제공하는데 그 목적이 있다.The present invention is to solve the problem of the prior art MIM capacitor forming process, and before forming the capacitor electrode layer MIM to improve the uniformity and electrical properties of the thin film for forming the electrode by forming the surface of the lower layer An object of the present invention is to provide a capacitor manufacturing method of a semiconductor device having a (Metal-Insulator-Metal) structure.
도 1a내지 도 1k는 본 발명에 따른 반도체 소자의 커패시터 형성을 위한 공정 단면도1A to 1K are cross-sectional views of a process for forming a capacitor of a semiconductor device according to the present invention.
도 2는 본 발명의 다른 실시예를 나타낸 공정 단면도2 is a process cross-sectional view showing another embodiment of the present invention.
-도면의 주요 부분에 대한 부호의 설명 -Explanation of symbols on the main parts of the drawings
11. 반도체 기판 12. 제 2 ILD층11. Semiconductor Substrate 12. Second ILD Layer
13. 콘택홀 14. 플러그 형성용 폴리층13. Contact hole 14. Poly layer for plug formation
15a.15b. 베리어 메탈층 16. 캡 산화막15a.15b. Barrier Metal Layer 16.Cap Oxide
17. 커패시터 형성 영역 18. 하부 전극 형성용 물질층17. Capacitor Formation Region 18. Lower Electrode Formation Material Layer
18a. 실린더 19. 유전층18a. Cylinder 19. Dielectric Layer
20. 상부 전극 형성용 물질층20. Material layer for forming the upper electrode
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 커패시터 제조 방법은 콘택홀을 갖는 배선간 층간 절연층을 형성하는 단계;상기 콘택홀내에 플러그층,베리어 메탈층을 차례로 형성하는 단계;전면에 캡 산화막층을 형성하고 선택적으로 식각하여 커패시터 형성 영역을 정의하는 단계;후속되는 하부 전극 형성용 물질층의 막질을 개선하기 위하여 노출된 표면을 플라즈마 트리트먼트 공정으로 질화시키는 단계;전면에 하부 전극 형성용 물질층을 형성하고 캡 산화막을 딥 아웃하여 하부 전극을 형성하는 단계;상기 하부 전극상에 유전체층,상부 전극을 차례로 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming an interlayer insulating layer having contact holes; sequentially forming a plug layer and a barrier metal layer in the contact hole; Forming a cap oxide layer and selectively etching to define a capacitor formation region; nitriding the exposed surface by a plasma treatment process to improve the film quality of the subsequent lower electrode forming material layer; forming a lower electrode on the front surface Forming a lower electrode by forming a layer for the material and dipping out the cap oxide layer; and sequentially forming a dielectric layer and an upper electrode on the lower electrode.
이하, 첨부된 도면을 참고하여 본 발명에 따른 반도체 소자의 커패시터 제조 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a capacitor manufacturing method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a내지 도 1k는 본 발명에 따른 반도체 소자의 커패시터 형성을 위한 공정 단면도이고, 도 2는 본 발명의 다른 실시예를 나타낸 공정 단면도이다.1A to 1K are cross-sectional views illustrating a process for forming a capacitor of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view illustrating another embodiment of the present invention.
본 발명은 하부 전극을 형성하기 위한 Ru 증착전 하부층을 NH3가스에 플라즈마를 여과시켜 얇게 질화(Nitridation)시켜 Ru 증착 공정시 스텝 커버리지(Step coverage)를 개선시키고, Ru 증착후 표면 거칠기(surface Roughness)를 개선을 위하여 N2+O2플라즈마 트리트먼트(treatment)를 실시한 후 TiON을 증착하여 커패시터의 전기적 특성을 향상시킬 수 있도록 한 것이다.The present invention improves the step coverage during the Ru deposition process by nitridation of the lower layer before ru deposition to form a lower electrode by filtering a plasma through NH 3 gas, and surface roughness after Ru deposition. ) were subjected to N 2 + O 2 plasma treatment (treatment) for improving the deposition of a TiON is to improve the electrical characteristics of the capacitor.
제조 공정은 먼저, 도 1a에서와 같이, 하부의 셀 트랜지스터 및 비트 라인 그리고 제 1 ILD(InterLayer Dielectric)층을 포함하는 반도체 기판(11)상에 배선간 층간 절연층으로 제 2 ILD층(12)을 형성한다.First, as shown in FIG. 1A, the fabrication process includes a second ILD layer 12 as an interlayer insulating layer on a semiconductor substrate 11 including a lower cell transistor, a bit line, and a first interlayer dielectric (ILD) layer. To form.
그리고 도 1b에서와 같이, 폴리 실리콘을 증착하기 위해 상기 제 2 ILD층(12)을 선택적으로 식각하여 콘택홀(13)을 형성한다.In addition, as shown in FIG. 1B, the second ILD layer 12 is selectively etched to form a contact hole 13 to deposit polysilicon.
이어, 도 1c에서와 같이, 플러그 형성용 폴리층(14)을 증착한 후, 콘택홀(13)의 일정 깊이까지 에치백하여 리세스시킨다.Subsequently, as illustrated in FIG. 1C, the plug forming poly layer 14 is deposited and then etched back to a predetermined depth of the contact hole 13 to be recessed.
그리고 도 1d에서와 같이, 상기 리세스 부분에 베리어 메탈층(15a)(15b)으로 Ti/TiN을 증착한다.As shown in FIG. 1D, Ti / TiN is deposited on the recess portions by barrier metal layers 15a and 15b.
이어, 도 1e에서와 같이, 커패시터 실린더(Cylinder)를 형성하기 위해 캡 산화막(16)을 증착하고, 도 1f에서와 같이, 상기 캡 산화막(16)을 에치하여 커패시터 형성 영역(17)을 정의한다.Subsequently, as shown in FIG. 1E, a cap oxide layer 16 is deposited to form a capacitor cylinder, and as shown in FIG. 1F, the cap oxide layer 16 is etched to define a capacitor formation region 17. .
그리고 도 1g에서와 같이, 상기 커패시터 형성 영역(17)을 NH3가스에 플라즈마(Plasma)를 여기시켜 트리트먼트 처리한다.As shown in FIG. 1G, the capacitor formation region 17 is treated by exciting plasma with NH 3 gas.
여기서, NH3가스의 양을 5sccm~50sccm으로 하고, 압력은 0.1torr~2torr로 유지하고 처리 시간은 5초~600초로한다.Here, the amount of NH 3 gas is 5 sccm to 50 sccm, the pressure is maintained at 0.1 to 2 tor, and the treatment time is 5 to 600 seconds.
이어, 도 1h에서와 같이, 하부 전극 형성용 물질층(18)으로 Ru를 증착한다.Subsequently, as illustrated in FIG. 1H, Ru is deposited on the lower electrode forming material layer 18.
여기서, 하부전극인 Ru의 증착 방법은 Tris(2,4-octanedionato)tuthenium를 기상상 태로 만든다.Here, the deposition method of the lower electrode Ru brings Tris (2,4-octanedionato) tuthenium into the gas phase.
그리고 웨이퍼 온도를 200℃~350℃로 유지하고 반응 가스로 O2 수십~수백 sccm로 유지하고, 반응로의 압력을 수 mTorr~수 Torr로 유지한다.Then, the wafer temperature is maintained at 200 ° C. to 350 ° C., the reaction gas is maintained at several tens to several hundred sccm of O 2, and the pressure of the reactor is maintained at several mTorr to several Torr.
이 상태에서 PECVD(Plasma Enhanced Chemical Vapour Deposition)법으로 Ru를 일부 증착한다. 이때의 조건은 R.F.Power 100watt~300watt로 유지한다.In this state, Ru is partially deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD). The condition at this time is maintained at R.F.Power 100watt ~ 300watt.
이어, 다시 LPCVD(Low Pressure CVD)법으로 Ru를 일부 증착한다. R.F.Power 인가시 서브 히터(sub heater)를 접지(ground)로 하고 샤워 헤드(shower head)를 전극으로 사용한다.Subsequently, Ru is partially deposited by LPCVD (Low Pressure CVD). When the R.F.Power is applied, the sub heater is grounded and the shower head is used as the electrode.
그리고 도 1i에서와 같이, Ru를 CMP(Chemical Mechanical Polishing)후, 캡 산화막(16)을 딥 아웃하여 실린더(18a)를 형성한다.As shown in FIG. 1I, after Ru is CMP (Chemical Mechanical Polishing), the cap oxide film 16 is diped out to form a cylinder 18a.
이어, 도 1j에서와 같이, TiCl4소오스를 170℃~190℃로 유지되는 기화기에서 기상상태로 만들고, 반응 가스인 NH3개스를 10sccm~1000sccm 정도를 사용하고, 반응로 내의 압력을 0.1torr~1.2torr로 유지하고 300℃~400℃로 가열된 웨이퍼에 유전층(19)으로 TiON을 증착한다.Subsequently, as shown in FIG. 1J, the TiCl 4 source is brought into a gaseous state in a vaporizer maintained at 170 ° C. to 190 ° C., and NH 3 gas, which is a reaction gas, is used at about 10 sccm to about 1000 sccm, and the pressure in the reactor is 0.1 tor. TiON is deposited as a dielectric layer 19 on a wafer heated at 300 to 400 ° C., maintained at 1.2 torr.
그리고 도 1k에서와 같이, 후속 열처리 공정으로 1분간 플라즈마 N2+O2처리를 300℃~500℃에서 진행하고 500℃~650℃에서 TiON 박막내 C의 제거 및 증가된 라이트라이드(Nitride) 함량을 유지하기 위하여 N2개스를 사용하여 퍼니스 바큠 어닐)(furnace Vaccum Anneal)을 실시한다.1k, the plasma N 2 + O 2 treatment was performed at 300 ° C. to 500 ° C. for 1 minute in a subsequent heat treatment process, and the removal of C and increased nitride content in the TiON thin film at 500 ° C. to 650 ° C. was performed. Furnace Vaccum Anneal is carried out using N 2 gas to maintain.
이어, 상부 전극 형성용 물질층(20)으로 Ru 또는 TiN을 증착한다.Subsequently, Ru or TiN is deposited on the upper electrode forming material layer 20.
이와 같은 본 발명의 제 1 실시예 이외에 Ru 박막의 막질을 더 개선하기 위하여 도 2에서와 같이, Ru의 증착후에 RTP(Rapid Thermal Process) 처리를 N2가스의 양을 10sccm~10slm으로 하고, 반응로의 온도를 600℃~1000℃로 유지한 상태에서 수초~수백초 진행하는 것도 가능하다.In order to further improve the film quality of the Ru thin film in addition to the first embodiment of the present invention as described above, the RTP (Rapid Thermal Process) treatment after the deposition of Ru, the amount of N 2 gas to 10sccm ~ 10slm, the reaction It is also possible to advance several seconds to several hundred seconds in the state which maintained the temperature of the furnace at 600 degreeC-1000 degreeC.
이와 같은 본 발명은 Ru 증착전 하부층을 NH3가스에 플라즈마를 여과시켜 얇게 질화(Nitridation)시켜 Ru 증착 공정시 스텝 커버리지(Step coverage)를 개선시킨다.As described above, the present invention improves step coverage during the Ru deposition process by thinly nitridating the lower layer prior to Ru deposition by filtering a plasma through NH 3 gas.
또한, Ru 증착후 표면 거칠기(surface Roughness)를 개선을 위하여 N2+O2플라즈마 트리트먼트(treatment)를 실시한 후 TiON을 증착하여 커패시터의 전기적 특성을 향상시킬 수 있도록 한 것이다.In addition, in order to improve surface roughness after Ru deposition, N 2 + O 2 plasma treatment is performed and TiON is deposited to improve electrical characteristics of the capacitor.
이와 같은 본 발명에 따른 반도체 소자의 커패시터 제조 방법은 다음과 같은 효과가 있다.Such a capacitor manufacturing method of a semiconductor device according to the present invention has the following effects.
하부전극 Ru 증착을 PECVD법과 LPCVD법 2 스텝으로 진행하여 In-Situ로 진행하므로 Ru 증착시 증착율을 증가시킬 수 있다.Since the lower electrode Ru deposition proceeds to In-Situ by PECVD and LPCVD in two steps, the deposition rate may be increased during Ru deposition.
또한, Ru 막질을 개선시키므로 TiON 커패시터의 높은 정전 용량과 낮은 누설전류를 동시에 확보할 수 있다.In addition, since the Ru film quality is improved, high capacitance and low leakage current of the TiON capacitor can be secured at the same time.
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