KR100422596B1 - Method for fabricating capacitor - Google Patents
Method for fabricating capacitor Download PDFInfo
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- KR100422596B1 KR100422596B1 KR10-2001-0038870A KR20010038870A KR100422596B1 KR 100422596 B1 KR100422596 B1 KR 100422596B1 KR 20010038870 A KR20010038870 A KR 20010038870A KR 100422596 B1 KR100422596 B1 KR 100422596B1
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- capacitor
- oxide film
- film
- heat treatment
- lower electrode
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- 239000003990 capacitor Substances 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 29
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 9
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 35
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 239000011229 interlayer Substances 0.000 claims description 18
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 14
- 239000010410 layer Substances 0.000 claims description 12
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 8
- 230000008021 deposition Effects 0.000 abstract description 12
- 239000007769 metal material Substances 0.000 abstract description 5
- 238000003860 storage Methods 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 25
- 229910052707 ruthenium Inorganic materials 0.000 description 25
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 17
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 12
- 229910008484 TiSi Inorganic materials 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 239000010936 titanium Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 229910052786 argon Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 5
- 229910001882 dioxygen Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000007669 thermal treatment Methods 0.000 description 5
- 206010021143 Hypoxia Diseases 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- YDKGTAIMRZEYGE-UHFFFAOYSA-N [CH2]C[Ta] Chemical group [CH2]C[Ta] YDKGTAIMRZEYGE-UHFFFAOYSA-N 0.000 description 3
- 238000011534 incubation Methods 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910008482 TiSiN Inorganic materials 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 239000006200 vaporizer Substances 0.000 description 2
- OXJUCLBTTSNHOF-UHFFFAOYSA-N 5-ethylcyclopenta-1,3-diene;ruthenium(2+) Chemical compound [Ru+2].CC[C-]1C=CC=C1.CC[C-]1C=CC=C1 OXJUCLBTTSNHOF-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 239000007983 Tris buffer Substances 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- LENZDBCJOHFCAS-UHFFFAOYSA-N tris Chemical compound OCC(N)(CO)CO LENZDBCJOHFCAS-UHFFFAOYSA-N 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
- H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 산화막과 스토리지노드콘택홀내 금속물질(확산방지막)에서의 증착률 차이에 따른 금속 하부전극의 단차피복성 불량을 방지하도록 한 캐패시터의 제조 방법을 제공하기 위한 것으로, 반도체 기판 상에 금속으로 이루어진 확산방지막을 형성하는 단계, 상기 확산방지막을 포함한 상기 반도체 기판 상에 캐패시터산화막을 형성하는 단계, 상기 캐패시터산화막을 선택적으로 식각하여 상기 확산방지막의 표면을 노출시키는 오목부를 형성하는 단계, 상기 오목부가 형성된 상기 캐패시터산화막의 표면을 개질시키기 위해 암모니아 분위기에서 열처리하는 단계, 상기 표면이 개질된 캐패시터산화막을 포함한 전면에 금속 하부전극을 증착하는 단계, 상기 금속 하부전극을 상기 오목부내에만 잔류시키는 단계, 및 상기 잔류하는 금속 하부전극 상에 유전막, 상부전극을 순차적으로 형성하는 단계를 포함하여 이루어진다.The present invention is to provide a method of manufacturing a capacitor to prevent the step coverage defect of the lower metal electrode due to the difference in deposition rate in the oxide film and the metal material (anti-diffusion film) in the storage node contact hole. Forming a diffusion barrier layer, forming a capacitor oxide layer on the semiconductor substrate including the diffusion barrier layer, selectively etching the capacitor oxide layer to form a recess to expose a surface of the diffusion barrier layer, the recess portion Heat treatment in an ammonia atmosphere to modify the surface of the formed capacitor oxide film, depositing a metal lower electrode on the front surface including the modified capacitor oxide film, leaving the metal lower electrode only in the recess, and On the remaining metal lower electrode It comprises the step of forming a dielectric film, an upper electrode in order.
Description
본 발명은 반도체소자의 캐패시터 제조 방법에 관한 것으로, 특히 MIM 구조의 탄탈륨산화막을 이용한 캐패시터의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor using a tantalum oxide film having a MIM structure.
반도체 소자가 고집적화됨에 따라 충분한 정전용량을 확보하기 위해 캐패시터의 구조를 실린더(Cylinder), 핀(Pin), 적층(Stack) 또는 반구형 실리콘(HSG) 등의 복잡한 구조로 형성하여 전하저장 면적을 증가시키거나, SiO2나 Si3N4에 비해 유전상수가 큰 Ta2O5, TiO2, SrTiO3, (Ba,Sr)TiO등의 고유전물질에 대한 연구가 활발히 진행되고 있다.As semiconductor devices are highly integrated, the capacitor structure is formed into a complex structure such as cylinder, pin, stack, or hemispherical silicon (HSG) to secure sufficient capacitance, thereby increasing the charge storage area. In addition, studies on high dielectric materials such as Ta 2 O 5 , TiO 2 , SrTiO 3 , and (Ba, Sr) TiO, which have a higher dielectric constant than SiO 2 or Si 3 N 4 , are being actively conducted.
특히, 저압화학적기상증착법(Low Pressure Chemical Vapor Deposition; LPCVD)을 이용한 탄탈륨산화막(Ta2O5)은 비교적 유전율이 높아 적용 가능성이 높은 것으로 알려졌다.In particular, a tantalum oxide film (Ta 2 O 5 ) using Low Pressure Chemical Vapor Deposition (LPCVD) has a relatively high dielectric constant and is known to have high applicability.
최근에, 소자의 집적화에 의해 소자 크기가 감소함에 따라 유효산화막두께의 감소가 요구되며, 보다 신뢰성있는 소자를 제조하기 위해서는 바이어스전압(Bias voltage)에 따른 ΔC의 감소 및 누설전류와 같은 전기적 특성을 개선시키는 것이 필요하다.Recently, as the device size decreases due to the integration of devices, the effective oxide film thickness is required to be reduced, and in order to manufacture a more reliable device, electrical characteristics such as a decrease in ΔC and a leakage current according to a bias voltage are required. It is necessary to improve.
이러한 특성 개선을 위해서 통상 폴리실리콘대신 금속막을 상하부전극으로 이용하는 MIM(Metal-Insulator-Metal) 캐패시터가 연구되고 있으며, MIM 캐패시터제조시 캐패시터의 유효산화막두께(Tox), 누설전류 특성이 개선된 신뢰성 있는 소자를 제조하기 위해서는 양질의 캐패시터 유전막을 증착하는 공정이 매우 중요하다 할 것이다.MIM using a metal film instead of the conventional polysilicon to these characteristics improve the upper and lower electrodes (Metal-Insulator-Metal) capacitor is researched and which, MIM capacitors effective oxide thickness for the manufacture of a capacitor (T ox), the leakage current a characteristic to improve reliability The process of depositing a high quality capacitor dielectric film will be very important to fabricate the device.
특히, 탄탈륨산화막을 유전막으로 이용하는 MIM 캐패시터 제조시, 금속전극의 배향성에 따라 탄탈륨산화막이 방향성을 나타내어 유전상수가 증가하며, 금속전극은 폴리실리콘과의 전기적 에너지장벽(Energy barrier)(또는 일함수)이 크므로 유효산화막두께(Tox)를 감소시킬 수 있어 동일한 유효산화막 두께에서의 누설전류를 감소시키는 장점이 있다.In particular, when manufacturing a MIM capacitor using a tantalum oxide film as a dielectric film, the tantalum oxide film has a directionality according to the orientation of the metal electrode, and the dielectric constant increases, and the metal electrode has an electrical energy barrier (or work function) with polysilicon. Since the effective oxide film thickness (T ox ) can be reduced because of this large, there is an advantage of reducing the leakage current at the same effective oxide film thickness.
도 1은 종래기술에 따라 제조된 MIM구조의 탄탈륨산화막 캐패시터를 도시한 도면이다.1 is a view showing a tantalum oxide film capacitor of the MIM structure manufactured according to the prior art.
도 1을 참조하면, 소스/드레인(12)을 포함한 트랜지스터 제조 공정이 완료된 반도체기판(11)상에 층간절연막(Inter Layer Dielectric; ILD)(13)을 형성한 다음, 층간절연막(13)을 선택적으로 식각하여 소스/드레인(12)의 소정 부분이 노출되는 콘택홀을 형성한다.Referring to FIG. 1, an interlayer dielectric (ILD) 13 is formed on a semiconductor substrate 11 on which a transistor manufacturing process including a source / drain 12 is completed, and then an interlayer dielectric 13 is selectively selected. Etching to form a contact hole through which a predetermined portion of the source / drain 12 is exposed.
계속해서, 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후, 에치백(Etch back)공정으로 소정 깊이만큼 리세스시켜 콘택홀의 소정 부분에 매립되는 폴리실리콘플러그(14)를 형성한 다음, 폴리실리콘플러그(14)상에 티타늄실리사이드(이하 'TiSi2'라 약칭함)(15)와 티타늄나이트라이드(이하 'TiN'이라 약칭함)(16)의 적층막을 형성한다.Subsequently, after the polysilicon is formed on the entire surface including the contact hole, the polysilicon plug 14 embedded in the predetermined part of the contact hole is formed by recessing the substrate to a predetermined depth by an etch back process, and then polysilicon. On the plug 14, a laminated film of titanium silicide (hereinafter referred to as 'TiSi 2 ') 15 and titanium nitride (hereinafter referred to as 'TiN') 16 is formed.
이 때, TiSi2(15)는 폴리실리콘플러그(14)와 후속 하부전극과의 오믹 콘택(Ohmic contact)을 형성해 주고, TiN(16)는 후속 탄탈륨산화막의 열처리공정시 하부전극내에 잔존하는 산소가 폴리실리콘플러그(14) 또는 반도체기판(11)으로 확산하는 것을 방지하는 확산방지막의 역할을 한다.At this time, TiSi 2 (15) forms an ohmic contact between the polysilicon plug (14) and the subsequent lower electrode, and TiN (16) forms oxygen remaining in the lower electrode during the subsequent heat treatment of the tantalum oxide film. It serves as a diffusion barrier that prevents diffusion into the polysilicon plug 14 or the semiconductor substrate 11.
다음으로, TiN(16)를 포함한 층간절연막(13)상에 질화물계 식각정지막(17)과 캐패시터산화막(18)을 형성한 후, 스토리지노드마스크로 캐패시터산화막(18)과 식각정지막(17)을 순차적으로 식각하여 폴리실리콘플러그(14)에 정렬되는 오목부를 형성한다.Next, after forming the nitride-based etch stop film 17 and the capacitor oxide film 18 on the interlayer insulating film 13 including TiN (16), the capacitor oxide film 18 and the etch stop film 17 as a storage node mask. ) Are sequentially etched to form recesses aligned with the polysilicon plug 14.
계속해서, 오목부가 형성된 캐패시터산화막(18)의 표면을 따라루테늄막을 증착한 다음, 에치백 또는 화학적기계적연마를 통해 오목부내에만 루테늄막을 잔류시켜 이웃한 셀간 서로 격리되는 루테늄-하부전극(19)을 형성한다.Subsequently, a ruthenium film is deposited along the surface of the capacitor oxide film 18 in which the recess is formed, and then the ruthenium lower electrode 19 is isolated from each other between neighboring cells by leaving the ruthenium film only in the recess through etch back or chemical mechanical polishing. Form.
계속해서, 루테늄-하부전극(19)을 포함한 전면에 탄탈륨산화막(21)을 증착한 후, 산소결핍을 제거하기 위한 열처리와 탄탈륨산화막(21)내 잔류하는 불순물을 제거하기 위한 열처리를 순차적으로 진행한다.Subsequently, after the tantalum oxide film 21 is deposited on the entire surface including the ruthenium-lower electrode 19, a heat treatment for removing oxygen deficiency and a heat treatment for removing impurities remaining in the tantalum oxide film 21 are sequentially performed. do.
다음으로, 탄탈륨산화막(21)상에 상부전극(22)으로서 CVD에 의한 티타늄나이트라이드(이하 'CVD-TiN'이라 약칭함) 또는 루테늄막을 증착한다.Next, a titanium nitride (hereinafter abbreviated as 'CVD-TiN') or ruthenium film by CVD is deposited as the upper electrode 22 on the tantalum oxide film 21.
그러나, 종래기술은 루테늄막과 같은 금속으로 이루어진 하부전극이 대부분 캐패시터산화막과 금속물질(예컨대, TiN)에 증착되므로, 하부전극 증착시 산화막과 금속물질에서의 증착률이 큰 차이가 나면 우수한 단차피복성을 확보하기 어렵다.However, in the prior art, since a lower electrode made of a metal such as a ruthenium film is mostly deposited on a capacitor oxide film and a metal material (for example, TiN), an excellent step difference coating is obtained when the deposition rate of the oxide film and the metal material is different when the bottom electrode is deposited. It is difficult to secure the castle.
일반적으로 동일 물질을 여러 기판에 증착하는 경우, 하부기판 물질에 따라 인큐베이션시간(Incubation time)이 차이가 나고 증착속도도 차이가 난다. 전술한 종래기술에서 적용된 바와 같이, 루테늄막을 산화막 및 TiN과 같은 금속물질에 증착하는 경우 TiN에서의 인큐베이션시간이 산화막에서의 인큐베이션시간보다 증가하여 TiN에서의 증착속도가 느리다.In general, when the same material is deposited on multiple substrates, the incubation time is different and the deposition rate is different according to the lower substrate material. As applied in the above-mentioned prior art, when the ruthenium film is deposited on an oxide film and a metal material such as TiN, the incubation time in TiN is increased than the incubation time in the oxide film, so that the deposition rate in TiN is slow.
이 경우, 실제 캐패시터 구조에서는 바닥부분(TiN에 접하는 부분)에서의 금속전극 물질의 증착 두께가 상대적으로 작아지므로 단차피복성 특성의 개선이 필요하다.In this case, in the actual capacitor structure, the deposition thickness of the metal electrode material at the bottom portion (the portion in contact with TiN) becomes relatively small, and therefore, it is necessary to improve the step coating property.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 산화막과 금속물질에서의 증착률 차이에 따른 금속 하부전극의 단차피복성 불량을 방지하는데 적합한 캐패시터의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, the object of the present invention is to provide a method of manufacturing a capacitor suitable for preventing the step coverage defect of the metal lower electrode according to the deposition rate difference in the oxide film and the metal material. have.
도 1은 종래기술에 따라 제조된 MIM 구조의 탄탈륨산화막 캐패시터를 도시한 도면,1 is a view showing a tantalum oxide capacitor of the MIM structure manufactured according to the prior art,
도 2a 내지 도 2c는 본 발명의 실시예에 따른 MIM 구조의 탄탈륨산화막 캐패시터의 제조 방법을 도시한 공정 단면도,2A to 2C are cross-sectional views illustrating a method of manufacturing a tantalum oxide film capacitor having a MIM structure according to an embodiment of the present invention;
도 3a 내지 도 3c는 본 발명의 제2실시예에 따른 MIM 구조의 탄탈륨산화막 캐패시터의 제조 방법을 도시한 공정 단면도.3A to 3C are cross-sectional views illustrating a method of manufacturing a tantalum oxide film capacitor having a MIM structure according to a second embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 34 : 폴리실리콘플러그31 semiconductor substrate 34 polysilicon plug
35 : TiSi236 : TiN35: TiSi 2 36: TiN
38 : 캐패시터산화막 39 : SiON38: capacitor oxide film 39: SiON
40 : 루테늄-하부전극 41 : 탄탈륨산화막40: ruthenium-lower electrode 41: tantalum oxide film
42 : 상부전극42: upper electrode
상기의 목적을 달성하기 위한 본 발명의 캐패시터의 제조 방법은 반도체 기판 상에 금속으로 이루어진 확산방지막을 형성하는 단계, 상기 확산방지막을 포함한 상기 반도체 기판 상에 캐패시터산화막을 형성하는 단계, 상기 캐패시터산화막을 선택적으로 식각하여 상기 확산방지막의 표면을 노출시키는 오목부를 형성하는 단계, 상기 오목부가 형성된 상기 캐패시터산화막의 표면을 개질시키기 위해 암모니아 분위기에서 열처리하는 단계, 상기 표면이 개질된 캐패시터산화막을 포함한 전면에 금속 하부전극을 증착하는 단계, 상기 금속 하부전극을 상기 오목부내에만 잔류시키는 단계, 및 상기 잔류하는 금속 하부전극 상에 유전막, 상부전극을 순차적으로 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The method of manufacturing a capacitor of the present invention for achieving the above object comprises the steps of forming a diffusion barrier film made of a metal on the semiconductor substrate, forming a capacitor oxide film on the semiconductor substrate including the diffusion barrier film, the capacitor oxide film Selectively etching to form a recess exposing the surface of the diffusion barrier, heat treating in an ammonia atmosphere to modify the surface of the capacitor oxide film on which the recess is formed, and metal on the front surface including the capacitor oxide film having the surface modified And depositing a lower electrode, remaining the metal lower electrode only in the concave portion, and sequentially forming a dielectric film and an upper electrode on the remaining metal lower electrode.
또한, 본 발명의 캐패시터의 제조 방법은 반도체기판상에 층간절연막을 형성하는 단계, 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀에 폴리실리콘플러그를 부분 매립시키는 단계, 상기 부분 매립된 폴리실리콘플러그상에 상기 콘택홀을 완전히 매립시키도록 티타늄실리사이드를 형성하는 단계, 상기 티타늄실리사이드를 포함한 층간절연막상에 캐패시터산화막을 형성하는 단계, 상기 캐패시터산화막을 선택적으로 식각하여 상기 폴리실리콘플러그에 정렬되는 오목부를 형성하는 단계, 상기 오목부에 의해 노출된 상기 티타늄실리사이드와 상기 캐패시터산화막의 표면을 암모니아 분위기에서 개질시키는 단계, 및 상기 개질된 캐패시터산화막을 포함한 전면에 금속 하부전극을 증착하는 단계를 포함하여 이루어짐을 특징으로 한다.In addition, the method of manufacturing a capacitor of the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate, selectively etching the interlayer insulating film to form a contact hole, partially embedding a polysilicon plug in the contact hole, the Forming titanium silicide to completely fill the contact hole on the partially buried polysilicon plug, forming a capacitor oxide film on the interlayer insulating film including the titanium silicide, and selectively etching the capacitor oxide film to etch the polysilicon. Forming a recess aligned with the plug, modifying a surface of the titanium silicide and the capacitor oxide film exposed by the recess in an ammonia atmosphere, and depositing a metal lower electrode on the front surface including the modified capacitor oxide film Made up of steps It characterized.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2c는 본 발명의 제 1 실시예에 따른 MIM 구조의 탄탈륨산화막 캐패시터의 제조 방법을 도시한 공정 단면도로서, 캐패시터의 유전막으로 탄탈륨산화막을 이용하고, 하부전극으로 루테늄막을, 상부전극으로 TiN 또는 루테늄막을 이용한 경우를 도시하고 있다.2A to 2C are cross-sectional views illustrating a method of manufacturing a tantalum oxide film capacitor having a MIM structure according to a first embodiment of the present invention, wherein a tantalum oxide film is used as a dielectric film of a capacitor, and a ruthenium film is used as a lower electrode and an upper electrode. The case where TiN or ruthenium film is used is shown.
도 2a에 도시된 바와 같이, 소스/드레인(32)을 포함한 트랜지스터 제조 공정이 완료된 반도체기판(31)상에 층간절연막(ILD)(33)을 형성한다.As shown in FIG. 2A, an interlayer insulating film (ILD) 33 is formed on the semiconductor substrate 31 on which the transistor manufacturing process including the source / drain 32 is completed.
그리고, 층간절연막(33)상에 통상의 노광 및 현상을 통해 콘택마스크를 형성한 후, 콘택마스크로 층간절연막(33)을 식각하여 소스/드레인(32)의 소정 부분이 노출되는 콘택홀을 형성하고, 콘택마스크를 제거한다.After forming a contact mask on the interlayer insulating layer 33 through normal exposure and development, the interlayer insulating layer 33 is etched using the contact mask to form a contact hole through which a predetermined portion of the source / drain 32 is exposed. And remove the contact mask.
계속해서, 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후, 에치백공정으로 소정 깊이만큼 리세스시켜 콘택홀의 소정 부분에 매립되는 폴리실리콘플러그(34)를 형성한다.Subsequently, after the polysilicon is formed on the entire surface including the contact hole, the polysilicon plug 34 embedded in the predetermined portion of the contact hole is formed by recessing it by a predetermined depth by an etch back process.
그리고, 전면에 티타늄(Ti)을 증착한 후, 급속열처리(RTP)하여 폴리실리콘 플러그(34)의 실리콘(Si) 원자와 티타늄(Ti)의 반응을 유발시켜 폴리실리콘플러그 (34)상에 TiSi2(35)를 형성한다. 이 때, TiSi2(35)는 폴리실리콘플러그(34)와 후속 하부전극과의 접촉저항을 개선시키기 위한 오믹 콘택층이다.After depositing titanium (Ti) on the front surface, rapid thermal treatment (RTP) causes a reaction between silicon (Si) atoms of the polysilicon plug 34 and titanium (Ti) to cause TiSi on the polysilicon plug 34. 2 (35) forms. At this time, TiSi 2 35 is an ohmic contact layer for improving the contact resistance between the polysilicon plug 34 and the subsequent lower electrode.
계속해서, TiSi2(35)상에 TiN(36)를 형성한 후, 층간절연막(33)의 표면이 노출될때까지 TiN(36)를 화학적기계적연마(CMP) 또는 에치백하여 콘택홀내에 매립시킨다.Subsequently, after the TiN 36 is formed on the TiSi 2 35, the TiN 36 is buried in the contact hole by chemical mechanical polishing (CMP) or etching back until the surface of the interlayer insulating film 33 is exposed. .
여기서, TiN(36)는 후속 탄탈륨산화막의 열처리공정시 하부전극내에 잔존하는 산소가 폴리실리콘플러그(34) 또는 반도체기판(31)으로 확산하는 것을 방지하는 확산방지막의 역할을 한다.Here, the TiN 36 serves as a diffusion barrier that prevents oxygen remaining in the lower electrode from diffusing into the polysilicon plug 34 or the semiconductor substrate 31 during the subsequent heat treatment of the tantalum oxide film.
도 2b에 도시된 바와 같이, TiN(36)를 포함한 층간절연막(33)상에 질화물계 식각정지막(37)과 캐패시터산화막(38)을 형성한 후, 스토리지노드마스크로 캐패시터산화막(38)과 식각정지막(37)을 순차적으로 식각하여 폴리실리콘플러그(34)에 정렬되는 하부전극이 형성될 영역(이하 '오목부'라 약칭함)를 오픈시킨다.As shown in FIG. 2B, after the nitride-based etch stop film 37 and the capacitor oxide film 38 are formed on the interlayer insulating film 33 including TiN 36, the capacitor oxide film 38 is formed as a storage node mask. The etch stop layer 37 is sequentially etched to open a region (hereinafter, abbreviated as “concave portion”) in which a lower electrode aligned with the polysilicon plug 34 will be formed.
다음으로, 암모니아(NH3) 분위기로 급속열처리(Rapid Thermal Process; RTP) 또는 플라즈마 열처리(Plasma anneal)를 실시하여 오목부가 형성된 캐패시터 산화막(38)의 표면을 SiON(39)으로 개질시킨다.Next, a rapid thermal process (RTP) or plasma heat treatment (Plasma anneal) is performed in an ammonia (NH 3 ) atmosphere to modify the surface of the capacitor oxide film 38 having the concave portion formed with the SiON 39.
이 때, 급속열처리의 경우 500℃∼800℃에서 20초∼120초동안 실시하고, 플라즈마열처리의 경우 300℃∼700℃에서 20초∼120초동안 200W∼1000W의 파워로 실시한다.In this case, the rapid heat treatment is performed at 500 ° C. to 800 ° C. for 20 seconds to 120 seconds, and the plasma heat treatment is performed at 300 ° C. to 700 ° C. for 20 seconds to 120 seconds at a power of 200 W to 1000 W.
다음으로, 그 표면이 SiON(39)로 개질된 캐패시터산화막 (38)의 표면을 따라 저압화학기상증착법(LPCVD)을 이용하여 루테늄막, 예컨대 루테늄-하부전극(40)을 증착한다.Next, a ruthenium film, such as ruthenium-lower electrode 40, is deposited using low pressure chemical vapor deposition (LPCVD) along the surface of the capacitor oxide film 38 whose surface is modified with SiON 39.
상기한 루테늄-하부전극(40)의 저압화학기상증착법에 대해 설명하면 다음과같으며, 루테늄-하부전극(40)을 루테늄막으로 약칭하여 설명한다.The low pressure chemical vapor deposition method of the ruthenium-lower electrode 40 is as follows. The ruthenium-lower electrode 40 is abbreviated as a ruthenium film.
먼저, 루테늄막의 소스(source) 물질로는 최근에 주로 이용되며 경제적으로 저렴한 Ru(od)3[Ru(CH3COCHCOCH2CH2CH2CH3)3), Tris(2,4-octanedionato)ruthenium] 또는 Ru(EtCp)2[Ru(C2H5C5H4)2, Bis(ethylcyclopentadienyl)ruthenium] 중 어느 하나를 사용하고, 기화기(Vaporizer)를 이용하여 소스 물질을 기상상태로 만든다.First, ru (od) 3 [Ru (CH 3 COCHCOCH 2 CH 2 CH 2 CH 3 ) 3 ), Tris (2,4-octanedionato) ] Or Ru (EtCp) 2 [Ru (C 2 H 5 C 5 H 4 ) 2 , Bis (ethylcyclopentadienyl) ruthenium], and vaporize the source material using a vaporizer.
이처럼 기상의 루테늄 소스물질을 반응챔버내로 플로우시키기 위해 아르곤가스를 운반가스(carrier gas)로 이용하며, 이 때 아르곤 가스의 유량은 50sccm∼200sccm을 유지한다.As such, argon gas is used as a carrier gas to flow the ruthenium source material into the reaction chamber, and the flow rate of argon gas is maintained at 50 sccm to 200 sccm.
다음으로, 반응챔버내에 반응가스인 산소가스를 플로우시켜 루테늄 소스물질을 열분해시키므로써 순수한 루테늄막만을 증착시킨다.Next, only the pure ruthenium film is deposited by pyrolysing the ruthenium source material by flowing oxygen gas which is a reaction gas into the reaction chamber.
이 때, 산소가스의 유량은 50sccm∼400sccm을 유지하며, 반응챔버의 압력은 0.1torr∼10torr를 유지하고, 루테늄막이 증착되는 기판은 230℃∼350℃를 유지한다.At this time, the flow rate of the oxygen gas is maintained at 50sccm to 400sccm, the pressure of the reaction chamber is maintained at 0.1torr to 10torr, and the substrate on which the ruthenium film is deposited is maintained at 230 ° C to 350 ° C.
다음으로, 산소가스 및 반응부산물을 제거하기 위해 희석가스로서 아르곤을 플로우시키는데, 이 때 아르곤가스의 유량은 400℃∼800℃를 유지한다.Next, argon is flowed as a diluent gas to remove oxygen gas and reaction byproducts, and the flow rate of argon gas is maintained at 400 ° C to 800 ° C.
이와 같은 저압화학기상증착에 의해 100Å∼300Å의 두께를 갖는 루테늄막(39)을 증착시킨다.By such low pressure chemical vapor deposition, a ruthenium film 39 having a thickness of 100 kPa to 300 kPa is deposited.
상술한 루테늄막 증착시, 캐패시터산화막(38) 표면을 SiON(39)로 개질시킨 상태이므로, TiN(36)과 SiON(39)에서의 루테늄막의 증착속도 차이를 감소시킬 수 있다.In the ruthenium film deposition described above, since the surface of the capacitor oxide film 38 is modified with the SiON 39, the difference in deposition rate of the ruthenium film between the TiN 36 and the SiON 39 can be reduced.
즉, SiON(39)에서 루테늄막의 증착속도가 감소되므로 루테늄막의 단차피복성이 우수하다.That is, since the deposition rate of the ruthenium film is reduced in the SiON 39, the step coverage of the ruthenium film is excellent.
다음으로, 에치백 또는 화학적기계적연마를 통해 오목부내에만 루테늄-하부전극(40)를 잔류시킨다. 즉, 이웃한 셀간 서로 격리되는 루테늄-하부전극(40)을 형성한다.Next, the ruthenium-lower electrode 40 remains only in the recess through etch back or chemical mechanical polishing. That is, the ruthenium-lower electrode 40 is isolated from neighboring cells.
도 2c에 도시된 바와 같이, 루테늄-하부전극(40)을 포함한 전면에 탄탈륨산화막(41)을 저압화학기상증착법으로 증착한다.As illustrated in FIG. 2C, a tantalum oxide film 41 is deposited on the entire surface including the ruthenium-lower electrode 40 by low pressure chemical vapor deposition.
탄탈륨산화막(41)의 저압화학기상증착법에 대해 설명하면 다음과 같다.The low pressure chemical vapor deposition method of the tantalum oxide film 41 is described as follows.
먼저 반응챔버내에 원료물질로서 탄탈륨에칠레이트[Ta(OC2H5)5]를 운반가스인 질소(N2)를 통해 플로우시킨다. 이 때, 질소의 유량은 350sccm∼450sccm을 유지한다.First, tantalum ethylene [Ta (OC 2 H 5 ) 5 ] is flowed through nitrogen (N 2 ), which is a carrier gas, as a raw material in the reaction chamber. At this time, the flow rate of nitrogen is maintained at 350 sccm to 450 sccm.
그리고, 반응챔버내에 반응가스(또는 산화제)로서 산소를 20sccm∼50sccm의 유량으로 플로우시킨 후, 300℃∼450℃의 온도로 가열된 기판상에서 공급된 탄탈륨에칠레이트를 열분해시켜 기판상에 탄탈륨산화막을 증착한다. 이 때, 반응챔버는 0.1torr∼2torr의 압력을 유지한다.Then, oxygen is flowed into the reaction chamber as a reaction gas (or an oxidant) at a flow rate of 20 sccm to 50 sccm, and then a tantalum oxide film is thermally decomposed on the substrate to be thermally decomposed on the substrate heated at a temperature of 300 ° C to 450 ° C. Deposit. At this time, the reaction chamber maintains a pressure of 0.1torr to 2torr.
한편, 탄탈륨산화막을 형성하기 위한 소스로 널리 사용되는 탄탈륨에칠레이트는 실온에서 액체 상태이며, 145℃ 온도에서 기화하는 특성을 가지고 있으므로, 탄탈륨에칠레이트를 용이하게 반응시키기 위하여 액상인 소스를 기상으로 만들어야 한다. 예컨대, 탄탈륨에칠레이트를 170℃∼190℃로 유지되는 기화기에서 기상상태로 변화시킨 후, 질소가스에 실어 반응챔버내로 공급시킨다.On the other hand, since tantalum ethylene is widely used as a source for forming a tantalum oxide film, it is liquid at room temperature and has a property of vaporizing at 145 ° C. Should be made. For example, tantalum ethylene is changed into a gaseous state in a vaporizer maintained at 170 ° C to 190 ° C, and then loaded into nitrogen gas and supplied into the reaction chamber.
상기한 바와 같이 탄탈륨산화막(41)을 증착한 후, 탄탈륨산화막(41)내 산소 공공을 제거하기 위해 저온에서 플라즈마 열처리 또는 UV/O3열처리를 실시한다.As described above, after the tantalum oxide film 41 is deposited, plasma heat treatment or UV / O 3 heat treatment is performed at low temperature to remove oxygen vacancies in the tantalum oxide film 41.
이 때, 플라즈마열처리는 산소(O2), N2O 또는 N2+O2의 혼합 가스분위기에서 300℃∼500℃의 온도로 30초∼120초동안 200W∼500W의 파워로 진행된다.At this time, the plasma heat treatment proceeds at a power of 200W to 500W for 30 seconds to 120 seconds at a temperature of 300 ° C to 500 ° C in a mixed gas atmosphere of oxygen (O 2 ), N 2 O or N 2 + O 2 .
그리고, UV/O3열처리는 300℃∼500℃의 온도로 2분∼10분동안 램프의 강도를 15㎽/cm2∼30㎽/cm2로 유지하면서 진행된다.And, UV / O 3 thermal treatment is conducted while maintaining the strength of the lamp during 2-10 minutes at a temperature of 300 ℃ ~500 ℃ to 15㎽ / cm 2 ~30㎽ / cm 2 .
이와 같이, 탄탈륨산화막(41)을 저온(300℃∼500℃)에서 플라즈마열처리하거나 또는 UV/O3열처리하면, 탄탈륨산화막(41)내 산소결핍을 충분히 제거할 수 있다.As described above, when the tantalum oxide film 41 is subjected to plasma heat treatment or UV / O 3 heat treatment at low temperature (300 ° C. to 500 ° C.), oxygen deficiency in the tantalum oxide film 41 can be sufficiently removed.
다음으로, 탄탈륨산화막(41)내 산소결핍을 제거한 후, 유전특성을 얻기 위해 고온에서 급속열처리(RTP) 또는 노열처리(Furnace anneal)를 실시한다.Next, after the oxygen deficiency in the tantalum oxide film 41 is removed, rapid thermal treatment (RTP) or furnace anneal is performed at high temperature to obtain dielectric properties.
이 때, 급속열처리는 질소(N2), 아르곤(Ar) 또는 헬륨(He) 중 어느 하나의 비활성가스와 산소가스의 혼합 가스분위기에서 500℃∼650℃의 온도로 30초∼60초 동안 진행된다.At this time, rapid heat treatment is performed for 30 seconds to 60 seconds at a temperature of 500 ° C to 650 ° C in a mixed gas atmosphere of nitrogen (N 2 ), argon (Ar) or helium (He) in an inert gas and oxygen gas. do.
그리고, 노열처리는 질소(N2), 아르곤(Ar) 또는 헬륨(He) 중 어느 하나의 비활성가스와 산소가스의 혼합 분위기에서 500℃∼600℃의 온도로 10분∼30분동안 진행된다.The heat treatment is performed for 10 minutes to 30 minutes at a temperature of 500 ° C to 600 ° C in a mixed atmosphere of inert gas and oxygen gas of nitrogen (N 2 ), argon (Ar) or helium (He).
상기한 급속열처리 및 노열처리 공정시, 산소와 비활성가스의 혼합비는 1:10∼10:10으로 유지한다.In the rapid heat treatment and furnace treatment processes, the mixing ratio of oxygen and inert gas is maintained at 1:10 to 10:10.
이와 같이, 탄탈륨산화막(41)내 산소결핍을 제거한 후, 고온(500℃∼700℃)에서 열처리를 실시하면, 탄탈륨산화막(41)내에 잔류하는 탄소, 수소 등의 불순물을 제거할 수 있다.In this manner, after the oxygen deficiency in the tantalum oxide film 41 is removed, heat treatment is performed at a high temperature (500 ° C to 700 ° C), whereby impurities such as carbon and hydrogen remaining in the tantalum oxide film 41 can be removed.
다음으로, 탄탈륨산화막(41)상에 상부전극(42)으로서 티타늄나이트라이드 또는 루테늄막을 증착한다.Next, a titanium nitride or ruthenium film is deposited on the tantalum oxide film 41 as the upper electrode 42.
도 3a 내지 도 3c는 본 발명의 제 2 실시예에 따른 캐패시터의 제조 방법을 도시한 공정 단면도이다.3A to 3C are cross-sectional views illustrating a method of manufacturing a capacitor according to a second embodiment of the present invention.
도 3a에 도시된 바와 같이, 소스/드레인(52)을 포함한 트랜지스터 제조 공정이 완료된 반도체기판(51)상에 층간절연막(ILD)(53)을 형성한 다음, 층간절연막(53)상에 통상의 노광 및 현상을 통해 콘택마스크를 형성한 후, 콘택마스크로 층간절연막(53)을 식각하여 소스/드레인(52)의 소정 부분이 노출되는 콘택홀을 형성하고, 콘택마스크를 제거한다.As shown in FIG. 3A, an interlayer insulating film (ILD) 53 is formed on a semiconductor substrate 51 on which a transistor manufacturing process including a source / drain 52 is completed, and then on a interlayer insulating film 53. After forming the contact mask through exposure and development, the interlayer insulating layer 53 is etched with the contact mask to form a contact hole through which a predetermined portion of the source / drain 52 is exposed, and the contact mask is removed.
계속해서, 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후, 에치백공정으로 소정 깊이만큼 리세스시켜 콘택홀의 소정 부분에 매립되는 폴리실리콘플러그(54)를 형성한다.Subsequently, after the polysilicon is formed on the entire surface including the contact hole, the polysilicon plug 54 embedded in the predetermined portion of the contact hole is formed by recessing it by a predetermined depth by an etch back process.
그리고, 전면에 티타늄(Ti)을 증착한 후, 급속열처리(RTP)하여 폴리실리콘 플러그(54)의 실리콘(Si) 원자와 티타늄(Ti)의 반응을 유발시켜 폴리실리콘플러그 (44)상에 TiSi2(55)를 형성한다. 이 때, TiSi2(55) 형성후 콘택홀이 완전히 매립된다.After depositing titanium (Ti) on the entire surface, rapid thermal treatment (RTP) causes a reaction between silicon (Si) atoms of the polysilicon plug 54 and titanium (Ti) to cause TiSi on the polysilicon plug 44. 2 to form 55. At this time, the contact hole is completely filled after the TiSi 2 55 is formed.
도 3b에 도시된 바와 같이, 층간절연막(53)상에 질화물계 식각정지막(56)과 캐패시터산화막(57)을 형성한 후, 스토리지노드마스크로 캐패시터산화막(57)과 식각정지막(56)을 순차적으로 식각하여 폴리실리콘플러그(54)에 정렬되는 오목부를 오픈시킨다.As shown in FIG. 3B, after the nitride-based etch stop layer 56 and the capacitor oxide layer 57 are formed on the interlayer insulating layer 53, the capacitor oxide layer 57 and the etch stop layer 56 are formed as storage node masks. Are sequentially etched to open the recesses aligned with the polysilicon plug 54.
다음으로, 암모니아(NH3) 분위기로 급속열처리(RTP) 또는 플라즈마 열처리를 실시하여 오목부가 형성된 캐패시터 산화막(57)의 표면을 SiON(58)으로 개질시킴과 동시에 TiSi2(55)를 TiSiN(59)으로 개질시킨다.Next, rapid thermal treatment (RTP) or plasma heat treatment is performed in an ammonia (NH 3 ) atmosphere to modify the surface of the capacitor oxide film 57 having the recesses formed with SiON 58, and at the same time, TiSi 2 (55) to TiSiN (59). ).
이 때, 급속열처리의 경우 500℃∼800℃에서 20초∼120초동안 실시하고, 플라즈마열처리의 경우 300℃∼700℃에서 20초∼120초동안 200W∼1000W의 파워로 실시한다.In this case, the rapid heat treatment is performed at 500 ° C. to 800 ° C. for 20 seconds to 120 seconds, and the plasma heat treatment is performed at 300 ° C. to 700 ° C. for 20 seconds to 120 seconds at a power of 200 W to 1000 W.
도 3c에 도시된 바와 같이, 그 표면이 SiON(58)로 개질된 캐패시터산화막 (57)의 표면을 따라 저압화학기상증착법(LPCVD)을 이용하여 루테늄막, 예컨대 루테늄-하부전극(60)을 증착한다. 이 때, 루테늄-하부전극(60)의 저압화학기상증착법은 본 발명의 제 1 실시예와 동일하며, 루테늄막 증착시 캐패시터산화막(57) 표면을 SiON(58)로 개질시킨 상태이므로, 루테늄막의 단차피복성이 우수하다.As shown in FIG. 3C, a ruthenium film such as ruthenium-lower electrode 60 is deposited using low pressure chemical vapor deposition (LPCVD) along the surface of the capacitor oxide film 57 whose surface is modified with SiON 58. do. At this time, the low pressure chemical vapor deposition method of the ruthenium-lower electrode 60 is the same as the first embodiment of the present invention, and since the surface of the capacitor oxide film 57 is modified with SiON 58 during the ruthenium film deposition, Excellent step coverage
다음으로, 에치백 또는 화학적기계적연마를 통해 오목부내에만 루테늄-하부전극(60)를 잔류시킨다. 즉, 이웃한 셀간 서로 격리되는 루테늄-하부전극(60)을 형성한다.Next, the ruthenium-lower electrode 60 remains only in the recess through etch back or chemical mechanical polishing. That is, the ruthenium-lower electrode 60 is formed to be isolated from the neighboring cells.
다음으로, 루테늄-하부전극(60)을 포함한 전면에 탄탈륨산화막(61)을 저압화학기상증착법으로 증착한다. 여기서, 탄탈륨산화막(61)의 저압화학기상증착법은 본 발명의 제 1 실시예와 동일하다.Next, a tantalum oxide film 61 is deposited on the entire surface including the ruthenium-lower electrode 60 by low pressure chemical vapor deposition. Here, the low pressure chemical vapor deposition method of the tantalum oxide film 61 is the same as in the first embodiment of the present invention.
다음으로, 탄탈륨산화막(61)상에 상부전극(62)으로서 티타늄나이트라이드 또는 루테늄막을 증착한다.Next, a titanium nitride or ruthenium film is deposited on the tantalum oxide film 61 as the upper electrode 62.
전술한 제 1 실시예와 제 2 실시예의 공정을 완료하면 오목(Concave) 구조의 캐패시터가 형성되며, 캐패시터산화막을 딥아웃(dip out)하여 실린더형(Cylinder) 캐패시터를 형성할 수도 있다.When the process of the first and second embodiments described above is completed, a capacitor having a concave structure is formed, and the capacitor oxide film may be diped out to form a cylindrical capacitor.
본 발명은 탄탈륨산화막을 유전막으로 이용하고, 상하부전극으로 금속을 이용하는 캐패시터에 적용가능하며, 아울러 BST[(BaxSr1-x)TiO3]와 같은 고유전체를 유전막으로 사용하는 모든 DRAM 및 PZT와 같은 강유전체를 유전막으로 사용하는 모든 강유전체 메모리(FeRAM)에 적용가능하다.The present invention is applicable to a capacitor using a tantalum oxide film as a dielectric film and a metal using an upper and lower electrode, and all DRAM and PZT using a high-k dielectric such as BST [(Ba x Sr 1-x ) TiO 3 ] as a dielectric film. It is applicable to all ferroelectric memories (FeRAM) using ferroelectrics as dielectric films.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 캐패시터산화막의 표면을 암모니아 처리하므로써 TiN과 캐패시터산화막에서의 루테늄막의 증착속도 차이를 감소시켜 하부전극인 루테늄막의 단차피복성을 확보할 수 있는 효과가 있다.The present invention as described above has the effect of reducing the difference in deposition rate of the ruthenium film in the TiN and the capacitor oxide film by ammonia treatment of the surface of the capacitor oxide film to ensure the step coverage of the ruthenium film as the lower electrode.
또한, 암모니아 플라즈마 처리 공정을 하부전극 증착챔버에서 진행할 수 있으므로 별도의 장비 투자없이 효과적으로 공정 진행이 가능한 효과가 있다.In addition, since the ammonia plasma treatment process can be performed in the lower electrode deposition chamber, the process can be effectively performed without additional equipment investment.
그리고, TiSi2만을 형성시킨 후 암모니아 처리하여 캐패시터산화막 표면을개질시킴과 동시에 TiSi2에 TiSiN을 형성시키므로써, 확산배리어막인 TiN 증착 공정을 생략할 수 있어 제조 공정을 단순화시킬 수 있는 효과가 있다.In addition, since only TiSi 2 is formed, the surface of the capacitor oxide film is modified by ammonia treatment, and TiSiN is formed on TiSi 2 , thereby the TiN deposition process, which is a diffusion barrier film, can be omitted, thereby simplifying the manufacturing process. .
Claims (5)
Priority Applications (1)
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| KR10-2001-0038870A KR100422596B1 (en) | 2001-06-30 | 2001-06-30 | Method for fabricating capacitor |
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| KR10-2001-0038870A KR100422596B1 (en) | 2001-06-30 | 2001-06-30 | Method for fabricating capacitor |
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| KR20030002129A KR20030002129A (en) | 2003-01-08 |
| KR100422596B1 true KR100422596B1 (en) | 2004-03-12 |
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| KR10-2001-0038870A KR100422596B1 (en) | 2001-06-30 | 2001-06-30 | Method for fabricating capacitor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100968425B1 (en) | 2007-06-27 | 2010-07-07 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040106950A (en) * | 2003-06-05 | 2004-12-20 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor memory device |
| KR20050011151A (en) | 2003-07-22 | 2005-01-29 | 삼성전자주식회사 | Methods of forming semiconductor device having a capacitor including electrodes comprising metal |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000038514A (en) * | 1998-12-08 | 2000-07-05 | 윤종용 | Method for manufacturing dram cell capacitor having improved leakage current feature |
| KR20000048374A (en) * | 1998-12-28 | 2000-07-25 | 마찌다 가쯔히꼬 | Method of fabricating semiconductor memory device |
| US6103567A (en) * | 1999-08-10 | 2000-08-15 | Vanguard International Semiconductor Corp. | Method of fabricating dielectric layer |
| JP2001196557A (en) * | 2000-01-13 | 2001-07-19 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
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2001
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000038514A (en) * | 1998-12-08 | 2000-07-05 | 윤종용 | Method for manufacturing dram cell capacitor having improved leakage current feature |
| KR20000048374A (en) * | 1998-12-28 | 2000-07-25 | 마찌다 가쯔히꼬 | Method of fabricating semiconductor memory device |
| US6103567A (en) * | 1999-08-10 | 2000-08-15 | Vanguard International Semiconductor Corp. | Method of fabricating dielectric layer |
| JP2001196557A (en) * | 2000-01-13 | 2001-07-19 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100968425B1 (en) | 2007-06-27 | 2010-07-07 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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| KR20030002129A (en) | 2003-01-08 |
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