KR100476374B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR100476374B1 KR100476374B1 KR10-2000-0082312A KR20000082312A KR100476374B1 KR 100476374 B1 KR100476374 B1 KR 100476374B1 KR 20000082312 A KR20000082312 A KR 20000082312A KR 100476374 B1 KR100476374 B1 KR 100476374B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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Abstract
본 발명은 오믹콘택층과 확산방지막의 계면 저항을 줄임으로써 하부전극의 콘택 저항을 줄여 캐패시터의 전기적 특성의 향상시키고 공정의 단순화를 기하는 반도체소자 제조 방법을 제공하기 위한 것으로서, 이를 위해 본 발명은 반도체소자 제조 방법에 있어서, 절연막을 선택적으로 식각하여 커패시터 콘택홀을 형성하고 상기 콘택홀 내부에 리세스된 플러그를 형성하는 제1단계; 상기 제1단계가 완료된 결과물 상에 Ti와 TiN를 증착하여 상기 콘택홀 내부에만 Ti/TiN 장벽층이 형성되도록 평탄화하는 제2단계; 상기 제2단계가 완료된 결과물 상에 저압 화학기상증착법으로 산소를 반응가스로 이용하여 Ru 소스가스를 분해하여 Ru를 증착함과 동시에 암모니아를 이용하여 상기 산소를 환원시켜 제거하며 Ru 하부전극을 형성하는 제3단계; 상기 제3단계가 완료된 결과물 상에 암모니아 분위기에서 급속열처리하는 제4단계; 상기 Ru 하부전극 상에 Ta2O5층을 증착 및 결정화하여 Ta2O5 유전막을 형성하는 제5단계; 및 상기 제5단계가 완료된 결과물 상에 상부전극을 형성하는 제6단계를 포함하여 이루어진다.The present invention is to provide a method for manufacturing a semiconductor device that reduces the contact resistance of the lower electrode by reducing the interface resistance of the ohmic contact layer and the diffusion barrier to improve the electrical characteristics of the capacitor and simplify the process. A method for manufacturing a semiconductor device, comprising: forming a capacitor contact hole by selectively etching an insulating film and forming a recessed plug in the contact hole; A second step of depositing Ti and TiN on the resultant product of which the first step is completed to planarize the Ti / TiN barrier layer to be formed only in the contact hole; Decomposition Ru source gas by using oxygen as a reaction gas on the resultant of the second step is completed by using a low pressure chemical vapor deposition method to deposit Ru and at the same time to reduce the oxygen by using ammonia to form a Ru bottom electrode The third step; A fourth step of rapid heat treatment in an ammonia atmosphere on the resultant of the third step; A fifth step of forming a Ta 2 O 5 dielectric layer by depositing and crystallizing the Ta 2 O 5 layer on the Ru lower electrode; And a sixth step of forming an upper electrode on the result of the fifth step.
Description
본 발명은 반도체소자 제조 방법에 관한 것으로, 더욱 상세하게는 Ru 하부전극을 갖는 MIM(Metal Insulator Metal) 구조의 캐패시터 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor having a metal insulator metal (MIM) structure having a Ru bottom electrode.
통상적으로 Ta2O5 캐패시터의 하부전극은 RTN(Rapid Thermal Nitrization) 표면처리된 폴리실리콘을 사용하였다.Typically, the lower electrode of the Ta 2 O 5 capacitor used a polysilicon surface treatment of rapid thermal nitrization (RTN).
한편, 소자가 점차 고 집적화됨에 따라 안정된 소자동작을 위한 셀당 캐패시턴스는 변화가 없는 반면 캐패시터 셀 사이즈는 점점 줄어들게 되어 유효산화막의 두께가 30Å 정도인 폴리실리콘을 하부전극으로 하는 Ta2O5 캐패시터 구조는 한계에 도달하게 되었다.On the other hand, as the device is increasingly integrated, the capacitance per cell for stable device operation does not change, but the capacitor cell size is gradually reduced, and the Ta 2 O 5 capacitor structure having polysilicon as the lower electrode having an effective oxide thickness of about 30Å is used. The limit has been reached.
이러한 문제를 해결하기 위해 Ru와 같은 메탈을 하부전극으로 도입해 유효산화막 두께를 낮추는 방법이 시도되었다. 이러한 Ru 하부전극의 도입은 플러그 물질인 폴리실리콘과 Ru 하부전극의 열반응 방지를 위한 장벽층 형성공정을 필요로 하게 된다. In order to solve this problem, a method of reducing the effective oxide thickness by introducing a metal such as Ru as a lower electrode has been attempted. The introduction of the Ru lower electrode requires a barrier layer forming process for preventing thermal reaction between the polysilicon, which is a plug material, and the Ru lower electrode.
그러나, 종래기술의 Ru를 하부전극물질로 하는 Ta2O5 캐패시터 제조 공정에서는 Ru를 증착 시 저압 화학기상증착법(Low Pressure Chemical Vapor Deposition; LPCVD)을 사용함으로서 Ru 박막 내에 존재하는 산소가 후속의 Ta2O5 유전막 증착 후, 열처리 공정 과정에서 TiN 등의 장벽층을 산화시켜 이중 캐패시터를 형성하거나, 박막 리프팅(Film lifting)의 문제를 유발하여 캐패시터의 전기적 특성 및 전극용량을 열화시킨다.However, in the Ta 2 O 5 capacitor manufacturing process using Ru as a lower electrode material of the prior art, the oxygen present in the Ru thin film by using a Low Pressure Chemical Vapor Deposition (LPCVD) during the deposition of Ru is subsequently removed. After deposition of the 2 O 5 dielectric layer, a barrier layer such as TiN is oxidized in the heat treatment process to form a double capacitor, or cause a problem of thin film lifting, resulting in deterioration of the electrical characteristics and the electrode capacity of the capacitor.
한편, 이러한 문제점을 해결하기 위해 물리기상증착법(Physical Vapor Deposition; PVD)으로 먼저 Ru를 증착 후 화학기상증착법(Chemical Vapor Deposition; CVD)에 의해 Ru를 다시 증착하여 상기 장벽층의 산화를 방지하기 위한 방법이 시도된다.Meanwhile, in order to solve this problem, first, Ru is deposited by physical vapor deposition (PVD), followed by chemical vapor deposition (CVD) to re-deposit Ru to prevent oxidation of the barrier layer. The method is tried.
그러나, 상기 물리기상증착법(PVD)으로 증착되는 Ru 박막은 단착피복성이 불량하고, 화학기상증착법(CVD)으로 증착되는 Ru 박막 내에 존재하는 산소가 많을 경우 후속 공정을 통해 물리기상증착법(PVD)으로 증착되는 Ru 박막 내로 산소가 침투하여 상기 장벽층을 산화시키는 문제가 발생한다.However, the Ru thin film deposited by the physical vapor deposition method (PVD) is poor in single layer coating, and when there is a large amount of oxygen present in the Ru thin film deposited by chemical vapor deposition (CVD), the physical vapor deposition method (PVD) through a subsequent process Oxygen penetrates into the Ru thin film deposited to cause oxidation of the barrier layer.
도 1은 종래의 Ru 하부전극 증착 후 암모니아(NH3)를 이용하여 열처리하는 방법을 사용한 반도체소자의 캐패시터 단면도를 나타낸다.1 is a cross-sectional view of a capacitor of a semiconductor device using a conventional method of heat treatment using ammonia (NH 3 ) after deposition of a Ru bottom electrode.
도 1를 참조하면, 트랜지스터의 소스/드레인과 같은 전도층(10)상의 절연막(11)을 선택적으로 식각하여 캐패시터 콘택홀(도시하지 않음)을 형성한 후 상기 콘택홀(도시하지 않음) 내부에 리세스된 폴리실리콘 플러그(12)를 형성한다. 다음으로 Ti/TiN층(13, 14)을 증착하여 상기 콘택홀(도시하지 않음) 내부에만 TiN 장벽층(14)이 형성되도록 평탄화한다. 이어서, 실린더 등의 형상으로 하부전극을 형성하가 위하여 희생산화물(도시하지 않음)을 증착 후 일정 부위를 식각한다.Referring to FIG. 1, an insulating film 11 on a conductive layer 10 such as a source / drain of a transistor is selectively etched to form a capacitor contact hole (not shown), and then inside the contact hole (not shown). The recessed polysilicon plug 12 is formed. Next, the Ti / TiN layers 13 and 14 are deposited and planarized so that the TiN barrier layer 14 is formed only inside the contact hole (not shown). Subsequently, in order to form the lower electrode in the shape of a cylinder or the like, certain portions are etched after the deposition of the sacrificial oxide (not shown).
다음으로, 화학기상증착법(CVD)을 이용하여 Ru를 증착한 후 암모니아 분위기에서 급속열처리(Rapid Thermal Process)를 실시하여 상기 Ru 하부전극(15) 내의 산소를 제거한 후에 Ta2O5 유전막(16)과 상부전극(17)을 차례로 증착하여 적층구조의 캐패시터를 형성한다.Next, after depositing Ru using chemical vapor deposition (CVD) and performing a rapid thermal process in ammonia atmosphere to remove oxygen in the Ru lower electrode 15, the Ta 2 O 5 dielectric film 16 And the upper electrode 17 are sequentially deposited to form a capacitor having a stacked structure.
전술한 바와 같이 이루어지는 RTP처리하여 Ru 내의 산소를 제거하는 종래기술은 Ru 하부전극 내의 산소는 제거되지만, 상기 Ru 하부전극에 산소가 다량 존재하다가 제거되는 경우 Ru가 응집되어 불연속적인 막이 형성되어 전기적 특성이 열화되는 문제가 발생한다.In the prior art in which the oxygen in the Ru is removed by the RTP treatment as described above, the oxygen in the Ru lower electrode is removed, but when a large amount of oxygen is present in the Ru lower electrode, the Ru is agglomerated to form a discontinuous film, thereby causing electrical characteristics. This deterioration problem occurs.
본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로서, Ru가 응집되어 불연속적인 Ru 하부전극이 형성되는 것을 방지하면서 Ru 하부전극 내의 산소를 제거하여 상기 Ru 하부전극의 막질을 개선하는 반도체소자 제조 방법을 제공하는데 그 목적이 있다. The present invention is to solve the above problems of the prior art, a semiconductor device that improves the film quality of the Ru lower electrode by removing oxygen in the Ru lower electrode while preventing Ru from agglomerated to form a discontinuous Ru lower electrode It is an object to provide a manufacturing method.
상기 목적을 달성하기 위하여 본 발명은 캐패시터의 제조 방법에 있어서, 절연막을 선택적으로 식각하여 커패시터 콘택홀을 형성하고 상기 콘택홀 내부에 리세스된 플러그를 형성하는 제1단계; 상기 제1단계가 완료된 결과물 상에 Ti와 TiN를 증착하여 상기 콘택홀 내부에만 Ti/TiN 장벽층이 형성되도록 평탄화하는 제2단계; 상기 제2단계가 완료된 결과물 상에 저압 화학기상증착법으로 산소를 반응가스로 이용하여 Ru 소스가스를 분해하여 Ru를 증착함과 동시에 암모니아를 이용하여 상기 산소를 환원시켜 제거하며 Ru 하부전극을 형성하는 제3단계; 상기 제3단계가 완료된 결과물 상에 암모니아 분위기에서 급속열처리하는 제4단계; 상기 Ru 하부전극 상에 Ta2O5층을 증착 및 결정화하여 Ta2O5 유전막을 형성하는 제5단계; 및 상기 제5단계가 완료된 결과물 상에 상부전극을 형성하는 제6단계를 포함한다.In order to achieve the above object, the present invention provides a method of manufacturing a capacitor, comprising: a first step of selectively etching an insulating film to form a capacitor contact hole and forming a recessed plug inside the contact hole; A second step of depositing Ti and TiN on the resultant product of which the first step is completed to planarize the Ti / TiN barrier layer to be formed only in the contact hole; Decomposition Ru source gas by using oxygen as a reaction gas on the resultant of the second step is completed by using a low pressure chemical vapor deposition method to deposit Ru and at the same time to reduce the oxygen by using ammonia to form a Ru bottom electrode The third step; A fourth step of rapid heat treatment in an ammonia atmosphere on the resultant of the third step; A fifth step of forming a Ta 2 O 5 dielectric layer by depositing and crystallizing the Ta 2 O 5 layer on the Ru lower electrode; And a sixth step of forming an upper electrode on a result of the fifth step being completed.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도 3a 내지 도 3d를 참조하여 설명한다.Hereinafter, in order to explain in detail enough to enable those skilled in the art to easily carry out the technical idea of the present invention, refer to FIGS. 3A to 3D attached to the most preferred embodiment of the present invention. Will be explained.
도 2a 내지 도 2f는 본 발명의 반도체소자 제조 공정을 나타내는 단면도이다.2A to 2F are cross-sectional views illustrating a semiconductor device manufacturing process of the present invention.
먼저, 도 2a에 도시된 바와 같이 예컨대, 트랜지스터의 소스/드레인과 같은 전도층(20) 상의 절연막(21)을 선택적으로 식각하여 캐패시터 콘택홀(도시하지 않음)을 형성하고, 상기 콘택홀(도시하지 않음) 내부에 플러그(22)를 형성하되, 콘택홀(도시하지 않음)의 상부 영역에서 리세스되도록 콘택홀(도시하지 않음) 내부 일부영역에만 플러그(22)를 형성한다. 여기서, 상기 절연막(21)은 통상 산화막 계열의 박막이 적용되며 메모리소자의 경우 층간 절연 및 평탄화 등을 고려하여 통상 다층의 산화막이 적용된다.First, as shown in FIG. 2A, an insulating layer 21 on the conductive layer 20 such as a source / drain of a transistor is selectively etched to form a capacitor contact hole (not shown), and the contact hole (not shown). The plug 22 is formed inside the plug 22, but the plug 22 is formed only in a partial region inside the contact hole (not shown) to be recessed in the upper region of the contact hole (not shown). In this case, an oxide film-based thin film is generally applied to the insulating layer 21. In the memory device, a multilayer oxide film is usually applied in consideration of interlayer insulation and planarization.
다음으로 도 2b에 도시된 것처럼, Ti층(23) 과 TiN 장벽층(24)을 증착하고 상기 콘택홀(도시하지 않음) 내부에만 상기 TiN 장벽층(24)이 형성되도록 평탄화 공정, 예컨대 에치백 또는 CMP(Chemical Mechanical Polishing) 공정을 실시한다. 여기서, Ti와 TiN의 증착두께는 플러그(22)가 형성된 이후의 콘택홀(도시하지 않음)의 리세스 정도 및 기타 조건에 따라 결정된다.Next, as shown in FIG. 2B, a planarization process, for example, an etch back, is deposited such that the Ti layer 23 and the TiN barrier layer 24 are formed, and the TiN barrier layer 24 is formed only inside the contact hole (not shown). Or CMP (Chemical Mechanical Polishing) process. Here, the deposition thickness of Ti and TiN is determined according to the degree of recess of the contact hole (not shown) and other conditions after the plug 22 is formed.
다음으로 도 2c에 도시된 바와 같이, Ru 하부전극의 형상을 결정하기 위한 희생산화막(25)을 증착한 후 상기 TiN 장벽층이 드러나도록 일정 부위를 식각한다.Next, as shown in FIG. 2C, after depositing a sacrificial oxide film 25 for determining the shape of the Ru lower electrode, a predetermined portion is etched to expose the TiN barrier layer.
다음으로 도 2d에 도시된 바와 같이 저압 화학기상증착법(LPCVD)으로 산소를 반응가스로 이용하여 Ru 소스가스를 분해하여 Ru를 증착함과 동시에 암모니아를 이용하여 상기 산소를 환원시켜 제거하며 Ru 하부전극(26)을 형성한다.Next, as illustrated in FIG. 2D, Ru source gas is decomposed using low pressure chemical vapor deposition (LPCVD) using oxygen as a reaction gas to deposit Ru, and at the same time, the oxygen is reduced and removed using ammonia. (26) is formed.
상기 Ru 하부전극(26) 형성 과정을 구체적으로 살펴 보면, 먼저, Ru 증착 시 반응가스로 10 sccm 내지 100 sccm의 산소를 이용하여 소스가스를 분해함과 동시에 100 sccm 내지 2000 sccm의 암모니아를 주입하여 산소를 환원시켜 증착되는 Ru 하부전극(26) 내의 산소를 제거한다. 여기서, 챔버 내는 0.1 Torr 내지 10 Torr의 압력 및 250℃ 내지 350℃의 웨이퍼 온도를 유지한다.Looking at the process of forming the Ru lower electrode 26 in detail, first, by decomposing the source gas by using 10 sccm to 100 sccm of oxygen as the reaction gas during the deposition of Ru and injecting ammonia of 100 sccm to 2000 sccm Oxygen is reduced to remove oxygen in the Ru lower electrode 26 that is deposited. Here, the chamber maintains a pressure of 0.1 Torr to 10 Torr and a wafer temperature of 250 ° C to 350 ° C.
이러한 과정을 반복적으로 실시하여 소정 두께의 하부전극(26)을 형성한 후에 암모니아 분위기에서 급속열처리(RTP)하여 상기 Ru 하부전극(26) 내의 산소를 완전히 제거한다. 여기서, 상기 급속열처리는 1000 sccm 내지 5000 sccm의 암모니아 분위기 및 500℃ 내지 700℃의 온도 하에서 30초 내지 120초 동안 실시한다.After repeating this process to form the lower electrode 26 having a predetermined thickness, rapid heat treatment (RTP) in an ammonia atmosphere is used to completely remove oxygen in the Ru lower electrode 26. Here, the rapid heat treatment is performed for 30 seconds to 120 seconds under an ammonia atmosphere of 1000 sccm to 5000 sccm and a temperature of 500 ℃ to 700 ℃.
다음으로 도 2e에 도시된 바와 같이, 상기 Ru 하부전극(26)을 평탄화하며 상기 희생산화막(25)을 딥아웃(Dip-out)한 후 Ta2O5를 증착 및 후처리하여 Ta2O 5 유전막(27)을 형성한다.Next, as shown in FIG. 2E, the Ru lower electrode 26 is planarized, and the sacrificial oxide layer 25 is dip-outed, and then Ta 2 O 5 is deposited and post-treated to form Ta 2 O 5. The dielectric film 27 is formed.
상기 Ta2O5 유전막(27)의 형성은 0.1 Torr 내지 2 Torr의 압력과 300℃ 내지 450℃의 온도를 유지하며 170℃ 내지 190℃의 기상상태인 탄탈륨 에칠레이트와 10 sccm 내지 1000 sccm의 산소를 이용한다.The formation of the Ta 2 O 5 dielectric layer 27 maintains a pressure of 0.1 Torr to 2 Torr and a temperature of 300 ° C. to 450 ° C., and a tantalum ethyleneate in a gaseous state of 170 ° C. to 190 ° C. and oxygen of 10 sccm to 1000 sccm. Use
상기 후처리 공정은 상기 Ta2O5 유전막(27)을 300℃ 내지 500℃의 온도를 유지하며 N2O 플라즈마처리 또는 자외선오존(UV-O3)처리를 이용한 표면처리한 후에 500℃ 내지 650℃의 온도 하에서 질소와 산소를 이용하여 급속열처리(RTP)한다.The post-treatment process maintains the Ta 2 O 5 dielectric layer 27 at a temperature of 300 ° C. to 500 ° C., and then performs surface treatment using N 2 O plasma treatment or ultraviolet ozone (UV-O 3 ) treatment. Rapid heat treatment (RTP) using nitrogen and oxygen at a temperature of ℃.
다음으로 도 2f에 도시된 바와 같이, 상기 Ta2O5 유전막(27) 상에 Ru 또는 TiN을 증착하여 상부전극(28)을 형성한다.Next, as shown in FIG. 2F, Ru or TiN is deposited on the Ta 2 O 5 dielectric layer 27 to form the upper electrode 28.
한편, 커패시터는 도면에 도시된 원통형 이외에 평판형, 오목형 등 다양한 형상으로 제조하는 것이 가능하다.On the other hand, the capacitor can be manufactured in various shapes such as a flat plate, a concave shape in addition to the cylindrical shape shown in the drawings.
전술한 것처럼 본 발명의 반도체소자 제조 방법은 저압 화학기상증착법을 이용하여 Ru 하부전극 증착 시 산소와 암모니아를 동시에 사용함으로써 산소를 제거함과 동시에 Ru 하부전극의 막질을 개선하고, 후속 암모니아 급속열처리에 의해 산소를 완전히(거의) 제거함으로써 산소에 의한 하지 장벽층의 산화를 방지하여 전체적인 캐패시터의 전기적 특성과 전극용량을 향상시킬 수 있음을 실시예를 통해 알아보았다.As described above, the semiconductor device manufacturing method of the present invention uses oxygen and ammonia at the same time to deposit the lower electrode by using a low pressure chemical vapor deposition method to remove oxygen and at the same time improve the film quality of the lower electrode of the Ru by rapid thermal treatment of ammonia. By removing oxygen completely (almost), the oxidation of the underlying barrier layer by oxygen was prevented, and thus the electrical characteristics and the electrode capacity of the entire capacitor were improved.
이상에서 본 발명의 기술 사상을 바람직한 실시예에 따라 구체적으로 기술하였으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 캐패시터 제조 방법에 있어서, Ru 하부전극의 막질을 개선하며 하지 장벽층의 산화를 방지함으로써 캐패시터의 전기적 특성과 전극용량을 향상시킬 수 있다.The present invention improves the film quality of the lower electrode of the Ru and prevents oxidation of the underlying barrier layer, thereby improving the electrical characteristics and the capacitance of the capacitor.
도 1은 종래의 Ru 하부전극 증착 후 암모니아(NH3)를 이용하여 열처리한 반도체소자의 캐패시터 단면도,1 is a cross-sectional view of a capacitor of a semiconductor device heat-treated using ammonia (NH 3 ) after deposition of a conventional Ru lower electrode;
도 2a 내지 2f는 본 발명의 실시예에 따른 반도체소자의 캐패시터 제조 공정을 나타내는 단면도.2A to 2F are cross-sectional views illustrating a capacitor manufacturing process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
20 : 전도층20: conductive layer
21 : 절연막21: insulating film
22 : 플러그22: plug
23 : Ti층23: Ti layer
24 : TiN층24: TiN layer
25 : 산화막25: oxide film
26 : Ru 하부전극26: Ru lower electrode
27 : 유전막27: dielectric film
28 : 상부전극28: upper electrode
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| US5668040A (en) * | 1995-03-20 | 1997-09-16 | Lg Semicon Co., Ltd. | Method for forming a semiconductor device electrode which also serves as a diffusion barrier |
| KR19980070915A (en) * | 1997-01-31 | 1998-10-26 | 윌리엄비.켐플러 | Integrated circuit structure manufacturing method |
| KR20000007684A (en) * | 1998-07-06 | 2000-02-07 | 윤종용 | Fabricating method of capacitor having ferroelectric film |
| KR20000040654A (en) * | 1998-12-18 | 2000-07-05 | 전주범 | Apparatus for adjusting volume in 2 tuner television and method thereof |
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| US5668040A (en) * | 1995-03-20 | 1997-09-16 | Lg Semicon Co., Ltd. | Method for forming a semiconductor device electrode which also serves as a diffusion barrier |
| KR19980070915A (en) * | 1997-01-31 | 1998-10-26 | 윌리엄비.켐플러 | Integrated circuit structure manufacturing method |
| KR20000007684A (en) * | 1998-07-06 | 2000-02-07 | 윤종용 | Fabricating method of capacitor having ferroelectric film |
| KR20000040654A (en) * | 1998-12-18 | 2000-07-05 | 전주범 | Apparatus for adjusting volume in 2 tuner television and method thereof |
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