KR20040039979A - Method of manufacturing capacitor for semiconductor device - Google Patents
Method of manufacturing capacitor for semiconductor device Download PDFInfo
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- KR20040039979A KR20040039979A KR1020020068242A KR20020068242A KR20040039979A KR 20040039979 A KR20040039979 A KR 20040039979A KR 1020020068242 A KR1020020068242 A KR 1020020068242A KR 20020068242 A KR20020068242 A KR 20020068242A KR 20040039979 A KR20040039979 A KR 20040039979A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 Ta2O5와 같은 고유전율의 유전막을 적용한 반도체 소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device to which a high dielectric constant film such as Ta 2 O 5 is applied.
일반적으로, 메모리셀에 사용되는 캐패시터는 스토리지(storage)용 하부 전극, 유전막, 및 플레이트(plate)용 상부전극으로 이루어지며, 제한된 면적 내에서 큰 커패시턴스를 얻기 위하여, 캐패시터의 높이를 증가시키고 MPS 등을 적용하면서 기존의 SiON(εr∼7)보다 유전율이 약 3 내지 4배 높은 Ta2O5(εr∼25)와 같은 고유전율의 유전막을 적용하고 있다.In general, a capacitor used in a memory cell is composed of a lower electrode for storage, a dielectric film, and an upper electrode for a plate, and in order to obtain a large capacitance within a limited area, the height of the capacitor is increased and MPS is used. The dielectric constant of high dielectric constant, such as Ta2O5 (ε r -25), which is about 3 to 4 times higher than conventional SiON (ε r -7), is applied.
한편, 이러한 Ta2O5는 일반적으로 비정질 상태로 증착이 이루어지기 때문에 결정화 및 막질특성 향상을 위하여 증착 후, 플라즈마 분위기의 저온 열처리와 노(furnace) 또는 급속열처리(Rapid Thermal Processing; RTP)의 고온열처리의 열처리 공정을 수행하는데, 이러한 열처리 공정이 진행될수록 Ta2O5의 막질 특성을 향상되나, 하부전극의 산화로 인하여 저유전층이 형성된다. 따라서, 종래에는 하부전극의 산화를 방지하기 위하여, Ta2O5를 증착하기 전에 NH3 개스에 의한 플라즈마 처리를 수행하여 폴리실리콘 표면을 질화시켜 SiN의 질화막을 형성시키는 방법이 이루어지고 있다. 그러나, 이 경우에도 후속 고온열처리 공정시 하부전극이 산화되는 것을 완전하게 방지할 수 없기 때문에 저유전층의 형성을 억제할 수 없게 됨으로써, 결국 캐패시턴스 저하 및 누설전류 특성의 저하를 야기시키게 된다.On the other hand, since Ta2O5 is generally deposited in an amorphous state, it is deposited after low temperature heat treatment in a plasma atmosphere and high temperature heat treatment in a furnace or rapid thermal processing (RTP) to improve crystallization and film quality. As the heat treatment process proceeds, the film quality of Ta 2 O 5 is improved, but a low dielectric layer is formed due to oxidation of the lower electrode. Accordingly, in order to prevent oxidation of the lower electrode, a method of forming a nitride film of SiN by nitriding a polysilicon surface by performing plasma treatment with NH 3 gas before depositing Ta 2 O 5 is performed. However, even in this case, since the lower electrode cannot be completely prevented from being oxidized in the subsequent high temperature heat treatment process, the formation of the low dielectric layer cannot be suppressed, which in turn causes a decrease in capacitance and a decrease in leakage current characteristics.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, Ta2O5와 같은 고유전율 유전막의 유전율을 더 높이면서 후속 열처리 공정에 따른 하부전극의 산화를 억제하여 고집적화에 따른 충분한 캐패시턴스를 확보함과 동시에 누설전류 특성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the problems of the prior art as described above, while increasing the dielectric constant of the high-k dielectric film, such as Ta2O5, while suppressing the oxidation of the lower electrode in the subsequent heat treatment process to secure sufficient capacitance due to high integration In addition, an object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device capable of improving leakage current characteristics.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10 : 반도체 기판 11 : 층간절연막10 semiconductor substrate 11 interlayer insulating film
12 : 플러그 13 : 하부전극12 plug 13 lower electrode
14 : 질화막 15 : Ta2O5막14 nitride film 15 Ta2O5 film
16A : TiN막 16B : 도핑된 폴리실리콘막16A: TiN film 16B: Doped polysilicon film
16 : 상부전극16: upper electrode
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 소정의 공정이 완료된 반도체 기판 상에 하부전극을 형성하는 단계; 하부전극의 표면에 박막의 질화막을 형성하는 단계; 질화막 상부에 고유전율의 유전막으로서 Ta2O5막을 형성하는 단계; Ta2O5막을 열처리하는 단계; 및 열처리된 Ta2O5막 상에 상부전극을 형성하는 단계를 포함하고, Ta2O5막의 형성은 CVD로 총 두께의 1/2 두께로 Ta2O5막을 형성하는 제 1 공정과, 1/2 두께의 Ta2O5막을 진공 RTP 장비로 스파이킹 열처리하는 제 2 공정과, 다시 온도를 상온으로 하강시켜 제 1 및 제 2 공정을 1회 반복 수행하여 나머지 두께의 Ta2O5막을 형성하는 제 3 공정으로 이루어진 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is the step of forming a lower electrode on a semiconductor substrate is completed a predetermined process; Forming a nitride film of a thin film on the surface of the lower electrode; Forming a Ta2O5 film on the nitride film as a high dielectric constant film; Heat treating the Ta 2 O 5 film; And forming an upper electrode on the heat-treated Ta2O5 film, wherein the formation of the Ta2O5 film is performed by CVD to form a Ta2O5 film with a thickness of 1/2 of a total thickness, and a vacuum RTP device using a Ta2O5 film having a thickness of 1/2. And a third process of forming a Ta2O5 film having a remaining thickness by repeatedly performing the first and second processes once by lowering the temperature to room temperature again by performing a spiking heat treatment in a furnace. It can be achieved by the method.
여기서, Ta2O5막은 40 내지 100Å의 두께로 형성하고, Ta2O5막의 CVD는 소오스 개스로서 Ta(C2H5O)5를 사용하고 반응개스로서 O2를 사용하여 400 내지 500℃의 온도 및 1Torr 미만의 압력에서 수행하며, CVD 공정시 압력은 02 분압에 의해 조절하낟.Here, the Ta 2 O 5 film is formed to a thickness of 40 to 100 kPa, CVD of the Ta 2 O 5 film is carried out at a temperature of 400 to 500 ℃ and a pressure of less than 1 Torr using Ta (C 2 H 5 O) 5 as the source gas and O2 as the reaction gas, The pressure in the CVD process is controlled by 02 partial pressure.
또한, 스파이킹 열처리는 1 내지 100Torr의 압력의 O2 분위기 및 800 내지850℃의 온도하에서 수행하며, 스파이킹 열처리시 상승속도를 초당 15 내지 25℃로 적용하여 800 내지 850℃의 온도에서 1 내지 2 초 정도 유지시키고, 스파이킹 열처리 동안 일정한 O2 분압을 유지시킨다.In addition, the spiking heat treatment is carried out under an O2 atmosphere of a pressure of 1 to 100 Torr and a temperature of 800 to 850 ° C, and during the spiking heat treatment, the rising rate is applied to 15 to 25 ° C per second to 1 to 2 at a temperature of 800 to 850 ° C. Hold for a second and maintain a constant O2 partial pressure during the spiking heat treatment.
또한, Ta2O5막의 열처리는 노를 이용하여 600 내지 650℃의 온도에서 N2 분위기로 5 내지 30분 동안 수행한다.In addition, the heat treatment of the Ta 2 O 5 film is performed for 5 to 30 minutes in an N 2 atmosphere at a temperature of 600 to 650 ℃ using a furnace.
또한, 질화막은 10 내지 20Å의 두께로 RTN 공정으로 형성하는데, RTN 공정은 600 내지 1000℃의 온도에서 수행한다.In addition, the nitride film is formed by the RTN process with a thickness of 10 to 20 kPa, and the RTN process is performed at a temperature of 600 to 1000 ° C.
또한, 하부전극은 도핑된 폴리실리콘막으로 형성하고, 상부전극은 TiN 박막과 도핑된 폴리실리콘막을 순차적으로 증착하여 형성하는데, TiN 박막은 200 내지 500Å의 두께로 증착하고, 도핑된 폴리실리콘막은 1000 내지 1500Å의 두께로 형성하며, TiN 박막은 CVD로 TiCl4 및 NH3 개스를 소오스 개스로 하여 500 내지 700℃의 온도에서 증착한다.In addition, the lower electrode is formed of a doped polysilicon film, the upper electrode is formed by sequentially depositing a TiN thin film and a doped polysilicon film, TiN thin film is deposited to a thickness of 200 ~ 500 내지, the doped polysilicon film is 1000 And a TiN thin film are deposited by CVD at a temperature of 500 to 700 ° C. using TiCl 4 and NH 3 gas as the source gas.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
도 1a를 참조하면, 트랜지스터 및 비트라인 등의 소정의 공정이 완료된 반도체 기판(10) 상에 층간절연막(11)을 형성하고, 기판(10)의 일부가 노출되도록 층간절연막(11)을 식각하여 플러그용 콘택홀을 형성한다. 그 다음, 상기 콘택홀에 매립되도록 층간절연막(11) 상에 플러그용 도전막으로 폴리실리콘막을 증착하고 화학기계연마(Chemical Mechanical Polishing; CMP) 공정이나 에치백(etchback) 공정으로 폴리실리콘막을 전면식각하여 플러그(12)를 형성한다. 그 후, 기판 전면 상에 캐패시터 산화막(미도시)을 형성하고, 플러그(12) 및 플러그(12) 주변의 일부가 노출되도록 산화막을 식각하여 캐패시터용 홀을 형성한 다음, 상기 홀 표면 및 산화막 상부에 도핑된 폴리실리콘막을 증착한다. 여기서, 도핑된 폴리실리콘막은 PH3 개스를 이용한 인-시튜(in-situ) 도핑방법으로 형성하고, 바람직하게 P의 농도는 3.0 ×1020atoms/cc로 유지한다. 그리고 나서, CMP 공정이나 에치백 공정으로 산화막의 표면이 노출되도록 폴리실리콘막을 전면 식각하여 서로 분리시켜 하부전극(13)을 형성한 후 상기 산화막을 제거한다.Referring to FIG. 1A, an interlayer insulating film 11 is formed on a semiconductor substrate 10 on which predetermined processes such as transistors and bit lines are completed, and the interlayer insulating film 11 is etched to expose a portion of the substrate 10. A plug contact hole is formed. Then, a polysilicon film is deposited on the interlayer insulating film 11 as a plug conductive film so as to be filled in the contact hole, and the entire surface of the polysilicon film is etched by a chemical mechanical polishing (CMP) process or an etchback process. To form the plug 12. Thereafter, a capacitor oxide film (not shown) is formed on the entire surface of the substrate, and the oxide film is etched to expose the plug 12 and a portion of the plug 12 periphery, thereby forming a capacitor hole. The doped polysilicon film is deposited. Here, the doped polysilicon film is formed by an in-situ doping method using PH3 gas, and the concentration of P is preferably maintained at 3.0 x 10 20 atoms / cc. Then, the polysilicon film is etched to the entire surface by the CMP process or the etch back process to expose the surface of the oxide film, and then the lower electrode 13 is formed to remove the oxide film.
도 1b를 참조하면, 후속 Ta2O5막 형성에 따른 열처리 공정시 하부전극(13)의 산화를 방지하기 위하여 급속열질화(Rapid Thermal Nitrification; RTN) 공정으로 하부전극(13) 표면에 SiN 박막의 질화막(14)을 형성한다. 바람직하게, RTN은 600 내지 1000℃의 온도에서 수행하고, 질화막(14)은 10 내지 20Å의 두께로 얇게 형성한다.Referring to FIG. 1B, in order to prevent oxidation of the lower electrode 13 in a subsequent heat treatment process according to Ta2O5 film formation, a nitride film of a SiN thin film (SiN thin film) is formed on the surface of the lower electrode 13 by a rapid thermal nitrification (RTN) process. 14). Preferably, the RTN is carried out at a temperature of 600 to 1000 ℃, the nitride film 14 is formed thin to a thickness of 10 to 20Å.
도 1c를 참조하면, 질화막(14) 상에 고유전율의 유전막으로서 Ta2O5막(15)을 40 내지 100Å의 두께로 형성한다. 여기서, Ta2O5막(15)의 형성은 먼저 화학기상증착(Chemical Vapor Deposition; CVD)으로 소오스 개스로서 Ta(C2H5O)5를 사용하고 반응개스로서 O2를 사용하여 400 내지 500℃의 온도 및 1Torr 미만의 압력에서 총 두께의 1/2 두께, 즉 20 내지 50Å의 두께로 Ta2O5막을 형성하는 제 1 공정과,이 1/2 두께의 Ta2O5막을 진공 RTP 장비로 1 내지 100Torr의 압력의 O2 분위기 및 800 내지 850℃의 온도하에서 스파이킹(spiking) 열처리하는 제 2 공정과, 다시 온도를 상온으로 하강시켜 상기 제 1 및 제 2 공정을 1회 반복 수행하여 나머지 두께의 Ta2O5막을 형성하는 제 3 공정으로 이루어진다.Referring to FIG. 1C, a Ta 2 O 5 film 15 is formed on the nitride film 14 as a high dielectric constant film with a thickness of 40 to 100 GPa. Here, the formation of the Ta2O5 film 15 is first performed using Chemical Vapor Deposition (CVD) using Ta (C2H5O) 5 as the source gas and O2 as the reaction gas at a temperature of 400 to 500 ° C and less than 1 Torr. The first step of forming a Ta2O5 film at a thickness of 1/2 to the thickness of 20 to 50 kPa in pressure, and this half-thick Ta2O5 film using a vacuum RTP equipment in an O2 atmosphere at a pressure of 1 to 100 Torr and 800 to 850 A second step of spiking heat treatment at a temperature of ℃ and a third step of forming the Ta2O5 film of the remaining thickness by performing the first and second steps once again by lowering the temperature to room temperature again.
여기서, CVD 공정시 공정압력은 O2의 분압으로 조절하며, 스파이킹 열처리시 상승속도를 초당 15 내지 25℃로 적용하여 800 내지 850℃의 온도에서 1 내지 2 초 정도 유지시키며, 스파이킹 열처리 동안 일정한 O2 분압을 유지시킨다. 이러한 스파이킹 열처리 공정에 의해 하부전극(13)의 산화가 효과적으로 억제될 수 있을 뿐만 아니라, Ta2O5막(15) 내로 산소를 공급하는 것이 가능하다. 또한, 진공 RTP 장비는 종래의 챔버(chamber)형과는 달리 공정온도를 고온계(pyrometer)를 사용하여 웨이퍼에서 방출하는 파장으로 온도를 읽기 때문에 직접 공정반응이 일어나는 웨이퍼 표면의 온도를 실시간으로 모니터하여 초당 수십회 이상 재보정할 수 있을 뿐만 아니라, O2의 압력조절이 가능하여 Ta2O5막(15) 내로의 산소공급량을 조절할 수 있다. 이에 따라, Ta2O5막(15)으로의 충분한 산소공급이 가능해지므로 안정한 Ta-O 결합을 형성할 수 있을 뿐만 아니라 충분한 고유전율을 확보할 수 있게 된다.Here, in the CVD process, the process pressure is controlled by the partial pressure of O2, and during the spiking heat treatment, the rising rate is applied at 15 to 25 ° C. per second to maintain the temperature at 800 to 850 ° C. for about 1 to 2 seconds, and is constant during the spiking heat treatment. Maintain a partial pressure of O2. By the spiking heat treatment process, not only the oxidation of the lower electrode 13 can be effectively suppressed, but also oxygen can be supplied into the Ta2O5 film 15. In addition, unlike the conventional chamber type, the vacuum RTP equipment reads the process temperature with the wavelength emitted from the wafer using a pyrometer, so it monitors the temperature of the wafer surface where the direct process reaction occurs in real time. Not only can it be recalibrated more than a few tens of times per second, but the pressure of O 2 can be adjusted to adjust the oxygen supply amount into the Ta 2 O 5 film 15. As a result, sufficient oxygen supply to the Ta 2 O 5 film 15 is possible, and thus not only a stable Ta-O bond can be formed but also a sufficient high dielectric constant.
그리고 나서, Ta2O5막(15)의 결정화 및 막질특성 개선을 위하여 노를 이용하여 600 내지 650℃의 온도에서 N2 분위기로 5 내지 30분 동안 열처리를 수행한다.Then, heat treatment is performed for 5 to 30 minutes in an N 2 atmosphere at a temperature of 600 to 650 ° C. using a furnace to improve the crystallization and film quality of the Ta 2 O 5 film 15.
도 1d를 참조하면, Ta2O5막(15) 상부에 TiN 박막(16A)과 도핑된 폴리실리콘막(16B)을 순차적으로 증착하여 상부전극(16)을 형성한다. TiN 박막(16A)은 CVD 공정으로 TiCl4 및 NH3 개스를 소오스 개스로 하여 500 내지 700℃의 온도에서 200내지 500Å의 두께로 증착하고, 도핑된 폴리실리콘막은 1000 내지 1500Å의 두께로 형성한다.Referring to FIG. 1D, the TiN thin film 16A and the doped polysilicon film 16B are sequentially deposited on the Ta 2 O 5 film 15 to form the upper electrode 16. The TiN thin film 16A is deposited with a thickness of 200 to 500 kPa at a temperature of 500 to 700 ° C. using TiCl 4 and NH 3 gas as a source gas by a CVD process, and the doped polysilicon film is formed to a thickness of 1000 to 1500 kPa.
상기 실시예에 의하면, 하부전극의 표면에 질화막을 형성하면서 유전막인 Ta2O5막을 CVD 공정 및 진공 RTP 장비의 스파이킹 열처리공정 등으로 2회에 걸쳐 형성함으로써, 하부전극의 산화를 효과적으로 억제하는 것이 가능할 뿐만 아니라 Ta2O5막으로의 충분한 산소공급으로 고유전율을 충분히 확보할 수 있게 된다. 이에 따라, 고집적화에 따른 충분한 캐패시턴스를 확보할 수 있고, 누설전류 특성을 향상시킬 수 있게 된다.According to the above embodiment, by forming the nitride film on the surface of the lower electrode, the Ta2O5 film, which is a dielectric film, is formed twice in the CVD process and the spiking heat treatment process of the vacuum RTP equipment. In addition, sufficient oxygen supply to the Ta 2 O 5 film ensures a high dielectric constant. As a result, sufficient capacitance due to high integration can be ensured, and leakage current characteristics can be improved.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 Ta2O5와 같은 고유전율 유전막의 유전율을 더 높이면서 후속 열처리 공정에 따른 하부전극의 산화를 효과적으로 억제할 수 있으므로, 고집적화에 따른 충분한 캐패시턴스를 확보할 수 있고 동시에 누설전류 특성을 향상시킬 수 있다.The present invention described above can effectively suppress oxidation of the lower electrode during the subsequent heat treatment process while increasing the dielectric constant of the high-k dielectric film such as Ta2O5, thereby ensuring sufficient capacitance due to high integration and improving leakage current characteristics. Can be.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100615602B1 (en) * | 2004-09-15 | 2006-08-25 | 삼성전자주식회사 | Methods of forming a titanium nitride layer having a smooth surface and methods of forming a semiconductor device using the same |
| US7588989B2 (en) | 2001-02-02 | 2009-09-15 | Samsung Electronic Co., Ltd. | Dielectric multilayer structures of microelectronic devices and methods for fabricating the same |
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| US7588989B2 (en) | 2001-02-02 | 2009-09-15 | Samsung Electronic Co., Ltd. | Dielectric multilayer structures of microelectronic devices and methods for fabricating the same |
| US8115262B2 (en) | 2001-02-02 | 2012-02-14 | Samsung Electronics Co., Ltd. | Dielectric multilayer structures of microelectronic devices and methods for fabricating the same |
| KR100615602B1 (en) * | 2004-09-15 | 2006-08-25 | 삼성전자주식회사 | Methods of forming a titanium nitride layer having a smooth surface and methods of forming a semiconductor device using the same |
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