JPH09167761A - Deposition of sog film - Google Patents

Deposition of sog film

Info

Publication number
JPH09167761A
JPH09167761A JP32611395A JP32611395A JPH09167761A JP H09167761 A JPH09167761 A JP H09167761A JP 32611395 A JP32611395 A JP 32611395A JP 32611395 A JP32611395 A JP 32611395A JP H09167761 A JPH09167761 A JP H09167761A
Authority
JP
Japan
Prior art keywords
sog
film
substrate
wiring
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP32611395A
Other languages
Japanese (ja)
Inventor
Taku Saeki
卓 佐伯
Ryuya Hara
竜弥 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UMC Japan Co Ltd
Original Assignee
Nippon Steel Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Semiconductor Corp filed Critical Nippon Steel Semiconductor Corp
Priority to JP32611395A priority Critical patent/JPH09167761A/en
Publication of JPH09167761A publication Critical patent/JPH09167761A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PROBLEM TO BE SOLVED: To eliminate crack from the protective film for underlying metallization. SOLUTION: After dripping SOG(spin on glass) liquid 4, a wafer 50 is turned at a low speed of 50-1000r.p.m. to spread the SOG liquid 4 flatly on an Al metallization 2 and an Si substrate. Subsequently, it is turned at a high speed of 4800r.p.m. or above within 5sec thus removing the SOG liquid 4 from the upper part of Al metallization 2. Consequently, substantially same quantity of SOG is deposited on the side A of Al metallization 2 contiguous to an adjacent Al metallization and the flat surface B side thereof.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
工程において層間絶縁膜の平坦化の目的で用いられるS
OG膜の形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for flattening an interlayer insulating film in a semiconductor device manufacturing process.
The present invention relates to a method for forming an OG film.

【0002】[0002]

【従来の技術】半導体装置の製造工程においては、多層
配線化の実施に伴い、各配線間の層間絶縁膜の平坦化が
行われている。層間絶縁膜の平坦化技術としては、従来
より、SOG(Spin On Glass) を用いる方法が知られ
ている。例えば、SOGを用いた平坦化技術の一つが特
開平7−142464号公報に開示されている。ここに
は、図13に示されるように、下層配線を覆う保護膜上
の有機物を分解除去した後、SOG液を塗布、ベークす
ることで、絶縁性、密着性に優れたSOG膜を形成する
方法が記載されている。
2. Description of the Related Art In the process of manufacturing a semiconductor device, flattening of an interlayer insulating film between wirings is carried out in accordance with implementation of multilayer wiring. As a technique for flattening the interlayer insulating film, a method using SOG (Spin On Glass) has been conventionally known. For example, one of the flattening techniques using SOG is disclosed in Japanese Patent Laid-Open No. 7-142464. As shown in FIG. 13, the SOG film having excellent insulation and adhesion is formed by decomposing and removing the organic matter on the protective film covering the lower layer wiring, and then applying and baking the SOG liquid. The method is described.

【0003】層間絶縁膜を平坦化する場合、このように
して下層配線を完全に覆う厚いSOG膜を形成した後、
ウェハ全面にエッチバックを施してSOG膜の上面を平
坦化するという方法がある。あるいは、エッチバックを
行わずに、塗布したSOG液をベークする前に比較的高
速でウェハを回転させて、各下層配線間の間隙、または
下層配線の段差部に表面が凹状となったSOGを残すと
いう方法がある。
When the interlayer insulating film is flattened, after forming a thick SOG film that completely covers the lower layer wiring in this way,
There is a method in which the entire surface of the wafer is etched back to flatten the upper surface of the SOG film. Alternatively, without etching back, the wafer is rotated at a relatively high speed before baking the applied SOG liquid to remove the SOG having a concave surface in the gap between the lower layer wirings or the stepped portion of the lower layer wirings. There is a way to leave.

【0004】前者の方法はウェハを均一に平坦化する方
法であるが、エッチバックが必要なために工程数が多く
なるという欠点を持っている。その一方、後者の方法は
ウェハを均一に平坦化するというよりも下層配線の段差
をなだらかにするというものであり、SOG液塗布時の
スピンのみで簡単に実施できるため、半導体製造工程に
おいてはこの方法がよく用いられている。
The former method is a method for uniformly flattening a wafer, but has a drawback that the number of steps is increased because etching back is required. On the other hand, the latter method is not to flatten the wafer uniformly, but to make the level difference of the lower layer wiring smooth, and since it can be easily performed only by spin at the time of applying the SOG liquid, this method is used in the semiconductor manufacturing process. The method is often used.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
SOG膜の形成方法においては、次のような問題が生じ
ていた。以下、図2を用いて説明する。図2はSOG膜
の従来の形成方法を示す図であり、図2(a)に示すよ
うに、Si基板1からなるウェハ上にAlによる配線パ
ターン2が形成されている。なお、Al配線2の膜厚は
700〜1000nm、線幅は0.8〜1.0μm、配
線間隔は0.8〜1.2μmである。
However, the conventional SOG film forming method has the following problems. Hereinafter, description will be made with reference to FIG. FIG. 2 is a diagram showing a conventional method of forming an SOG film. As shown in FIG. 2A, a wiring pattern 2 made of Al is formed on a wafer made of a Si substrate 1. The film thickness of the Al wiring 2 is 700 to 1000 nm, the line width is 0.8 to 1.0 μm, and the wiring interval is 0.8 to 1.2 μm.

【0006】次に、図2(b)に示すように、Si基板
1表面およびAl配線2表面上に、膜厚100〜300
nm程度のCVD膜3を形成する。なお、CVD膜3と
してはPSGまたはP−SiOが用いられ、これがAl
配線の保護膜となる。
Next, as shown in FIG. 2B, a film thickness of 100 to 300 is formed on the surface of the Si substrate 1 and the surface of the Al wiring 2.
A CVD film 3 having a thickness of about nm is formed. As the CVD film 3, PSG or P-SiO is used, which is Al
It serves as a protective film for the wiring.

【0007】そして、図2(c)に示すように、CVD
膜3の上にSOG液4を塗布する。この際、SOG液4
を滴下すると、SOG液4は配線2と配線2の間に溜ま
りやすく、平坦な箇所には溜まりにくい。ついで、SO
G液4を滴下したウェハを4500rpm 前後の回転数で
回転させると、図2(d)に示すように、配線2間のS
OG液4aの量はそれ程変化しないが、平坦な箇所のS
OG液4bは振り切られてしまい、Al配線2の側壁部
分に残るのみとなる。
Then, as shown in FIG. 2C, CVD
The SOG liquid 4 is applied on the film 3. At this time, SOG liquid 4
When is dropped, the SOG liquid 4 easily collects between the wirings 2 and does not easily collect in a flat portion. Then SO
When the wafer on which the G liquid 4 is dropped is rotated at a rotation speed of about 4500 rpm, as shown in FIG.
The amount of the OG liquid 4a does not change so much, but the S
The OG liquid 4b is shaken off and remains only on the side wall of the Al wiring 2.

【0008】その後、ウェハにベークを施すことにより
SOG膜4の脱水処理を行う。このベーク工程では、3
00〜500℃の温度で約60分の熱処理を行うことに
より、SOGに脱水反応が生じ、層間絶縁膜として完成
する。
Thereafter, the SOG film 4 is dehydrated by baking the wafer. In this baking process, 3
By performing a heat treatment for about 60 minutes at a temperature of 00 to 500 ° C., a dehydration reaction occurs in SOG to complete the interlayer insulating film.

【0009】ところで、このベーク工程においては、一
般にAl配線には自身が膨張する方向に内部応力が生
じ、CVD膜およびSOG膜には自身が収縮する方向に
内部応力が生じる。ところが、図2(d)に示したよう
に、一つのAl配線2の上部を見ると、隣のAl配線が
隣接する側(図中符号Aで示す)と平坦面側(図中符号
Bで示す)とでその部分に存在するSOGの量が大きく
異なっている。
By the way, in this baking step, an internal stress is generally generated in the Al wiring in the direction in which it expands, and an internal stress is generated in the CVD film and the SOG film in the direction in which it shrinks. However, as shown in FIG. 2D, when looking at the upper part of one Al wiring 2, the side where the adjacent Al wiring is adjacent (denoted by reference numeral A in the figure) and the flat surface side (denoted by reference numeral B in the figure). The amount of SOG present in that portion is significantly different from that shown in FIG.

【0010】SOGが少ない平坦面側BのCVD膜3で
はAlの膨張によって生じる引張応力が分散されるため
問題は生じない。これに対して、SOGが多いAl配線
隣接側AのCVD膜3ではAlの膨張による引張応力が
SOG膜4aの圧縮応力で抑えられてしまい、逃げるこ
とができない。さらに、こちら側ではCVD膜3とSO
G膜4aとの熱膨張率差による応力も大きくなる。した
がって、Al配線隣接側Aと平坦面側Bで応力の不均衡
が生じ、Al配線隣接側AのCVD膜3の角の部分に応
力が集中するため、この部分がはじけるようにCVD膜
3にクラック5が生じる。その結果、Al配線2の絶縁
性、信頼性の劣化が生じることになる。
In the CVD film 3 on the flat surface B having a small amount of SOG, the tensile stress generated by the expansion of Al is dispersed, so that no problem occurs. On the other hand, in the CVD film 3 on the side A of the Al wiring adjacent to a large amount of SOG, the tensile stress due to the expansion of Al is suppressed by the compressive stress of the SOG film 4a and cannot escape. Furthermore, on this side, the CVD film 3 and SO
The stress due to the difference in coefficient of thermal expansion from the G film 4a also increases. Therefore, stress imbalance occurs between the A wiring adjacent side A and the flat surface side B, and stress concentrates on the corner portions of the CVD film 3 on the Al wiring adjacent side A, so that this portion pops off on the CVD film 3. Cracks 5 occur. As a result, the insulation property and reliability of the Al wiring 2 are deteriorated.

【0011】本発明は、上記の課題を解決するためにな
されたものであって、下地となる金属配線の保護膜にク
ラックを生じさせることのないSOG膜の形成方法を提
供することを目的とする。
The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for forming an SOG film which does not cause cracks in a protective film of a metal wiring as an underlayer. To do.

【0012】[0012]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明のSOG膜の形成方法は、基板上に形成さ
れた金属配線に保護膜を被覆し、保護膜上に金属配線と
基板上面との段差を低減するためのSOG膜を回転塗布
により形成する方法において、SOG液を基板上に滴下
した後、基板を低速で回転させることにより滴下したS
OG液をその上面が平坦となるように金属配線および基
板の上方に塗り広げ、ついで、基板を高速で回転させる
ことにより少なくとも金属配線の上方にあたる部分のS
OG液を除去することを特徴とするものである。
In order to achieve the above object, a method of forming an SOG film according to the present invention covers a metal wiring formed on a substrate with a protective film, and forms a metal wiring on the protective film. In a method of forming an SOG film for reducing a step difference from the upper surface of a substrate by spin coating, after the SOG liquid is dropped on the substrate, S is dropped by rotating the substrate at a low speed.
The OG liquid is spread over the metal wiring and the substrate so that the upper surface thereof is flat, and then the substrate is rotated at a high speed so that at least the S portion above the metal wiring is exposed.
The feature is that the OG liquid is removed.

【0013】より具体的には、SOG液を基板上に滴下
した後、基板を低速で回転させる際の回転数を500〜
1000rpm とし、その後、基板を高速で回転させる際
の回転数を4800rpm 以上とし、基板の低速回転と高
速回転の間の時間間隔を5秒以内とすることが望まし
い。
More specifically, after the SOG liquid is dropped on the substrate, the number of rotations when the substrate is rotated at a low speed is 500 to.
It is desirable to set the rotation speed to 1000 rpm, and thereafter to rotate the substrate at a high speed at 4800 rpm or more, and to set the time interval between the low speed rotation and the high speed rotation of the substrate to 5 seconds or less.

【0014】[0014]

【発明の実施の形態】以下、本発明の一実施の形態を図
1を参照して説明する。図1は本実施の形態のSOG膜
の形成方法を順を追って示す図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a diagram sequentially showing a method of forming an SOG film according to the present embodiment.

【0015】図1(a)に示すように、Si基板1から
なる5インチ径のウェハ上にAlによる配線パターン2
が形成されている。なお、Al配線2の膜厚は700〜
1000nm、線幅は0.8〜1.0μm、配線間隔は
0.8〜1.2μmである。
As shown in FIG. 1A, a wiring pattern 2 of Al is formed on a 5-inch diameter wafer made of a Si substrate 1.
Are formed. The thickness of the Al wiring 2 is 700 to
The thickness is 1000 nm, the line width is 0.8 to 1.0 μm, and the wiring interval is 0.8 to 1.2 μm.

【0016】次に、図1(b)に示すように、Si基板
1表面およびAl配線2表面上に、膜厚100〜300
nm程度のCVD膜3を形成する。なお、CVD膜3と
してはPSGまたはP−SiOが用いられ、これがAl
配線2の保護膜となる。ここまでの工程は従来の方法と
同様である。
Next, as shown in FIG. 1B, a film thickness of 100 to 300 is formed on the surface of the Si substrate 1 and the surface of the Al wiring 2.
A CVD film 3 having a thickness of about nm is formed. As the CVD film 3, PSG or P-SiO is used, which is Al
It serves as a protective film for the wiring 2. The steps up to this point are the same as in the conventional method.

【0017】そして、図1(c)に示すように、CVD
膜3の上にSOG液4を塗布する。通常、SOG液4は
Al配線2間のような狭い箇所には入り込みやすく、A
l配線2上やSi基板1上などの比較的広い平坦部には
残りにくいという性質を持っている。そこで、SOG液
4がCVD膜3を完全に覆い、Al配線2上やSi基板
1上にも充分残るだけの量を滴下する。例えば、径が5
インチのウェハで2〜3ccとする。
Then, as shown in FIG.
The SOG liquid 4 is applied on the film 3. Normally, the SOG liquid 4 easily enters a narrow space such as between the Al wirings 2,
It has a property that it is hard to remain on a relatively wide flat portion such as the 1 wiring 2 or the Si substrate 1. Therefore, the SOG liquid 4 is dropped so as to completely cover the CVD film 3 and sufficiently remain on the Al wiring 2 and the Si substrate 1. For example, the diameter is 5
Inch wafer has 2-3 cc.

【0018】ついで、SOG液4を滴下したウェハを低
速回転で、例えば回転数500〜1000rpm 程度で
0.2〜0.5秒間回転させることにより、Al配線2
のパターンの有無にかかわらず膜の上面がほぼ平坦とな
るようにSOG液4を塗り広げる。ついで、回転モータ
の電源を切り、回転数を低下させて回転が完全に止まる
までの間、すなわち、通例、5秒以内に高速回転、例え
ば4800rpm 以上まで回転数を上げることにより、余
分なSOG液4だけが振り切られ、図1(d)に示すよ
うに、Al配線2間の狭い側Aと広い平坦部側Bで同じ
量のSOG液4が残る。なお、高速回転に上昇させる途
中、再び低速回転を経ることになるが、非常に短い時間
であるため、これは無視できる。
Then, the wafer on which the SOG liquid 4 has been dropped is rotated at a low speed, for example, at a rotation speed of about 500 to 1000 rpm for 0.2 to 0.5 seconds, whereby the Al wiring 2 is formed.
The SOG liquid 4 is spread so that the upper surface of the film becomes substantially flat regardless of the presence or absence of the pattern. Then, turn off the power of the rotary motor and lower the rotation speed until the rotation stops completely, that is, normally, within 5 seconds, rotate at a high speed, for example, increase the rotation speed to 4800 rpm or more to obtain an extra SOG liquid. Only 4 is shaken off, and as shown in FIG. 1D, the same amount of SOG liquid 4 remains on the narrow side A between the Al wirings 2 and the wide flat side B. It should be noted that, while the speed is increased to the high speed rotation, the low speed rotation is performed again, but since this is a very short time, this can be ignored.

【0019】例えば低速回転の回転数を500rpm 未満
とした場合、ウェハ中央部に滴下したSOG液が充分に
広がらないため、ウェハ中央部チップのSOG膜4の厚
みとウェハ周辺部チップのSOG膜4の厚みの差が極め
て大きくなり、特にウェハ周辺部チップのSOG膜4の
厚みは、図1(c)に示すように、Al配線2上のCV
D膜3にまで達することがない。すなわち、SOG膜4
が従来技術として示した図2(c)と同じ形態となるた
め、このウェハを回転させることでAl配線2上のSO
G膜4を除去し、図1(d)に示すように、Al配線2
間の狭い側Aと広い平坦部側Bで同じ量のSOG膜4を
残すことができなくなってしまう。したがって、低速回
転時の回転数の下限を500rpm とする。
For example, when the rotation speed of the low speed rotation is less than 500 rpm, the SOG liquid dropped on the central portion of the wafer does not spread sufficiently, so that the thickness of the SOG film 4 of the central chip of the wafer and the SOG film 4 of the peripheral chip of the wafer are reduced. The thickness difference of the SOG film 4 on the wafer peripheral chip becomes extremely large, as shown in FIG. 1C.
It does not reach the D film 3. That is, the SOG film 4
2 has the same form as that shown in FIG. 2C shown as the prior art. Therefore, the SO on the Al wiring 2 is rotated by rotating this wafer.
The G film 4 is removed, and as shown in FIG.
The same amount of SOG film 4 cannot be left on the narrow side A and the wide flat part side B. Therefore, the lower limit of the rotation speed at low speed rotation is set to 500 rpm.

【0020】一方、低速回転の回転数を1000rpm 以
上とした場合、回転数が増大するにつれてウェハに作用
する遠心力が増大し、SOG滴下量に対してウェハの外
に飛ばされるSOGの割合が増大するため、ウェハ内に
残存する、特にAl配線2間を除く部分のSOGの量が
少なくなる。すると、SOG膜4の厚みは結局のところ
Al配線2上のCVD膜3にまで達することがなく、上
記と同様、広い平坦部側Bの膜厚が薄いSOG膜4しか
形成できない。したがって、低速回転時の回転数の上限
を1000rpm とする。
On the other hand, when the rotation speed of the low-speed rotation is 1000 rpm or more, the centrifugal force acting on the wafer increases as the rotation speed increases, and the ratio of the SOG that is flown outside the wafer to the SOG dropping amount increases. Therefore, the amount of SOG remaining in the wafer, especially in the portion excluding between the Al wirings 2, is reduced. Then, the thickness of the SOG film 4 does not reach the CVD film 3 on the Al wiring 2 after all, and like the above, only the thin SOG film 4 on the wide flat portion side B can be formed. Therefore, the upper limit of the rotation speed at low speed rotation is set to 1000 rpm.

【0021】また、高速回転の回転数を4800rpm 未
満とした場合、Al配線2上のCVD膜3上にSOG膜
4が残留してしまい、Al配線2間のSOG膜4と平坦
部側のSOG膜が連続的に繋がるため、所望の半導体構
造が得られない。したがって、高速回転時の回転数の下
限を4800rpm とする。
When the rotation speed of the high speed rotation is set to less than 4800 rpm, the SOG film 4 remains on the CVD film 3 on the Al wiring 2 and the SOG film 4 between the Al wirings 2 and the SOG on the flat portion side. Since the films are continuously connected, the desired semiconductor structure cannot be obtained. Therefore, the lower limit of the rotation speed at the time of high speed rotation is set to 4800 rpm.

【0022】さらに、低速回転と高速回転の時間間隔に
ついては、時間間隔が5秒を越えるとウェハが完全に回
転を停止してしまうため、滴下するSOG液はウェハの
外に飛ばされることなく、ウェハ裏面側に浸透する。と
ころが、SOG液がウェハ裏面に浸透すると、その後の
乾燥工程やウェハ搬送工程等で浸透したSOG液が粉末
状態となってパーティクルの原因となるため、好ましく
ない。したがって、低速回転と高速回転の間の時間間隔
の上限値を5秒とする。なお、この5秒は、通例のスピ
ンコータの場合であって、要はウェハの回転が完全に停
止しない時間であればよい。
Regarding the time interval between the low speed rotation and the high speed rotation, when the time interval exceeds 5 seconds, the rotation of the wafer stops completely, so that the dropped SOG liquid is not splashed to the outside of the wafer. Penetrates to the back side of the wafer. However, if the SOG liquid permeates the back surface of the wafer, the SOG liquid permeated in the subsequent drying process, wafer transfer process, or the like becomes a powder state and causes particles, which is not preferable. Therefore, the upper limit of the time interval between the low speed rotation and the high speed rotation is set to 5 seconds. It should be noted that this 5 seconds is a case of a typical spin coater and may be any time as long as the rotation of the wafer is not completely stopped.

【0023】そして、SOG膜4を所定の形状に形成し
た後、ウェハにベークを施すことによりSOG膜4の脱
水処理を行う。このベーク工程では、300〜500℃
の温度で約60分の熱処理を行うと、SOGに脱水反応
が生じ、層間絶縁膜として完成する。
After forming the SOG film 4 into a predetermined shape, the wafer is baked to dehydrate the SOG film 4. In this baking process, 300-500 ° C
When the heat treatment is performed at the temperature of about 60 minutes, a dehydration reaction occurs in SOG to complete the interlayer insulating film.

【0024】本実施の形態のSOG膜の形成方法によれ
ば、図1(d)に示すように、一つのAl配線2を見た
ときに、隣のAl配線と隣接する側Aと平坦面側Bとで
その部分に存在するSOGの量を同じにすることができ
る。そこで、ベーク工程でウェハに熱が加えられたとき
に、Alの熱膨張によるCVD膜3の引張応力がSOG
膜4の圧縮応力で抑えられる度合がAl配線隣接側Aと
平坦面側Bとで同程度になり、かつ、CVD膜3とSO
G膜4の熱膨張率差による応力も双方で同程度となる。
According to the SOG film forming method of the present embodiment, as shown in FIG. 1D, when one Al wiring 2 is viewed, the side A adjacent to the adjacent Al wiring and the flat surface are formed. The amount of SOG present in that portion can be the same on side B. Therefore, when heat is applied to the wafer in the baking process, the tensile stress of the CVD film 3 due to the thermal expansion of Al causes SOG.
The degree of suppression by the compressive stress of the film 4 is almost the same on the side A adjacent to the Al wiring and the side B on the flat surface, and the CVD film 3 and the SO
The stress due to the difference in the coefficient of thermal expansion of the G film 4 is about the same for both.

【0025】すなわち、応力がAl配線隣接側Aと平坦
面側Bで均衡し、従来の形成方法を用いた場合のように
応力が片側に集中することがないので、CVD膜3にク
ラックが生じることがない。したがって、SOG膜がそ
の本来の目的である平坦化の役目を果たすことは勿論、
従来の形成方法に比べて、Al配線の絶縁性や信頼性を
向上させることができる。
That is, the stress is balanced between the side A adjacent to the Al wiring and the side B on the flat surface, and the stress is not concentrated on one side as in the case of using the conventional forming method, so that the CVD film 3 is cracked. Never. Therefore, it goes without saying that the SOG film fulfills its original purpose of flattening.
The insulation and reliability of the Al wiring can be improved as compared with the conventional forming method.

【0026】なお、本発明の技術範囲は上記実施の形態
に限定されるものではなく、本発明の趣旨を逸脱しない
範囲において種々の変更を加えることが可能である。例
えば本実施の形態では5インチウェハを用いる場合を例
として示したが、ウェハ径が多少大きくなったとして
も、SOGの滴下量は数cc程度あればウェハ回転後に
ウェハ上に残存するSOGの量が飽和状態となるため、
本発明の効果が同様に得られる。したがって、異なる径
のウェハに対しても低速回転および高速回転時のウェハ
の回転数のみを前述した範囲に設定することによって本
発明の方法を実現することができる。
The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, in the present embodiment, the case where a 5-inch wafer is used is shown as an example. However, even if the diameter of the wafer is slightly increased, if the drop amount of SOG is about several cc, the amount of SOG remaining on the wafer after the wafer is rotated. Becomes saturated,
The effect of the present invention can be obtained similarly. Therefore, even for wafers having different diameters, the method of the present invention can be realized by setting only the number of rotations of the wafer during low speed rotation and high speed rotation within the above-mentioned range.

【0027】[0027]

【発明の効果】以上、詳細に説明したように、本発明の
SOG膜の形成方法によれば、金属配線のうち、隣の金
属配線と隣接する側と平坦面側でその部分に存在するS
OGの量を同程度とすることができるため、ベーク工程
でウェハに熱を加えたときに保護膜中に生じる金属配線
の熱膨張による引張応力、SOG膜の圧縮応力を金属配
線側と平坦面側で均衡させることができる。したがっ
て、従来の形成方法を用いた場合のように応力が片側に
集中することがないので、金属配線を覆う保護膜にクラ
ックが生じることがなく、金属配線の絶縁性や信頼性を
向上させることができる。
As described above in detail, according to the method for forming an SOG film of the present invention, S existing in the portion of the metal wiring adjacent to the adjacent metal wiring and on the flat surface side.
Since the amount of OG can be made approximately the same, the tensile stress due to the thermal expansion of the metal wiring and the compressive stress of the SOG film that occur in the protective film when heat is applied to the wafer during the baking process are applied to the metal wiring side and the flat surface. Can be balanced on the side. Therefore, unlike the case where the conventional forming method is used, stress is not concentrated on one side, so that the protective film covering the metal wiring is not cracked, and the insulating property and reliability of the metal wiring are improved. You can

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態であるSOGの形成方法
を順を追って示す図である。
FIG. 1 is a diagram sequentially showing a method of forming an SOG which is an embodiment of the present invention.

【図2】従来のSOGの形成方法を順を追って示す図で
ある。
FIG. 2 is a diagram sequentially showing a conventional SOG forming method.

【符号の説明】[Explanation of symbols]

1 Si基板 2 Al配線(金属配線) 3 CVD膜(保護膜) 4,4a,4b SOG膜(SOG液) 5 クラック 1 Si substrate 2 Al wiring (metal wiring) 3 CVD film (protective film) 4, 4a, 4b SOG film (SOG liquid) 5 Crack

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 基板上に形成された金属配線に保護膜を
被覆し、該保護膜上に前記金属配線と基板上面との段差
を低減するためのSOG膜を回転塗布により形成する方
法において、 SOG液を基板上に滴下した後、該基板を低速で回転さ
せることにより滴下したSOG液をその上面が平坦とな
るように金属配線および基板の上方に塗り広げ、つい
で、基板を高速で回転させることにより少なくとも金属
配線の上方にあたる部分のSOG液を除去することを特
徴とするSOG膜の形成方法。
1. A method of coating a metal wiring formed on a substrate with a protective film, and forming an SOG film for reducing the step between the metal wiring and the upper surface of the substrate on the protective film by spin coating. After the SOG liquid is dropped on the substrate, the substrate is rotated at a low speed to spread the dropped SOG liquid over the metal wiring and the substrate so that the upper surface thereof is flat, and then the substrate is rotated at a high speed. By doing so, at least a portion of the SOG liquid above the metal wiring is removed, thereby forming a SOG film.
【請求項2】 請求項1に記載のSOG膜の形成方法に
おいて、 前記SOG液を前記基板上に滴下した後、該基板を低速
で回転させる際の回転数を500〜1000rpm とし、
その後、基板を高速で回転させる際の回転数を4800
rpm 以上とすることを特徴とするSOG膜の形成方法。
2. The method for forming an SOG film according to claim 1, wherein after the SOG liquid is dropped on the substrate, the rotation speed when the substrate is rotated at a low speed is 500 to 1000 rpm,
After that, the rotation speed when rotating the substrate at a high speed is 4800.
A method for forming an SOG film, characterized in that the speed is at least rpm.
【請求項3】 請求項1または2に記載のSOG膜の形
成方法において、 前記基板の低速回転と高速回転の間の時間間隔を5秒以
内とすることを特徴とするSOG膜の形成方法。
3. The method for forming an SOG film according to claim 1, wherein the time interval between the low speed rotation and the high speed rotation of the substrate is within 5 seconds.
JP32611395A 1995-12-14 1995-12-14 Deposition of sog film Withdrawn JPH09167761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32611395A JPH09167761A (en) 1995-12-14 1995-12-14 Deposition of sog film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32611395A JPH09167761A (en) 1995-12-14 1995-12-14 Deposition of sog film

Publications (1)

Publication Number Publication Date
JPH09167761A true JPH09167761A (en) 1997-06-24

Family

ID=18184238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32611395A Withdrawn JPH09167761A (en) 1995-12-14 1995-12-14 Deposition of sog film

Country Status (1)

Country Link
JP (1) JPH09167761A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010003577A (en) * 1999-06-24 2001-01-15 김영환 Method of forming an inter-layer insulating film in a semiconductor device
JP2011253846A (en) * 2010-05-31 2011-12-15 Nichia Chem Ind Ltd Light emitting device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010003577A (en) * 1999-06-24 2001-01-15 김영환 Method of forming an inter-layer insulating film in a semiconductor device
JP2011253846A (en) * 2010-05-31 2011-12-15 Nichia Chem Ind Ltd Light emitting device and method for manufacturing the same

Similar Documents

Publication Publication Date Title
JP2518435B2 (en) Multilayer wiring formation method
US5517062A (en) Stress released VLSI structure by the formation of porous intermetal layer
JPH09167761A (en) Deposition of sog film
JPH1197437A (en) Manufacture of semiconductor device and equipment therefor
JP3142457B2 (en) Method of manufacturing ferroelectric thin film capacitor
JPH08306681A (en) Formation of flattened coat insulating film
JP2928409B2 (en) Method for manufacturing semiconductor device
JPH0329298B2 (en)
JPH0565049B2 (en)
JPH0419707B2 (en)
JPH065544A (en) Manufacture of semiconductor device
JPH01207931A (en) Manufacture of semiconductor device
JPH05121560A (en) Manufacture of semiconductor device
JPH098137A (en) Semiconductor device and its manufacture
JPS6037150A (en) Manufacture of semiconductor device
JPH05152444A (en) Manufacture of semiconductor device
JPH01135044A (en) Semiconductor device
JPH0226054A (en) Manufacture of semiconductor device
JPH04326553A (en) Manufacture of semiconductor device
JPH06349951A (en) Manufacture of semiconductor device
JPS61256743A (en) Manufacture of semiconductor device
JPS6321850A (en) Manufacture of semiconductor device
JPS6358927A (en) Manufacture of semiconductor device
JPS61278148A (en) Forming method for glass coating
JPS5984442A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20030304