JPS6358927A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6358927A JPS6358927A JP20426486A JP20426486A JPS6358927A JP S6358927 A JPS6358927 A JP S6358927A JP 20426486 A JP20426486 A JP 20426486A JP 20426486 A JP20426486 A JP 20426486A JP S6358927 A JPS6358927 A JP S6358927A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode wiring
- aluminum alloy
- semiconductor device
- titanium nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 5
- 238000005546 reactive sputtering Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 238000000151 deposition Methods 0.000 abstract description 4
- 230000007797 corrosion Effects 0.000 abstract description 3
- 238000005260 corrosion Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、特に電極配
線の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming electrode wiring.
第２図は従来の半導体装置の主要製造工程を示し、以下
第２図を用いて従来の製造方法を説明する。FIG. 2 shows the main manufacturing steps of a conventional semiconductor device, and the conventional manufacturing method will be explained below using FIG.
まず、第２図（ａ）に示すようにシリコン基板１上に選
択酸化法で素子分離領域２を形成し、この素子分離領域
２で囲まれたシリコン基板１上にイオン注入法により拡
散層３を形成した後、シリコン基板１表面を絶縁膜４で
覆う。First, as shown in FIG. 2(a), an element isolation region 2 is formed on a silicon substrate 1 by a selective oxidation method, and a diffusion layer 3 is formed on the silicon substrate 1 surrounded by this element isolation region 2 by an ion implantation method. After forming the silicon substrate 1, the surface of the silicon substrate 1 is covered with an insulating film 4.
次に、第２回申）、に示すように絶縁膜４上にフォトレ
ジスト５を塗布し、写真製版を行うことによってフォト
レジスト５をパターニングした後、異方性ドライエツチ
ングで絶縁膜４をエツチングしてコンタクト孔を形成す
る。Next, as shown in Part 2), a photoresist 5 is coated on the insulating film 4, the photoresist 5 is patterned by photolithography, and then the insulating film 4 is etched by anisotropic dry etching. to form a contact hole.
そして、第２図（Ｃ）に示すようにスパッタ法でアルミ
ニウム合金膜６を堆積させ、最後に、写真製版と化学処
理を行うことによって第２図（ｄ）に示すようなアルミ
ニウム合金膜６からなる電極配線を形成する。Then, as shown in FIG. 2(C), an aluminum alloy film 6 is deposited by sputtering, and finally, by photolithography and chemical treatment, the aluminum alloy film 6 as shown in FIG. 2(d) is formed. Form an electrode wiring.
従来の半導体装置の製造方法は以上のように構成されて
いるので、微細で浅い拡散層をもつ半導体デバイスでは
、熱処理時のシリコン基板へのアルミニウムの拡散によ
ってＰＮ接合の接合特性が劣化するという問題点があっ
た。Since the conventional semiconductor device manufacturing method is configured as described above, in semiconductor devices having a fine and shallow diffusion layer, there is a problem that the bonding characteristics of the PN junction deteriorate due to the diffusion of aluminum into the silicon substrate during heat treatment. There was a point.
この発明は上記のような問題点を解消するためになされ
たもので、シリコン基板へのアルミニウムの拡散による
ＰＮ接合特性の劣化を防止でき、信頼性の高い半導体装
置の製造方法を得ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide a method for manufacturing a highly reliable semiconductor device that can prevent deterioration of PN junction characteristics due to diffusion of aluminum into a silicon substrate. shall be.
この発明に係る半導体装置の製造方法は、基板上にバリ
アメタル層として窒化チタン膜を５００Å以上堆積し、
その後電極配線用アルミニウム合金膜を形成するように
したものである。A method for manufacturing a semiconductor device according to the present invention includes depositing a titanium nitride film of 500 Å or more as a barrier metal layer on a substrate,
After that, an aluminum alloy film for electrode wiring is formed.
この発明においては、電極配線用のアルミニウム合金膜
を堆積する前に、バリアメタル層として耐熱性及び耐蝕
性に優れた窒化チタン膜を基板上に５００Å以上堆積す
るようにしたから、アルミニウム合金膜とシリコン基板
間の相互拡散を防止できる。In this invention, before depositing the aluminum alloy film for electrode wiring, a titanium nitride film with a thickness of 500 Å or more, which has excellent heat resistance and corrosion resistance, is deposited on the substrate as a barrier metal layer. Mutual diffusion between silicon substrates can be prevented.
以下、この発明の一実施例を図について説明する。第１
図は本発明の一実施例による半導体装置の製造方法を工
程順に示したものである。図において、１〜６は第２図
と同一のものであり、７は電極配線用アルミニウム合金
膜６を堆積する前に基板１上に形成された膜圧５００Å
以上の窒化チタン膜であり、アルミニウム合金膜６のバ
リアメタル層として耐熱性及び耐蝕性に優れたものであ
る。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. In the figure, 1 to 6 are the same as in FIG. 2, and 7 is a film with a film thickness of 500 Å formed on the substrate 1 before depositing the aluminum alloy film 6 for electrode wiring.
The above titanium nitride film has excellent heat resistance and corrosion resistance as a barrier metal layer of the aluminum alloy film 6.
次に製造方法について説明する。Next, the manufacturing method will be explained.
まず、第１図（ａ）に示すように従来方法と同じ方法で
シリコン基板１上に素子分離領域２．拡散層３、絶縁膜
４を順次形成し、該絶縁膜４にコンタクト孔を形成した
後、バリアメタル層として窒化チタン膜７をリアクティ
ブスパッタリング法で膜厚５００Å以上堆積する。First, as shown in FIG. 1(a), an element isolation region 2 is formed on a silicon substrate 1 using the same method as the conventional method. After sequentially forming a diffusion layer 3 and an insulating film 4 and forming a contact hole in the insulating film 4, a titanium nitride film 7 is deposited as a barrier metal layer to a thickness of 500 Å or more by a reactive sputtering method.
次に、第１図（ｂ）に示すように、上記窒化チタン膜７
上に電極配線材料としてアルミニウム合金膜６をスパッ
タ法等で堆積する。Next, as shown in FIG. 1(b), the titanium nitride film 7
An aluminum alloy film 6 is deposited thereon as an electrode wiring material by sputtering or the like.
そして、写真製版、化学処理を行うことにより選択的に
アルミニウム合金膜６及び窒化チタン膜７を残し、第１
図（Ｃ）に示すような電極配線を形成する。Then, by performing photolithography and chemical treatment, the aluminum alloy film 6 and the titanium nitride film 7 are selectively left, and the first
Electrode wiring as shown in Figure (C) is formed.
次に作用効果について説明する。Next, the effects will be explained.
第３図のグラフはＡｊ！、ＴｉＮ、ＰｔＳｉ、ｎ−３ｉ
系電極におけるＰｔ５ｉ−ｎ−３ｉシヨツトキダイオー
ド特性に対する窒化チタン（Ｔ ｉ Ｎ）膜の膜厚依存
性を示し、すなわち横軸に熱加速を行なう時間つまりＰ
−Ｎ接合の特性の劣化を早めるためダイオードに熱を加
える時間を取り、縦軸に逆方向電流値ＩＲを取り、窒化
チタン膜の膜厚をパラメータとして熱（４９０℃）によ
るＰ−Ｎ接合特性の劣化度を示している。ここでｒｉ−
２０ｎＡの破線はアルミニウム合金膜とシリコン基板間
に相互拡散が起こっているかどうかを判断する境界線で
ある。このグラフが示すように窒化チタンの膜厚が３０
０人、 ＳＯＯ人の場合は熱加速を１２０分行なうとす
でに相互拡散が起っているのに対し、窒化チタンの膜厚
が１０００人の場合は熱加速を３００分行なっても逆方
向電流は２０ｎＡ以下と少なく相互拡散は起っていない
。The graph in Figure 3 is Aj! , TiN, PtSi, n-3i
The film thickness dependence of the titanium nitride (T i N) film on the characteristics of the Pt5i-n-3i shot diode in the system electrode is shown.
- P-N junction characteristics due to heat (490°C) with the film thickness of the titanium nitride film as a parameter, taking the time to heat the diode to accelerate the deterioration of the characteristics of the N junction, and plotting the reverse current value IR on the vertical axis. It shows the degree of deterioration. Here ri-
The 20 nA broken line is a boundary line for determining whether mutual diffusion has occurred between the aluminum alloy film and the silicon substrate. As this graph shows, the film thickness of titanium nitride is 30
In the case of 0 people and SOO people, interdiffusion has already occurred after 120 minutes of thermal acceleration, whereas in the case of a titanium nitride film with a thickness of 1000 people, there is no reverse current even after 300 minutes of thermal acceleration. The current was less than 20 nA, and no interdiffusion occurred.
従って本実施例では基板とアルミニウム合金との間に膜
厚５００Å以上のＴｉＮ膜を形成するようにしたので、
信鯨性の高い電極を有する半導体装置が得られる。Therefore, in this example, a TiN film with a thickness of 500 Å or more was formed between the substrate and the aluminum alloy.
A semiconductor device having an electrode with high reliability can be obtained.
以上のように、この発明によれば、微細で浅いＰＮ接合
を有する半導体装置の製造方法において、基板上に障壁
金属層として反応性スパッタリング法により５００Å以
上の膜厚の窒化チタン膜を形成し、その後を極配線用の
アルミニウムを形成するようにしたので、接合特性の優
れた電極配線を有する半導体装置が得られる効果がある
。As described above, according to the present invention, in a method for manufacturing a semiconductor device having a fine and shallow PN junction, a titanium nitride film having a thickness of 500 Å or more is formed as a barrier metal layer on a substrate by a reactive sputtering method, Since aluminum for the electrode wiring is then formed, there is an effect that a semiconductor device having electrode wiring with excellent bonding characteristics can be obtained.
第１図はこの発明の一実施例による半導体装置の製造方
法を工程順に示す断面図、第２図は従来の半導体装置の
製造方法を工程順に示す断面図、第３図は窒化チタンの
バリア効果がその膜厚に依存することを説明するための
データ図である。
図において、ＩＬよシリコン基板、２は素子分離領域、
３は拡散層、４は絶縁膜、５はフォトレジスト、６はア
ルミニウム合金膜、７は窒化チタン膜である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of process, FIG. 2 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device in order of process, and FIG. 3 is a barrier effect of titanium nitride. FIG. 3 is a data diagram for explaining that the film thickness depends on the film thickness. In the figure, IL is a silicon substrate, 2 is an element isolation region,
3 is a diffusion layer, 4 is an insulating film, 5 is a photoresist, 6 is an aluminum alloy film, and 7 is a titanium nitride film. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (2)
て、 拡散層を有する半導体基板の表面上に絶縁膜を形成する
第１の工程、 前記拡散層上の絶縁膜にコンタクト用の窓明けを行う第
２の工程、 全面にバリアメタル膜、電極配線材料を順次形成する第
３の工程、 その後前記バリアメタル膜及び電極配線材料を選択的に
除去してコンタクト孔に電極配線を形成する第４の工程
を含むことを特徴とする半導体装置の製造方法。(1) In a method of manufacturing a semiconductor device in which electrode wiring is formed, a first step of forming an insulating film on the surface of a semiconductor substrate having a diffusion layer, forming a window for a contact in the insulating film on the diffusion layer. a second step, a third step of sequentially forming a barrier metal film and an electrode wiring material on the entire surface, and a fourth step of selectively removing the barrier metal film and electrode wiring material to form an electrode wiring in the contact hole. 1. A method of manufacturing a semiconductor device, the method comprising the steps of:
ィブスパッタリング法によって膜圧５００Å以上の窒化
チタン膜を形成し、その後電極配線材料としてアルミニ
ウム合金を全面に形成する工程であることを特徴とする
特許請求の範囲第１項記載の半導体装置の製造方法。(2) The third step is characterized in that a titanium nitride film with a film thickness of 500 Å or more is formed as a barrier metal film by a reactive sputtering method, and then an aluminum alloy is formed on the entire surface as an electrode wiring material. A method for manufacturing a semiconductor device according to claim 1.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20426486A JPS6358927A (en) | 1986-08-29 | 1986-08-29 | Manufacture of semiconductor device |
| DE19873714955 DE3714955A1 (en) | 1986-08-29 | 1987-05-06 | Method of fabricating a semiconductor device and semiconductor device fabricated by the method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20426486A JPS6358927A (en) | 1986-08-29 | 1986-08-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6358927A true JPS6358927A (en) | 1988-03-14 |
Family
ID=16487584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20426486A Pending JPS6358927A (en) | 1986-08-29 | 1986-08-29 | Manufacture of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS6358927A (en) |
| DE (1) | DE3714955A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63174319A (en) * | 1987-01-14 | 1988-07-18 | Hitachi Ltd | Manufacture of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS493237A (en) * | 1972-04-22 | 1974-01-12 | ||
| JPS605560A (en) * | 1983-06-23 | 1985-01-12 | Fujitsu Ltd | Semiconductor device |
| JPS609159A (en) * | 1983-06-29 | 1985-01-18 | Fujitsu Ltd | Semiconductor device |
| JPS6010717A (en) * | 1983-06-30 | 1985-01-19 | Nec Corp | Fabrication of contact for semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2164491B (en) * | 1984-09-14 | 1988-04-07 | Stc Plc | Semiconductor devices |
-
1986
- 1986-08-29 JP JP20426486A patent/JPS6358927A/en active Pending
-
1987
- 1987-05-06 DE DE19873714955 patent/DE3714955A1/en not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS493237A (en) * | 1972-04-22 | 1974-01-12 | ||
| JPS605560A (en) * | 1983-06-23 | 1985-01-12 | Fujitsu Ltd | Semiconductor device |
| JPS609159A (en) * | 1983-06-29 | 1985-01-18 | Fujitsu Ltd | Semiconductor device |
| JPS6010717A (en) * | 1983-06-30 | 1985-01-19 | Nec Corp | Fabrication of contact for semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63174319A (en) * | 1987-01-14 | 1988-07-18 | Hitachi Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3714955A1 (en) | 1988-03-17 |
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