JPS60257182A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60257182A JPS60257182A JP11293984A JP11293984A JPS60257182A JP S60257182 A JPS60257182 A JP S60257182A JP 11293984 A JP11293984 A JP 11293984A JP 11293984 A JP11293984 A JP 11293984A JP S60257182 A JPS60257182 A JP S60257182A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- junction
- metal electrode
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 238000004140 cleaning Methods 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 239000007790 solid phase Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 238000009434 installation Methods 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000605 extraction Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000003064 anti-oxidating effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体装置、特にショットキ・バリア・ダイ
オードの製造に適用して有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to the manufacture of semiconductor devices, particularly Schottky barrier diodes.
半導体に金属電極を接合して構成される、いわゆるショ
ットキ・バリア・ダイオードの製造方法としては次のよ
うなものが考えらねる。The following methods can be considered for manufacturing a so-called Schottky barrier diode, which is constructed by bonding a metal electrode to a semiconductor.
すなわち、導電型シリコン基板上に形成される導電型の
エピタキシャル層を、電極形成領域を除いて二酸化シリ
コン（Ｓｉｎ、）膜等からなる絶縁膜で被ったのち、前
記電極形成領域にたとえばタングステン（Ｗ）からなる
金属電極を形成する方法である。That is, after a conductive epitaxial layer formed on a conductive silicon substrate is covered with an insulating film made of silicon dioxide (Sin), etc., except for the electrode formation region, a tungsten (W) film is applied to the electrode formation region. ) is a method of forming a metal electrode consisting of
上記の方法において、絶縁膜の一部に電極形成領域を形
成する方法としては、たとえばフォトエツチングによっ
て電極形成領域に相当する絶縁膜を除去し、金属電極と
接合部を構成する前記エピタキシャル層を露出させ、洗
浄液で洗浄することによって浄化したのち金属電極をた
とえは真空蒸着によって所定の厚さ、所定の形状に形成
することが行なわれる。In the above method, the method for forming the electrode formation region in a part of the insulating film includes removing the insulating film corresponding to the electrode formation region by photoetching, for example, and exposing the epitaxial layer that forms the joint with the metal electrode. After cleaning by cleaning with a cleaning liquid, a metal electrode is formed into a predetermined thickness and shape by vacuum deposition, for example.
しかしながら上記の方法では、絶縁膜に形成される電極
形成領域が凹状であるため前記の洗浄作業に際し、電極
形成領域内の底部周辺に異物が残存しやすいという欠点
がある。However, the above method has a drawback in that since the electrode forming area formed in the insulating film is concave, foreign matter tends to remain around the bottom of the electrode forming area during the cleaning operation.
この結果接合部には異物が介在することと１．【す、安
定なショットキ接合が１月害さオ１．逆方向宵１王印加
時のリーク宵筺、の増加などに起因する製品不良の発生
があることを本発明者は見い出した。As a result, foreign matter is present in the joint.1. [A stable Schottky bond is damaged in January 1. The inventor of the present invention has found that product defects occur due to an increase in leakage when a reverse voltage is applied.
本発明の目的は、安定なショットキ接合を有する半導体
装置の製造技術を提供することにある。An object of the present invention is to provide a technique for manufacturing a semiconductor device having a stable Schottky junction.
本発明の前記ならびにその他の目的と新規な特徴は５本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体表面に絶縁膜を形成する前に金属電極
を形成することによって、金属電極と半導体の接合部に
異物が介在することを防止し、前記目的を達成するもの
である。That is, by forming a metal electrode before forming an insulating film on the semiconductor surface, foreign matter is prevented from intervening at the junction between the metal electrode and the semiconductor, thereby achieving the above object.
〔実施例１〕
第１図（ａ）〜（ｄ）は本発明の一実施例であるショッ
トキ・バリア・ダイオードの製造方法を工程順に示す断
面図である。[Embodiment 1] FIGS. 1(a) to 1(d) are cross-sectional views showing a method for manufacturing a Schottky barrier diode according to an embodiment of the present invention in order of steps.
第１図（ａ）に示されるように、導電型のシリコン基板
１の一主面には導電型のシ１）コンのエピタキシャル層
２が形成される。As shown in FIG. 1(a), an epitaxial layer 2 of conductive silicon 1) is formed on one main surface of a conductive silicon substrate 1. As shown in FIG.
このエピタキシャル層２の表面は、たとえば洗浄等の方
法によって清浄とされた後、たとえばタングステン（Ｗ
’）からなる金属電極層３が形成される。After the surface of the epitaxial layer 2 is cleaned by a method such as cleaning, the surface of the epitaxial layer 2 is cleaned using a method such as tungsten (W).
') is formed.
この場合、前記洗浄時において、エピタキシャル層２の
表面には凹凸がないため、異物等が残存しに（く、エピ
タキシャル層２０表面に形成される金属電極層３との界
面に異物が介在することが防止される。In this case, during the cleaning, since there are no irregularities on the surface of the epitaxial layer 2, no foreign matter remains (and no foreign matter is present at the interface with the metal electrode layer 3 formed on the surface of the epitaxial layer 20). is prevented.
次に真空中で所定の温度で所定時間加熱処理されること
によってエピタキシャル層２と金属電極層３の接合部は
定定化される。Next, the joint between the epitaxial layer 2 and the metal electrode layer 3 is stabilized by heat treatment in vacuum at a predetermined temperature for a predetermined time.
その後、同図（ｂ）に示されるように、金属電極層３は
、たとえばフォトエツチングの方法によって。Thereafter, as shown in FIG. 3(b), the metal electrode layer 3 is formed by, for example, a photo-etching method.
金属電極３ａとなる部分を残して除去される。It is removed leaving a portion that will become the metal electrode 3a.
また、金属電極層３が除去された部分のエピタキシャル
層２の表面部はさらに所定の厚さだけ、たとえばエツチ
ングの方法によって除去され、金属電極層３を構成する
金属原子がエピタキシャル層２０表面に拡散されること
によって形成される固相拡散層が取り除かれる。Further, the surface portion of the epitaxial layer 2 where the metal electrode layer 3 has been removed is further removed by a predetermined thickness by, for example, an etching method, and the metal atoms constituting the metal electrode layer 3 are diffused to the surface of the epitaxial layer 20. The solid phase diffusion layer formed by the oxidation is removed.
次に同図（ｃ）に示されるように、たとえば化学気相成
長（ＣＶＤ）法によって、金属電極３ａおよびエビ４キ
シャル層２０表面には、たとえば酸化シリコンからなる
絶縁膜４が形成される。Next, as shown in FIG. 4C, an insulating film 4 made of silicon oxide, for example, is formed on the surfaces of the metal electrode 3a and the evidential quaternary layer 20 by, for example, chemical vapor deposition (CVD).
この絶縁膜４の一部は、たとえばフォトエツチングの方
法によって除去され、取り出し電極形成窓５が形成され
る。A portion of this insulating film 4 is removed by, for example, a photoetching method, and a lead-out electrode forming window 5 is formed.
次に同図（ｄ）に示されるように、たとえばアルミニウ
ム（Ａｌｌ ）で構成される取り出し電極６が形成され
、ショットキ・バリア・ダイオード７がつくられる。Next, as shown in FIG. 2D, an extraction electrode 6 made of aluminum (All), for example, is formed, and a Schottky barrier diode 7 is fabricated.
本実施例の方法によれば、エピタキシャル層２０表面が
清浄な状態で金属電極層３が形成されるため、エピタキ
シャル層２と金属電極３ａとの接合部に異物が介在する
ことが防止され、安定なシ（５）
ョットキ接合が得られる。According to the method of this embodiment, the metal electrode layer 3 is formed with the surface of the epitaxial layer 20 being clean, so that it is possible to prevent foreign matter from intervening at the joint between the epitaxial layer 2 and the metal electrode 3a, and to ensure stability. (5) A Schottky junction is obtained.
〔実施例２〕
第２図は本発明の他の実施例であるショットキ・バリア
・ダイオードの製造方法を工程順に示す断面図である。[Embodiment 2] FIG. 2 is a sectional view showing a method for manufacturing a Schottky barrier diode according to another embodiment of the present invention in the order of steps.
本実施例においては、第２図（ａｌで示されるように、
金属電極層３０表面に、酸化防止のため、たとえば白金
（Ｐｔ）で構成される金属層８が設けられているところ
が前記の実施例１とは異なる。In this example, as shown in FIG. 2 (al),
This embodiment differs from the first embodiment in that a metal layer 8 made of, for example, platinum (Pt) is provided on the surface of the metal electrode layer 30 to prevent oxidation.
すなわち、金属電極層３に、たとえば真空蒸着の方法で
形成される金属層８は、同図（ｂｌで示されるように、
金属電極３ａの形成時においても、酸化防止層８ａとし
て残され、同図（ｃｌにおいて絶縁膜４が形成される際
に金属電極３ａが酸化されることを防止する。That is, the metal layer 8 formed on the metal electrode layer 3 by, for example, a vacuum evaporation method is as shown in FIG.
Even when the metal electrode 3a is formed, it is left as an oxidation prevention layer 8a to prevent the metal electrode 3a from being oxidized when the insulating film 4 is formed in the same figure (cl).
この酸化防止層８ａは同図（ｄ）で示されるように。This anti-oxidation layer 8a is as shown in FIG.
取り出し電極形成窓５が形成されたのち、絶縁膜４で覆
われた周辺部を除いて除去される。After the extraction electrode forming window 5 is formed, the portion except for the peripheral portion covered with the insulating film 4 is removed.
次に同図ｔｅｌで示されるように、露出される金属電極
３ａＫ取り出し電極６が形成され、ショット（６）
キ・バリア・ダイオード７ａがつくられる。Next, as shown by tel in the figure, an exposed metal electrode 3aK extraction electrode 6 is formed, and a Schott (6) barrier diode 7a is fabricated.
本実施例の方法によれば、エピタキシャル層２と金属１
を鞭３ａとの間に安定なショットキ接合が得られること
は、前記実施例１の場合と同様であるが、さら知、金属
電極３ａの表面の酸化が防止されるため、取り出しｔ極
６との間に良好なオーム接合が得られ、順方向の駆動電
圧が所定の値以」１に増大することが防止される。According to the method of this embodiment, the epitaxial layer 2 and the metal 1
A stable Schottky junction can be obtained between the metal electrode 3a and the metal electrode 3a, as in the case of Example 1, but since oxidation of the surface of the metal electrode 3a is prevented, A good ohmic junction is obtained between them, and the forward drive voltage is prevented from increasing beyond a predetermined value.
〔効果］
（１）半導体表面に金属電極が形成されたのち忙絶縁膜
が形成されるため、絶縁膜形成過程において半導体表面
と金属電極との間に異物が介在することが防止され、安
定なショットキ接合が得られる。[Effects] (1) Since a busy insulating film is formed after a metal electrode is formed on the semiconductor surface, foreign matter is prevented from intervening between the semiconductor surface and the metal electrode during the insulating film formation process, resulting in a stable A Schottky junction is obtained.
（２）金属ＩｆＩＬ極の表面に金属層が形成されたのち
に絶縁膜が形成されるため、金ＰＡｔ極の酸化が防止さ
れ、良好な順方向特性が得られる。(2) Since the insulating film is formed after the metal layer is formed on the surface of the metal IfIL electrode, oxidation of the gold PAt electrode is prevented and good forward characteristics are obtained.
（３）前記（１１、＋２１の結果、電気的特性の良好な
半導体装置が製造可能となり、製品の歩留りが向上する
。(3) As a result of the above (11, +21), it becomes possible to manufacture a semiconductor device with good electrical characteristics, and the yield of the product improves.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが２本発明は前記実施例に限定さ４るも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically described above based on Examples, it is to be noted that the present invention is not limited to the above-mentioned Examples, and that various changes can be made without departing from the gist thereof. Not even.
たとえば、金属電極の表面に形成される金属層を除去せ
ずに、そのまま積層宵１極として用いることも可能であ
る。For example, the metal layer formed on the surface of the metal electrode can be used as a stacked electrode without removing it.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるショットキ・バリア
・ダイオードの製造方法に適用した場合について説明し
たが、それに限定されるものではなく、たとえば、安定
なショット接合を必要とする半導体装置等の製造に広く
適用できる。The above explanation has mainly been about the case where the invention made by the present inventor is applied to the manufacturing method of Schottky barrier diodes, which is the background field of application, but the invention is not limited to this. It can be widely applied to the manufacture of semiconductor devices etc. that require shot bonding.
第１図（ａ）ないしくｄ） ｋ’！、本発明の一実施例
であるショットキ・バリア・ダイオードの製造方法を工
程順に示す断面図。
第２図（ａ）ないしｔｅｌは本発明の他の実施例である
ショットキ・バリア・ダイオードの製造方法を工程順に
示す断面図である。
１・・・シリコン基板、２・・・エピタキシャル層、３
金属電極層、３ａ・・・金回電極、４・・・絶縁膜、５
・・・取り出し電極形成窓、６・・・取り用し電極、’
１，７ａ・・・ショットキ・バリア・ダイオード、８・
・・金属層、８ａ・・・酸化防止層。
代理人 弁理士 高 橋 明 夫
）、
（、パ
３．４−゛づ・
第 １ 図
６反）Figure 1 (a) or d) k'! FIG. 1 is a cross-sectional view showing a method for manufacturing a Schottky barrier diode according to an embodiment of the present invention in order of steps. FIGS. 2A to 2C are cross-sectional views showing a method for manufacturing a Schottky barrier diode according to another embodiment of the present invention in the order of steps. 1... Silicon substrate, 2... Epitaxial layer, 3
Metal electrode layer, 3a... Gold electrode, 4... Insulating film, 5
... Take-out electrode forming window, 6... Take-out electrode,'
1,7a... Schottky barrier diode, 8.
...Metal layer, 8a...Antioxidation layer. (Representative Patent Attorney Akio Takahashi), (Page 3.4-゛zu, Part 1, Figure 6)
Claims (1)
る半導体装置の製造方法において、絶縁膜形成前に金属
電極を形成することを特徴とする。 半導体装置の製造方法。 ２、絶縁膜形成前に金属電極表面に金属層を形成するこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
の製造方法。 ３、半導体装置がショットキ・バリア・ダイオードであ
ることを特徴とする特許請求の範囲第１項記載の半導体
装置の製造方法。[Claims] 1. A method for manufacturing a semiconductor device in which a metal electrode is partially attached to one main surface of a semiconductor, characterized in that the metal electrode is formed before forming an insulating film. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a metal layer is formed on the surface of the metal electrode before forming the insulating film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a Schottky barrier diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11293984A JPS60257182A (en) | 1984-06-04 | 1984-06-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11293984A JPS60257182A (en) | 1984-06-04 | 1984-06-04 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60257182A true JPS60257182A (en) | 1985-12-18 |
Family
ID=14599277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11293984A Pending JPS60257182A (en) | 1984-06-04 | 1984-06-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60257182A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003258271A (en) * | 2002-03-01 | 2003-09-12 | Shindengen Electric Mfg Co Ltd | Silicon carbide schottky diode and manufacturing method of the same |
| JP2013008783A (en) * | 2011-06-23 | 2013-01-10 | Sanken Electric Co Ltd | Method of manufacturing semiconductor device, and semiconductor device |
-
1984
- 1984-06-04 JP JP11293984A patent/JPS60257182A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003258271A (en) * | 2002-03-01 | 2003-09-12 | Shindengen Electric Mfg Co Ltd | Silicon carbide schottky diode and manufacturing method of the same |
| JP2013008783A (en) * | 2011-06-23 | 2013-01-10 | Sanken Electric Co Ltd | Method of manufacturing semiconductor device, and semiconductor device |
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