JPS62155539A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62155539A
JPS62155539A JP29691885A JP29691885A JPS62155539A JP S62155539 A JPS62155539 A JP S62155539A JP 29691885 A JP29691885 A JP 29691885A JP 29691885 A JP29691885 A JP 29691885A JP S62155539 A JPS62155539 A JP S62155539A
Authority
JP
Japan
Prior art keywords
wiring
electrode
diffusion layer
film
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29691885A
Other languages
Japanese (ja)
Inventor
Shigeru Ozora
大空 茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29691885A priority Critical patent/JPS62155539A/en
Publication of JPS62155539A publication Critical patent/JPS62155539A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve yield on manufacture and reliability by constituting a wiring electrode of a leading-out electrode, a side surface thereof is coated with an oxide film, and a wiring metal formed, coating the surface of the leading-out electrode. CONSTITUTION:A diffusion layer 12 consisting of an N-type impurity is shaped to the surface of a P-type silicon substrate 11, and an insulating film 13 composed of an silicon oxide film, etc. is formed onto the N-type diffusion layer 12. A leading-out electrode 14 connected to the N-type diffusion layer 12 through an opening section bored to the insulating film 13 and consisting of polycrystalline silicon is shaped onto the insulating film 13, and constitutes a wiring electrode 20 together with an aluminum film 15 as a wiring metal formed, coating the leading-out electrode 14. Silicon oxide 17 is shaped on the side surface of the leading-out electrode 14. 14A represents a polycrystalline silicon wiring, and organizes a metallic wiring 30 integrally formed with the wiring electrode 20 together with the aluminum film 15.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、半導体装置の配線電極の形成方法として、半導体
基板表面の拡散層からの電極引出し部に多結晶シリコン
からなる引出し電極を設けた後、アルミニウム等より成
る配線金属をその上方に配置することが行なわれている
。これは浅い拡散層を配線金属より保護する為である。
Conventionally, as a method for forming wiring electrodes in a semiconductor device, a lead electrode made of polycrystalline silicon is provided at an electrode lead-out portion from a diffusion layer on the surface of a semiconductor substrate, and then a wiring metal made of aluminum or the like is placed above it. It is being done. This is to protect the shallow diffusion layer from the wiring metal.

第3図は従来の配線電極構造を有する半導体装置の断面
図である。
FIG. 3 is a sectional view of a semiconductor device having a conventional wiring electrode structure.

第3図において11はP型シリコン基板、12はP型シ
リコン基板11表面に形成されたN型拡散層、13Aは
N型拡散層12を含むP型シリコン基板11表面に形成
された酸化シリコン膜であり、電極引出しの為の開孔部
が設けられている。
In FIG. 3, 11 is a P-type silicon substrate, 12 is an N-type diffusion layer formed on the surface of the P-type silicon substrate 11, and 13A is a silicon oxide film formed on the surface of the P-type silicon substrate 11 including the N-type diffusion layer 12. An opening is provided for drawing out the electrode.

以下配線電極の形成方法について説明する。A method for forming wiring electrodes will be described below.

まずN型拡散層12に、酸化シリコン膜13Aを含むP
型シリコン基板11表面に多結晶シリコンを気相成長法
により成長させたのち、ホトリソグラフィ技術により引
出し電極14及び多結晶シリコン配線14Aを形成する
。続いて、イオン注入技術により多結晶シリコン中へ不
純物を導入して導電体化した後、配線金属として、例え
ばアルミニウム膜15を蒸着又はスパッタリングにより
全面に被着する。続いて、ホトリソグラフィ技術により
引出し電極14及び多結晶シリコン配線14A以外のア
ルミニウム膜を除去する事により、引出し電極14とア
ルミニウム膜15からなる配線電極20及び多結晶シリ
コン配線14Aとアルミニウム膜15とからなる金属配
線30が完成する。
First, in the N-type diffusion layer 12, P containing the silicon oxide film 13A is formed.
After growing polycrystalline silicon on the surface of the mold silicon substrate 11 by vapor phase growth, the lead electrode 14 and the polycrystalline silicon wiring 14A are formed by photolithography. Subsequently, impurities are introduced into the polycrystalline silicon using ion implantation technology to make it conductive, and then, as a wiring metal, for example, an aluminum film 15 is deposited over the entire surface by vapor deposition or sputtering. Subsequently, by removing the aluminum film other than the extraction electrode 14 and the polycrystalline silicon wiring 14A using photolithography technology, the wiring electrode 20 consisting of the extraction electrode 14 and the aluminum film 15, the polycrystalline silicon wiring 14A, and the aluminum film 15 are removed. The metal wiring 30 is completed.

〔発明か解決しようとする問題点〕[The problem that the invention attempts to solve]

上述した従来構造の配線電極を有する半導体装置では以
下のような問題がある。
The semiconductor device having the wiring electrode of the conventional structure described above has the following problems.

(1)配線電極側面部での配線電極と多結晶シリコンの
反応で引出し電極内部の抵抗が不均一となる為配線電極
の寿命が短くなる。
(1) Due to the reaction between the wiring electrode and polycrystalline silicon at the side surface of the wiring electrode, the resistance inside the lead-out electrode becomes uneven, resulting in a shortened lifespan of the wiring electrode.

(2)酸化膜と引出し電極との界面の欠陥領域を通じて
配線金属が拡散層に侵入し拡散層のPN接合を破壊する
(2) Wiring metal invades the diffusion layer through the defective region at the interface between the oxide film and the extraction electrode, destroying the PN junction of the diffusion layer.

(3)エツチング工程に於て配線電極の側面で多結晶シ
リコン層が露出する場合、酸化膜と多結晶シリコンとの
界面から拡散層へ汚染物が侵入する為素子の寿命が短く
なる。
(3) If the polycrystalline silicon layer is exposed on the side surface of the wiring electrode during the etching process, contaminants will enter the diffusion layer from the interface between the oxide film and the polycrystalline silicon, thereby shortening the life of the device.

この為、半導体装置の製造歩留り及び信頼度は低下した
ものとなっていた。
For this reason, the manufacturing yield and reliability of semiconductor devices have decreased.

本発明の目的は、上記問題点を除去し、製造歩留り及び
信頼度の向上した半導体装置を提供することにある。
An object of the present invention is to eliminate the above-mentioned problems and provide a semiconductor device with improved manufacturing yield and reliability.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、−導電型半導体基板上に形成さ
れた逆導電型不純物の拡散層と、この拡散層上に形成さ
れた絶縁膜と、この絶縁膜上に形成されかつ絶縁膜に設
けられた開孔部を通して前記拡散層に接続する多結晶シ
リコンからなる引出し電極と引出し電極の表面を覆って
形成された配線金属からなる配線電極とを有する半導体
装置であって、前記配線金属と接する前記引出し電極の
側面が酸化膜で覆われているものである。
The semiconductor device of the present invention includes a diffusion layer of an opposite conductivity type impurity formed on a conductivity type semiconductor substrate, an insulating film formed on the diffusion layer, and a diffusion layer formed on the insulating film and provided on the insulating film. A semiconductor device comprising an extraction electrode made of polycrystalline silicon that is connected to the diffusion layer through a hole formed in the opening, and a wiring electrode made of wiring metal formed covering a surface of the extraction electrode, the wiring electrode being in contact with the wiring metal. The side surface of the extraction electrode is covered with an oxide film.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

第1図に於て、P型シリコン基板11表面にはN型不純
物からなる拡散層12が形成されており、このN型拡散
層12上には酸化シリコン膜等からなる絶縁膜13が形
成されている。
In FIG. 1, a diffusion layer 12 made of N-type impurities is formed on the surface of a P-type silicon substrate 11, and an insulating film 13 made of a silicon oxide film or the like is formed on this N-type diffusion layer 12. ing.

この絶縁膜13上には、絶縁膜13に設けられた開孔部
を通してN型拡散層12に接続する多結晶シリコンから
なる引出し電極14が形成されており、この引出し電極
14を覆って設けられた配線金属とし、てのアルミニウ
ム膜15と共に配線室%20を構成している。そして、
この引出し電極14の側面には酸化シリコン17が形成
されている、 尚、14Aは多結晶シリコン配線であり、アルミニウム
膜15と共に、配線電極20と一体的に形成される金属
配線30を構成している。
A lead electrode 14 made of polycrystalline silicon is formed on this insulating film 13 and is connected to the N-type diffusion layer 12 through an opening provided in the insulating film 13. The aluminum film 15 constitutes the wiring chamber %20. and,
Silicon oxide 17 is formed on the side surface of this extraction electrode 14. Note that 14A is a polycrystalline silicon wiring, which together with the aluminum film 15 constitutes a metal wiring 30 that is integrally formed with the wiring electrode 20. There is.

このように構成された本実施例に於ては、引出し電極1
4の側面に酸化シリコン膜17が形成されている為側面
からのアルミニウム15の引出し電極I\の影響はなく
なる。従って引出し電極14の内部抵抗は均一となり、
PN接合の破壊はなくなる。
In this embodiment configured in this way, the extraction electrode 1
Since the silicon oxide film 17 is formed on the side surface of the aluminum 15, the influence of the lead electrode I\ of the aluminum 15 from the side surface is eliminated. Therefore, the internal resistance of the extraction electrode 14 becomes uniform,
Breakdown of the PN junction is eliminated.

更に、エツチング工程に於て、引出し電極14の側面の
アルミニウム15が除去されても汚染物の侵入は酸化シ
リコン膜17により阻止される為、素子の寿命が短くな
ることはない。
Further, even if the aluminum 15 on the side surface of the extraction electrode 14 is removed in the etching process, the silicon oxide film 17 prevents contaminants from entering, so the life of the device will not be shortened.

次に、本実施例について製造方法について説明する。Next, a manufacturing method for this example will be explained.

第2図(a)〜(c)は本発明の一実施例の製造方法を
説明する為の工程順に示した半導体チ・ツブの断面図で
ある。
FIGS. 2(a) to 2(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.

まず第2図(a)に示すように、P型シリコン基板11
上にN型拡散層12、酸化シリコン膜等からなる絶縁膜
13を形成したのち、絶縁膜13の所定部分に開孔部を
形成する。続いて全面にCVD法により多結晶シリコン
膜及び窒化シリコン膜16を順次堆積させたのち、バタ
ーニングし、多結晶シリコン膜からなる引出し電極14
を形成する。尚、14Aは金属配線30を構成する多結
晶シリコン配線である。
First, as shown in FIG. 2(a), a P-type silicon substrate 11
After forming an N-type diffusion layer 12 and an insulating film 13 made of a silicon oxide film or the like thereon, openings are formed in predetermined portions of the insulating film 13. Subsequently, a polycrystalline silicon film and a silicon nitride film 16 are successively deposited on the entire surface by CVD, and then buttered to form an extraction electrode 14 made of a polycrystalline silicon film.
form. Note that 14A is a polycrystalline silicon wiring that constitutes the metal wiring 30.

次に、第2図(b)に示すように、窒化シリコン膜16
をマスクとして熱酸化を行ない引出し電極14の側面に
酸化シリコン膜17を形成する。
Next, as shown in FIG. 2(b), the silicon nitride film 16
Using as a mask, thermal oxidation is performed to form a silicon oxide film 17 on the side surface of the extraction electrode 14.

この時、同時に多結晶シリコン配線14Aの側面にも酸
化シリコン膜17が形成される。
At this time, a silicon oxide film 17 is simultaneously formed on the side surface of the polycrystalline silicon wiring 14A.

次に、第2図(c)に示すように、窒化シリコン膜16
を熱リン酸溶液を用いて除去する。続いてイオン注入法
により引出し電極14及び多結晶シリコン配線14Aに
不純物を導入して導体化する、 次に第1図に示したように、全面にアルミニウムを蒸着
法又はスバ・ツタリング法により被着したのちパターニ
ングし、引出し電極14とアルミニウム膜15とからな
る配線電極20を形成する。
Next, as shown in FIG. 2(c), the silicon nitride film 16
is removed using hot phosphoric acid solution. Next, impurities are introduced into the extraction electrode 14 and the polycrystalline silicon wiring 14A by ion implantation to make them conductive. Next, as shown in FIG. 1, aluminum is deposited on the entire surface by vapor deposition or sputtering. Thereafter, patterning is performed to form a wiring electrode 20 consisting of a lead electrode 14 and an aluminum film 15.

この時同時に多結晶シリコン配線14Aとアルミニウム
膜】5とからなる金属配線30も配線電極20と一体的
に形成される。
At the same time, a metal wiring 30 consisting of the polycrystalline silicon wiring 14A and the aluminum film 5 is also formed integrally with the wiring electrode 20.

尚、上記実施例に於てはP型シリコン基板を用いた場合
について説明したが、N型シリコン基板を用いてもよい
事は勿論である。
Although the above embodiments have been described using a P-type silicon substrate, it goes without saying that an N-type silicon substrate may also be used.

〔発明の効果J 以上説明した様に本発明は、側面が酸化膜で覆われた引
出し電極と、この表面を覆って形成された配線金属力)
ら配線電極を構成することにより以下の様な効果がある
[Effect of the invention J As explained above, the present invention provides an extraction electrode whose side surface is covered with an oxide film, and a wiring metal layer formed covering this surface)
By configuring the wiring electrodes, the following effects can be obtained.

(1)引出し電極の内部抵抗が均一化される為、配線電
極の寿命が長くなる。
(1) Since the internal resistance of the lead electrode is made uniform, the life of the wiring electrode is extended.

く2)拡散層への配線金属の侵入が阻止される為、PN
接合が破壊されることがなくなる。
2) Since the penetration of wiring metal into the diffusion layer is prevented, PN
The bond will not be destroyed.

(3)工・・Iヂング工程に於て、配線電極の側面で配
線金属が除去されても汚染物の侵入は酸化膜によって阻
止される為、素子の寿命は短くなることはない。
(3) Process: Even if wiring metal is removed from the side surfaces of wiring electrodes in the I-ding process, the oxide film prevents contaminants from entering, so the life of the element will not be shortened.

以上の事から半導体装置の製造歩留及び信顆度を著しく
向上させることができる。
As a result of the above, the manufacturing yield and reliability of semiconductor devices can be significantly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の断面図、第2図(a)〜(
C)は第1図の実施例の製造方法を説明する為の工程順
に示した半導体チップの断面図、第3図は従来の半導体
装置の一例の断面図である1・・・P型シリコン基板、
12・・・N型拡散層、13・・・絶縁膜、13A・・
・酸化シリコン膜、14・・・引出し電極、14A・・
・多結晶シリコン配線、15・・・アルミニウム膜、1
6窒化シリコン膜、17酸化シリコン膜、20・・・配
線電極、30・・・金属配線。
FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS. 2(a) to (
C) is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the embodiment of FIG. 1, and FIG. 3 is a cross-sectional view of an example of a conventional semiconductor device. 1... P-type silicon substrate ,
12... N-type diffusion layer, 13... Insulating film, 13A...
・Silicon oxide film, 14... Leading electrode, 14A...
・Polycrystalline silicon wiring, 15...aluminum film, 1
6 silicon nitride film, 17 silicon oxide film, 20... wiring electrode, 30... metal wiring.

Claims (1)

【特許請求の範囲】[Claims] 一導電型半導体基板上に形成された逆導電型不純物の拡
散層と、該拡散層上に形成された絶縁膜と、該絶縁膜上
に形成されかつ絶縁膜に設けられた開孔部を通して前記
拡散層に接続する多結晶シリコンからなる引出し電極と
該引出し電極の表面を覆って形成された配線金属からな
る配線電極とを有する半導体装置において、前記配線金
属と接する前記引出し電極の側面が酸化膜で覆われてい
る事を特徴とする半導体装置。
A diffusion layer of an opposite conductivity type impurity formed on a semiconductor substrate of one conductivity type, an insulating film formed on the diffusion layer, and an opening formed on the insulating film and provided in the insulating film. In a semiconductor device having an extraction electrode made of polycrystalline silicon connected to a diffusion layer and a wiring electrode made of wiring metal formed covering the surface of the extraction electrode, a side surface of the extraction electrode in contact with the wiring metal is formed with an oxide film. A semiconductor device characterized by being covered with.
JP29691885A 1985-12-27 1985-12-27 Semiconductor device Pending JPS62155539A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29691885A JPS62155539A (en) 1985-12-27 1985-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29691885A JPS62155539A (en) 1985-12-27 1985-12-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62155539A true JPS62155539A (en) 1987-07-10

Family

ID=17839855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29691885A Pending JPS62155539A (en) 1985-12-27 1985-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62155539A (en)

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