JPH0476208B2 - - Google Patents
Info
- Publication number
- JPH0476208B2 JPH0476208B2 JP20131683A JP20131683A JPH0476208B2 JP H0476208 B2 JPH0476208 B2 JP H0476208B2 JP 20131683 A JP20131683 A JP 20131683A JP 20131683 A JP20131683 A JP 20131683A JP H0476208 B2 JPH0476208 B2 JP H0476208B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- diffusion layer
- opening
- present
- plane orientation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 26
- 238000009792 diffusion process Methods 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 1
- 230000035515 penetration Effects 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は、Si（シリコン）基板表面の拡散層と
接続する電極材料の突き抜けを改良した半導体装
置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which penetration of an electrode material connected to a diffusion layer on the surface of a Si (silicon) substrate is improved.
［発明の技術的背景］
従来、半導体装置は、例えば第１図ａ，ｂに示
すように製造されている。まず、面方位１００の
半導体基板１表面に拡散層２を形成した後、基板
１上に拡散層２を形成した後、基板１上に絶縁膜
３を形成する。つづいて、前記拡散層２に対応す
る絶縁膜３部分を選択的に開口し、開口部４を形
成する。次いで、全面に例えばＡを堆積した
後、パターニングし、開口部４を介して前記拡散
層２に接続するＡ配線５を形成する。[Technical Background of the Invention] Conventionally, semiconductor devices have been manufactured as shown in FIGS. 1a and 1b, for example. First, a diffusion layer 2 is formed on the surface of a semiconductor substrate 1 having a plane orientation of 100, and then the diffusion layer 2 is formed on the substrate 1, and then an insulating film 3 is formed on the substrate 1. Subsequently, a portion of the insulating film 3 corresponding to the diffusion layer 2 is selectively opened to form an opening 4. Next, after depositing, for example, A on the entire surface, patterning is performed to form an A wiring 5 connected to the diffusion layer 2 through the opening 4.
［背景技術の問題点］
しかしながら、前述した製造方法によれば、拡
散層２の深さが浅くになるに伴なつて、開口部２
周辺部でのストレスによつてＡ原子が基板１内
へ拡散、移動するいわゆるＡの突き抜け現象が
生ずる。これは、１００面では、開口部３周辺と
基板１との接触領域でのストレス緩和が大きいた
め、vacancyあるいはdislocation発生の促進が容
易となることに起因する。[Problems with the Background Art] However, according to the manufacturing method described above, as the depth of the diffusion layer 2 becomes shallower, the opening 2 becomes smaller.
A so-called A penetration phenomenon occurs in which A atoms diffuse and move into the substrate 1 due to stress in the peripheral area. This is because, in the case of 100 planes, stress relaxation is large in the contact area between the periphery of the opening 3 and the substrate 1, so that the occurrence of vacancy or dislocation is facilitated.
［発明の目的］
本発明は上記事情に鑑みてなされたもので、電
極取出し用の開口部から露出する基板の表面部分
をエツチング除去して開口部の周辺部の基板の面
方位を変えることによつて、配線材料の突き抜け
を防止し得る半導体装置の製造方法を提供するこ
とを目的とするものである。[Object of the Invention] The present invention has been made in view of the above circumstances, and involves etching away the surface portion of the substrate exposed from the electrode extraction opening to change the surface orientation of the substrate around the opening. Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent penetration of wiring material.
［発明の概要］
本発明は、表面に拡散層を有する面方位１００
のSi基板上に、前記拡散層に対応する部分に開口
部を有した絶縁膜を形成した後、前記開口部から
露出する基板の表面部分を選択的にエツチング除
去して前記開口部の周辺部の基板の面方位を１１
１に変えることによつて、後工程で形成される電
極材料による突き抜け現象を阻止することを図つ
たことを骨子とするものである。[Summary of the Invention] The present invention provides a surface orientation 100 having a diffusion layer on the surface.
After forming an insulating film having an opening in a portion corresponding to the diffusion layer on a Si substrate, the surface portion of the substrate exposed from the opening is selectively etched to remove the peripheral area of the opening. The plane orientation of the substrate is 11
1, the main idea is to prevent the punch-through phenomenon caused by the electrode material formed in a subsequent process.
［発明の実施例］
以下、本発明の一実施例を第２図ａ〜ｃ及び第
３図を参照して説明する。[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 2a-c and 3.
まず、面方位１００のSi基板１１の表面に拡散
層１２を形成した後、基板１１上に絶縁膜１３を
形成した。つづいて、前記拡散層１２に対応する
絶縁膜１３部分を選択的に開口し、開口部１４を
形成した（第２図ａ図示）。次いで、この開口部
１４から露出する基板１１の表面部分を例えば
KOHを用いてエツチング除去した。この際、エ
ツチング深さは前記拡散層１２の深さより浅い範
囲とする。その結果、開口部１４の周辺部の基板
面１６の面方位は１１１となり、その他の基板面
の面方位は１００のままであつた（第２図ｂ及び
第３図図示）。なお、第３図は第２図ｂの平面図
を示す。しかる後、全面にＡを蒸着し、パター
ニングすることによつて、前記開口部１４を介し
て拡散層１２に接続するＡ配線１５を形成した
（第３図図示）。 First, a diffusion layer 12 was formed on the surface of a Si substrate 11 with a surface orientation of 100, and then an insulating film 13 was formed on the substrate 11. Subsequently, a portion of the insulating film 13 corresponding to the diffusion layer 12 was selectively opened to form an opening 14 (as shown in FIG. 2A). Next, the surface portion of the substrate 11 exposed through the opening 14 is
It was removed by etching using KOH. At this time, the etching depth is set to be shallower than the depth of the diffusion layer 12. As a result, the surface orientation of the substrate surface 16 around the opening 14 was 111, and the surface orientation of the other substrate surfaces remained 100 (as shown in FIGS. 2b and 3). Note that FIG. 3 shows a plan view of FIG. 2b. Thereafter, A was deposited on the entire surface and patterned to form an A wiring 15 connected to the diffusion layer 12 through the opening 14 (as shown in FIG. 3).
しかして、本発明によれば、絶縁膜１３の開口
部１４から露出する面方位１００のSi基板１１の
表面をKOHによりエツチング除去して開口部１
４の周辺部の基板面１６の面方位を１１１とした
後、Ａの蒸着、パターニングを行つてＡ配線
１５を形成するため、Ａによる突き抜け現象を
従来と比べて著しく回避できる。その結果、歩留
まりを大幅に改善できる。事実、基板表面の拡散
層表面をエツチングしない従来のダイオードの逆
方向特性、及び本発明のようにエツチングして面
方位を変えた場合のダイオードの逆方向特性につ
いて、ウエハに形成された複数の素子を対象にし
て測定したところ（但し、測定した素子数が全て
良品であれば100％とした）、従来20〜30％であつ
たのが、70〜80％にまで大幅に改善できた。な
お、図中のａは従来を、ｂは本発明の場合のグラ
フを夫々示す。同図より、本発明が従来と比べ優
れていることが確認できる。 According to the present invention, the surface of the Si substrate 11 with a plane orientation of 100 exposed through the opening 14 of the insulating film 13 is removed by etching with KOH.
After setting the surface orientation of the substrate surface 16 at the peripheral portion of the substrate 4 to 111, vapor deposition and patterning of A are performed to form the A wiring 15. Therefore, the punch-through phenomenon caused by A can be significantly avoided compared to the conventional method. As a result, yield can be significantly improved. In fact, regarding the reverse direction characteristics of a conventional diode in which the surface of the diffusion layer on the substrate surface is not etched, and the reverse direction characteristics of a diode when the surface orientation is changed by etching as in the present invention, the characteristics of multiple elements formed on a wafer are as follows. (however, if all the measured elements were good, it was considered 100%), and the conventional rate of 20-30% was significantly improved to 70-80%. Note that in the figure, a shows the conventional graph, and b shows the graph of the present invention. From the figure, it can be confirmed that the present invention is superior to the conventional one.
なお、上記実施例では開口部から露出する基板
をエツチングする手段としてKOHを用いたが、
これに限らず、ある特定面を選択露出できる薬品
あるいはエツチング技術を用いてもよい。 In the above example, KOH was used as a means for etching the substrate exposed through the opening.
The present invention is not limited to this, and chemicals or etching techniques that can selectively expose a specific surface may be used.
［発明の効果］
以上詳述した如く本発明によれば、配線材料の
突き抜けを防し得る歩留まりの大きい半導体装置
の製造方法を提供できるものである。[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device with a high yield and which can prevent penetration of wiring material.
第１図ａは従来の半導体装置の断面図、同図ｂ
は同図ａの平面図、第２図ａ〜ｃは本発明の一実
施例に係る半導体装置の製造方法を工程順に示す
断面図、第３図は第２図ｂの平面図、第４図は従
来及び本発明による半導体装置の歩留まりを示す
棒グラフである。
１１……１００Si基板、１２……拡散層、１４
……開口部、１５……Ａ配線、１６……基板
面。
Figure 1a is a cross-sectional view of a conventional semiconductor device, and Figure 1b is a cross-sectional view of a conventional semiconductor device.
2 is a plan view of FIG. is a bar graph showing the yield of semiconductor devices according to the prior art and the present invention. 11...100Si substrate, 12...diffusion layer, 14
...opening, 15...A wiring, 16...board surface.
Claims (1)
る工程と、この基板上に前記拡散層に対応する部
分に開口部を有した絶縁膜を形成する工程と、前
記開口部から露出する基板の表面部分を選択的に
エツチングして前記開口部の周辺部の基板の面方
位を１１１に変える工程と、全面に金属を蒸着し
た後、パターニングして配線を形成する工程とを
具備することを特徴とする半導体装置の製造方
法。1. A step of forming a diffusion layer on the surface of a Si substrate with a plane orientation of 100, a step of forming an insulating film having an opening in a portion corresponding to the diffusion layer on this substrate, and a step of forming a diffusion layer on the surface of a Si substrate with a plane orientation of 100. It is characterized by comprising a step of selectively etching the surface portion to change the plane orientation of the substrate in the peripheral portion of the opening to 111, and a step of vapor depositing metal on the entire surface and then patterning it to form wiring. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58201316A JPS6092614A (en) | 1983-10-27 | 1983-10-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58201316A JPS6092614A (en) | 1983-10-27 | 1983-10-27 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6092614A JPS6092614A (en) | 1985-05-24 |
| JPH0476208B2 true JPH0476208B2 (en) | 1992-12-03 |
Family
ID=16438984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58201316A Granted JPS6092614A (en) | 1983-10-27 | 1983-10-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6092614A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0248221A (en) * | 1988-08-08 | 1990-02-19 | Mazda Motor Corp | Door structure of vehicle |
| JP2727902B2 (en) * | 1993-01-18 | 1998-03-18 | 日本電気株式会社 | Al contact structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53166222U (en) * | 1977-06-01 | 1978-12-26 | ||
| JP2556166Y2 (en) * | 1990-01-23 | 1997-12-03 | セイレイ工業株式会社 | Operator seat mounting mechanism |
| JP2006192961A (en) * | 2005-01-11 | 2006-07-27 | Seirei Ind Co Ltd | Seat supporting structure |
-
1983
- 1983-10-27 JP JP58201316A patent/JPS6092614A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6092614A (en) | 1985-05-24 |
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