JPH01108726A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01108726A JPH01108726A JP62267292A JP26729287A JPH01108726A JP H01108726 A JPH01108726 A JP H01108726A JP 62267292 A JP62267292 A JP 62267292A JP 26729287 A JP26729287 A JP 26729287A JP H01108726 A JPH01108726 A JP H01108726A
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- photoresist
- oxide film
- silicon
- mesa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 10
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 6
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract description 6
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- 230000002159 abnormal effect Effects 0.000 abstract description 8
- 238000007747 plating Methods 0.000 abstract description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052737 gold Inorganic materials 0.000 abstract description 7
- 239000010931 gold Substances 0.000 abstract description 7
- 229910052709 silver Inorganic materials 0.000 abstract description 7
- 239000004332 silver Substances 0.000 abstract description 7
- 238000006552 photochemical reaction Methods 0.000 abstract description 2
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 2
- 150000001875 compounds Chemical class 0.000 abstract 1
- 239000000126 substance Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Weting (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特にメサ状に
シリコン基板をエツチングする方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of etching a silicon substrate into a mesa shape.
従来、メサ構造を有し、かつバンブ電極を有する半導体
装置においては、バンブ電極を形成する前にメサ構造を
形成するため、バンプ電極形成時には、電極の近傍にメ
サ段差が存在していた。Conventionally, in a semiconductor device having a mesa structure and a bump electrode, since the mesa structure is formed before forming the bump electrode, a mesa step exists near the electrode when the bump electrode is formed.
この様子を、バンブ電極を有する半導体装置としてダイ
オードを例にとって説明する。まず第３図（ａ）に示す
ように、シリコン基板１上にシリコン酸化Ｊｌ！２を形
成しその開口部に金電極３を形成する。このあとメサ構
造を得るためにフォトレジスト４によりシリコン基板を
エツチングする（第３図（ｂ））。このエツチング量は
組立上の問題から５０μｍ程度と大きいものである。フ
ォトレジスト４を除去し第３図（Ｃ）に示すようなメサ
構造を形成した後、第３図（ｄ）に示すようにフォトレ
ジスト６をバターニングし、金電極３上に銀バンプ電極
７を形成する。この時、フォトレジスト６はスピンナー
（回転塗布様）を用いて形成するため、メサ段差の所で
フォトレジストが薄くなり、そこから異常メツキ部分１
１が発生する。この異常・メツキ部分１１はフォトレジ
ストを除去しても第３図（ｅ）に示すように残るため、
外観不良ま電極ショート不良等の原因となり、歩留り上
の大きな問題となっていた。This situation will be explained using a diode as an example of a semiconductor device having a bump electrode. First, as shown in FIG. 3(a), silicon oxide Jl! 2 and a gold electrode 3 is formed in the opening thereof. Thereafter, the silicon substrate is etched using photoresist 4 to obtain a mesa structure (FIG. 3(b)). This etching amount is as large as approximately 50 μm due to assembly problems. After removing the photoresist 4 and forming a mesa structure as shown in FIG. 3(C), the photoresist 6 is patterned as shown in FIG. 3(d), and a silver bump electrode 7 is formed on the gold electrode 3. form. At this time, since the photoresist 6 is formed using a spinner (rotary coating type), the photoresist becomes thinner at the mesa step, and from there the abnormal plating area 1
1 occurs. This abnormal/plated part 11 remains as shown in FIG. 3(e) even if the photoresist is removed.
This causes poor appearance and electrode short-circuit defects, which poses a major problem in terms of yield.
本発明の半導体装置の製造゛方法は、メサ構造を得るた
めに弗酸、硝酸系のエツチング液でシリコン基板をエツ
チング液る際、エツチングの終了時に表面に紫外線を含
む光を照射することにより、シリコン表面に化成酸化膜
を形成し、メサエッチング部を絶縁膜で被覆することを
特徴とする。The method for manufacturing a semiconductor device of the present invention is such that when a silicon substrate is etched with a hydrofluoric acid or nitric acid-based etching solution to obtain a mesa structure, the surface is irradiated with light containing ultraviolet rays at the end of etching. It is characterized by forming a chemical oxide film on the silicon surface and covering the mesa etched part with an insulating film.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例であるダイオードの製造
工程を示す断面図である。まず、第１図（ａ）に示すよ
うにシリコン基板１上にシリコン酸化膜２を形成し、そ
の開口部に金電極３を形成する０次にメサ構造を得るた
めに第１図（ｂ）に示すようにフォトレジスト４をマス
クにして弗酸、硝酸系のエツチング液によりシリコン基
板１をエツチングする。このエツチングの終了の時点で
シリコン基板に紫外線を含む光を照射すると、光化学反
応により、エツチング液に曝されたシリコン基板表面に
化成酸化膜５が形成される。このあと第１図（Ｃ）のよ
うにフォトレジスト４を除去する０次に第１°図（ｄ）
のようにフォトレジスト６をパターニングし、金電極３
の上に銀バンプ電極７を形成する。この際フォトレジス
ト６がメサ段差部で薄くなっても化成酸化膜５があるの
で異常メツキされない。FIG. 1 is a sectional view showing the manufacturing process of a diode according to a first embodiment of the present invention. First, as shown in FIG. 1(a), a silicon oxide film 2 is formed on a silicon substrate 1, and in order to obtain a zero-order mesa structure in which a gold electrode 3 is formed in the opening of the silicon oxide film 2, as shown in FIG. 1(b). As shown in FIG. 3, the silicon substrate 1 is etched using a hydrofluoric acid or nitric acid based etching solution using the photoresist 4 as a mask. When the silicon substrate is irradiated with light containing ultraviolet rays at the end of this etching, a chemical oxide film 5 is formed on the surface of the silicon substrate exposed to the etching solution due to a photochemical reaction. After this, the photoresist 4 is removed as shown in Figure 1 (C).
The photoresist 6 is patterned as shown in FIG.
A silver bump electrode 7 is formed thereon. At this time, even if the photoresist 6 becomes thinner at the mesa step portion, abnormal plating will not occur because the chemical oxide film 5 is present.
第２図は、本発明の第２の実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the invention.
まず、第２図（ａ）に示すようにシリコン基板２１にＰ
Ｎ接合２２を形成し、シリコン窒化膜２３をマスクにし
てシリコン基板をエツチングしメサ部２４を形成する。First, as shown in FIG. 2(a), P is applied to the silicon substrate 21.
An N junction 22 is formed, and the silicon substrate is etched using the silicon nitride film 23 as a mask to form a mesa portion 24.
この時、エツチング深さはＰＮ接合部より深くし、エツ
チング終了時点で光照射を行ない、化成酸化膜２５を形
成する。こうしてメサ部２４を形成し、このメサ部でＰ
Ｎ接合２２を切るために、接合耐圧の向上が得られる。At this time, the etching depth is set to be deeper than the PN junction, and at the end of the etching, light is irradiated to form a chemical oxide film 25. In this way, a mesa portion 24 is formed, and in this mesa portion, P
Since the N junction 22 is cut, the junction breakdown voltage can be improved.
この後、第２図（ｂ）に示すようにシリコン窒化膜２３
を熱リン酸にて除去し、ＣＶＤ法によりシリコン酸化膜
２６を形成する。この時、シリコン酸化膜２６のステッ
プカバレッジが悪いため、メサ部の特に側面にはほとん
ど膜が成長しない、続いて、第２図（Ｃ）に示すように
シリコン酸化膜２６にコンタクトホール２７を形成し、
金電極２８を形成する。この後、第２図（ｄ）のように
銀メツキを行なって銀バンプ電極２９が形成される。銀
バンプ電極形成時、従来はメサ部の所のシリコン酸化膜
のステップカバレッジが悪く段差部に異常メツキされた
が、化成酸化膜形成後は異常メツキは皆無となった。After this, as shown in FIG. 2(b), the silicon nitride film 23
is removed using hot phosphoric acid, and a silicon oxide film 26 is formed by CVD. At this time, since the step coverage of the silicon oxide film 26 is poor, almost no film grows, especially on the side surfaces of the mesa part.Continuously, a contact hole 27 is formed in the silicon oxide film 26 as shown in FIG. 2(C). death,
A gold electrode 28 is formed. Thereafter, silver plating is performed to form silver bump electrodes 29 as shown in FIG. 2(d). When silver bump electrodes were formed, conventionally the step coverage of the silicon oxide film at the mesa part was poor and abnormal plating occurred at the step part, but after forming the chemical oxide film, there was no abnormal plating.
以上説明したように、本発明はシリコン基板を弗酸、硝
酸系のエツチング液でエツチングする際、エツチング終
了時に光を照射することによりシリコン表面に化成酸化
膜を形成し、この絶縁膜によりメサ段差部での異常メツ
キの発生を防止し、信頼性、歩留りの向上ができる効果
がある。As explained above, in the present invention, when a silicon substrate is etched with a hydrofluoric acid or nitric acid-based etching solution, a chemical oxide film is formed on the silicon surface by irradiating light at the end of etching, and this insulating film eliminates mesa steps. This has the effect of preventing the occurrence of abnormal plating in the parts and improving reliability and yield.
第１図（ａ）〜（ｅ）は本発明の第１の実施例であるダ
イオードの製造工程を示す断面図、第２図（ａ）〜（ｄ
）は本発明の第２の実施例の製造工程を示す断面図、第
３図（ａ）〜（ｅ）は従来のダイオードの製造工程を示
す断面図である。
１．２１・・・シリコン基板、２．２６・・・シリコン
酸化膜、３，２８・・・金電極、４．６・・・フォトレ
ジスト、５，２５・・・化成酸化膜、７，２９・・・銀
バンプ電極、１１・・・異常メツキ部分、２２・・・Ｐ
Ｎ接合、２３・・・シリコン窒化膜、２４・・・メサ部
、２７・・・コンタクトホール。FIGS. 1(a) to (e) are cross-sectional views showing the manufacturing process of a diode according to the first embodiment of the present invention, and FIGS. 2(a) to (d)
) is a sectional view showing the manufacturing process of the second embodiment of the present invention, and FIGS. 3(a) to 3(e) are sectional views showing the manufacturing process of a conventional diode. 1.21... Silicon substrate, 2.26... Silicon oxide film, 3, 28... Gold electrode, 4.6... Photoresist, 5, 25... Chemical oxide film, 7, 29 ...Silver bump electrode, 11...Abnormal plating part, 22...P
N junction, 23... silicon nitride film, 24... mesa portion, 27... contact hole.
Claims (1)
エッチングする際、そのエッチング終点近傍で紫外線を
含む光を照射することを特徴とする半導体装置の製造方
法。A method for manufacturing a semiconductor device, which comprises irradiating a silicon substrate with ultraviolet light in the vicinity of the etching end point when etching a silicon substrate using a hydrofluoric acid or nitric acid-based etching solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62267292A JPH01108726A (en) | 1987-10-21 | 1987-10-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62267292A JPH01108726A (en) | 1987-10-21 | 1987-10-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01108726A true JPH01108726A (en) | 1989-04-26 |
Family
ID=17442801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62267292A Pending JPH01108726A (en) | 1987-10-21 | 1987-10-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01108726A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5702578A (en) * | 1992-07-06 | 1997-12-30 | Mazda Motor Corporation | Method of applying a surface coating |
| US5976677A (en) * | 1992-04-06 | 1999-11-02 | Mazda Motor Corporation | Surface coating and method of applying the same |
-
1987
- 1987-10-21 JP JP62267292A patent/JPH01108726A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5976677A (en) * | 1992-04-06 | 1999-11-02 | Mazda Motor Corporation | Surface coating and method of applying the same |
| US5702578A (en) * | 1992-07-06 | 1997-12-30 | Mazda Motor Corporation | Method of applying a surface coating |
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