JPS60101946A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate head and thereby obtain flat surface by coating the entire surface including birds' head generated at an oxide film surface with the resist film, on the occasion of isolating element regions formed on the semiconductor substrate into islands by a selective oxide film, and executing the ion etching by utilizing that the resist film is this on the heads. CONSTITUTION:An N<+> type layer 2 is formed by the epitaxial growth method on a P type Si substrate 1, a field SiO2 film 6 which enters the substrate 1 is formed by the selective oxidation and the layer 2 is isolated like an island. Next, a P type base region 3 is formed by diffusion in the layer 2 formed like island and an N<+> type emitter region 4 is then formed in such region, thereby forming a semiconductor device. In this case, according to the selective oxidation, namely LOCOS method, the birds' beak 7 and birds' head 8 are generated at the surface of film 6 and thereby the surface becomes uneven. Therefore, the ion etching of Ar, etc. is carried out to the entire part utilizing that the entire part is coated with the resist film 9 and the film 9 is thin on the head 8 in order to eliminate the head 8 and make flat the surface.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, in particular, as an element isolation technique, selectively oxidizing L by using 8i3N4 as a mask.
Regarding the OCO8 method.

(2) Description of Prior Art Element isolation technology using the conventional LOCO8 method has been widely applied as a means for achieving higher miniaturization and higher performance of LSIs.

Figure m1 shows an example of a cross-sectional view of an fc bipolar transistor manufactured using the LOCOf9 method. An element region consisting of a collector N+/Nepi region 2, a base P region 3, and an emitter N+ region is formed on a P substrate 1, and finally a metal interconnection l1li! form 5. As is clear from this figure, LOC
The disadvantages of the O8 method are the birds' beak phenomenon that forms at the edge of the field oxide film 6 and the birds' heads that form on the surface of the field oxide film 6.
'head) 8 phenomenon has occurred. Bird's beef must be prevented in device miniaturization, while hard's head creates unevenness in the field oxide film, causing the device surface to lose its flatness. Therefore, if the metal wiring 5 is formed on the field oxide film 6 where such a bird's head is present, disconnection is likely to occur. In particular, the frequency of this phenomenon tends to increase in multilayer wiring. As a result, the chip yield has decreased and the cost has increased. (3) Detailed Description of the Invention The purpose of the present invention is to eliminate unevenness on the field oxide film and improve the flatness of the device surface. An object of the present invention is to provide a method for manufacturing a semiconductor device with improved performance.

(4) Structure of the Invention The present invention is characterized in that after the element is formed, a photoresist is applied to the entire surface of the oxide film to smooth the unevenness, and then etched with inert gas ions.

(5) Detailed description of the invention Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention, and FIG.
FIG. 2(d) is a diagram of each step constituting the present invention after circuit elements are formed, and FIG. 2(e) is a cross-sectional view of the final structure obtained by the present invention after metal wiring (one layer).

First, in FIG. 2(a), collectors N+ and Ne are placed on the P substrate 1.
pi region 2. Base P area 3. An emitter N+ region 4 and a field oxide film 6 for isolating each element and protecting the element surface are formed. 7 represents Bird's Peak and 8 represents Bird's Head. Up to now, the manufacturing process has been the usual LOCO8 method. Next, in FIG. 2(b), each area 2,
3. Apply resist 9 to the entire surface of 4 and the surface of noield oxide film 6.

As shown in the figure, the coating is applied thinly on the convex portions corresponding to the bird's head 8, and thickly on the four portions, and the plane of the resist 9 is approximately flat on the concave and convex portions.

Next, an inert gas of Ar6 is ionized on the upper surface of the resist 9, and ion etching (also referred to as sputter etching) is performed. Reactive ion etching and different silicone resists and n
The etching rate of the v-oxide film is approximately equal, so the device surface is etched uniformly. This situation is shown in Figure 2 (
Shown in C).

Finally, in Figure 2 ((1), ion etching is performed for an appropriate period of time to remove the remaining resist, etc.).
−. It can be seen that the bird's head 8 has been relaxed by the ion erasure.

Is it possible to add gold wiring 5 to a semiconductor device manufactured by such a process? The results are shown in FIG. 2(e). As a result, the level difference in the metal wiring on the surface of the bird's head 8 is greatly reduced, and the probability of the wiring breaking is also reduced.

FIG. 3 is a second embodiment of the present invention, which is a sectional view of the final structure after metal distribution. In this embodiment, oxidation is performed after the process shown in FIG.
This is an example in which contacts 11 and 12 made of i-W material are provided to improve the reliability of metal wiring. Even if the field oxide film is made thicker, the bird's head relaxation and flattening are not impaired, and the same effect as in the first embodiment is produced.

(6) Detailed Description of the Invention As described above, the present invention allows the bird's head in the LOCO8 method to be relaxed or eliminated by ion etching, thereby making it possible to manufacture a semiconductor device with no wiring breaks and a high yield.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the structure of a bipolar transistor (NPN) manufactured using the conventional LOCO8 method. FIG. 2 is a process sectional view showing an embodiment of the present invention.
) is a sectional view after the circuit element formation process, FIG. 2(b) is a resist coating process diagram, FIG. 2(C) is an ion etching process diagram,
FIG. 2 ((1) is a cross-sectional view after ion etching is completed, and FIG. 2(e) is a cross-sectional view of the structure after metal wiring is formed. FIG. 3 is a final structure showing the second embodiment of the present invention. It is a sectional view. 1... P substrate, 2... Collector N@N
epi area, 3...Base P area, 4...
...Emitter N region, 5...Metal wiring, 6.
... Field oxide film, 7 ... Bird's beak (bird's peak), 8 ... Bird's head (Bird's head), 9 ... Resist , 10...
...Inert gas ion, 11...Polysilicon contact, 12...TI-W contact. Agent Patent Attorney Susumu Uchihara 2 Ward (e) 23 Figure

Claims (1)

[Claims] A bird's head is visible on a part of the field oxide film.
The LOCO8 method, which generates a raised phenomenon in the form of an ead), has a step of applying a resist to the entire surface of the field oxide film after forming a circuit element, and a step of etching with active gas ions after applying the resist. A method for manufacturing a featured semiconductor device.