JPH067573B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH067573B2 JPH067573B2 JP58149036A JP14903683A JPH067573B2 JP H067573 B2 JPH067573 B2 JP H067573B2 JP 58149036 A JP58149036 A JP 58149036A JP 14903683 A JP14903683 A JP 14903683A JP H067573 B2 JPH067573 B2 JP H067573B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- silicon substrate
- oxidation resistant
- resistant material
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は，微細化に好適でかつ表面段差のない素子間分
離構造を有する半導体装置及びその製造方法に関するも
のである。Description: FIELD OF THE INVENTION The present invention relates to a semiconductor device having an element isolation structure which is suitable for miniaturization and has no surface step, and a manufacturing method thereof.
従来の素子間分離の製造方法としては，耐酸化膜のパタ
ーンを基板上に形成し，これをマスクにしてシリコン基
板の表面を選択的に熱酸化する選択酸化法がよく知られ
ている。しかし，この選択酸化法およびその方法によっ
て製造された半導体装置には次のような欠点がある。As a conventional manufacturing method for element isolation, a selective oxidation method is well known in which a pattern of an oxidation resistant film is formed on a substrate and the surface of the silicon substrate is selectively thermally oxidized by using this as a mask. However, the selective oxidation method and the semiconductor device manufactured by the method have the following drawbacks.
まず，第１の欠点は微細化の限界である。即ち，選択酸
化によって形成されるバーズビークの幅が選択酸化膜の
厚さと同程度であり，このバーズビーグの領域が素子面
積の有効な利用を妨げる。First, the first drawback is the limit of miniaturization. That is, the width of the bird's beak formed by the selective oxidation is about the same as the thickness of the selective oxide film, and the region of the bird's beak hinders effective use of the element area.
第２の欠点は，長時間の熱酸化を必要とすることであ
る。例えば１μｍの膜厚の選択酸化膜を形成するのに10
00℃のウェット酸化法で５〜７時間程度を必要とする。
これは生産性の妨げとなるばかりでなく，積層欠陥の発
生，不純物拡散層の不都合な拡散を引き起こす原因とな
る。The second drawback is the need for long-term thermal oxidation. For example, to form a selective oxide film with a thickness of 1 μm, 10
The wet oxidation method at 00 ° C requires about 5 to 7 hours.
This not only hinders productivity, but also causes stacking faults and undesired diffusion of the impurity diffusion layer.
第３の欠点は，必ずしも充分な表面平坦化が図れないこ
とである。通常の選択酸化法では，酸化膜厚の約1/2
が，シリコン中に埋置されるため，表面段差は酸化膜厚
の約1/2となる。この表面段差を減少させるため，シリ
コン基板表面をあらかじめ一部エッチングした後，選択
酸化膜を形成することにより，この選択選化膜をシリコ
ン基板内に全部埋め込むという方法が提案されている。
しかし，この方法を用いると，選択酸化膜の周辺部に，
バーズビークの他にバーズヘッドとよばれる突出部が形
成されてしまう。このため，この方法によっても，表面
平坦化は，必ずしも充分には図れない。The third drawback is that sufficient surface flatness cannot always be achieved. With the normal selective oxidation method, about 1/2 of the oxide film thickness
However, since it is embedded in silicon, the surface step is about 1/2 of the oxide film thickness. In order to reduce the surface step, a method has been proposed in which the surface of the silicon substrate is partially etched in advance and then a selective oxide film is formed so that the selective selection film is entirely embedded in the silicon substrate.
However, using this method,
In addition to the bird's beak, a protruding portion called a bird's head is formed. Therefore, even with this method, the surface cannot be flattened sufficiently.
［発明の目的］ 本発明の目的は、バーズビーク、バーズヘッドがなく、
酸化膜厚が厚く、結晶欠陥や不純物拡散層の不都合な拡
散がなく、かつ、表面段差のない微細な素子間分離構造
を有する半導体装置、及びそのような構造を低温短時間
で実現できる製造方法を提供することにある。[Object of the Invention] An object of the present invention is to eliminate bird's beak and bird's head,
A semiconductor device having a large oxide film thickness, no crystal defects or undesired diffusion of an impurity diffusion layer, and a fine element isolation structure having no surface step, and a manufacturing method capable of realizing such a structure at low temperature in a short time. To provide.
［発明の概要］ 上記目的を達成するために、本発明の半導体装置は、シ
リコン基板の表面の半導体素子が作り込まれている素子
領域であるシリコン領域の周辺に、シリコン酸化膜が上
記シリコン基板の表面から上記シリコン基板の内部に向
かって存在し、上記シリコン領域と上記シリコン酸化膜
領域との境界に絶縁層が介在する構造を有し、上記素子
領域の上記シリコン基板表面からの深さよりも深い領域
まで上記絶縁層が存在しかつ、上記絶縁層の表面に近い
部分が酸化シリコンからなり、残りの深い部分が上記シ
リコン基板の一部領域の熱酸化防止のため、上記一部領
域の表面側に形成された薄膜である耐酸化性材料からな
ることを特徴とする。[Summary of the Invention] In order to achieve the above-mentioned object, a semiconductor device of the present invention has a silicon oxide film on the periphery of a silicon region which is an element region in which a semiconductor element is formed on the surface of the silicon substrate. Exists toward the inside of the silicon substrate from the surface of, and has a structure in which an insulating layer is present at the boundary between the silicon region and the silicon oxide film region, and the depth of the element region from the silicon substrate surface is The insulating layer is present up to a deep region, and a portion close to the surface of the insulating layer is made of silicon oxide, and the remaining deep portion is a surface of the partial region for preventing thermal oxidation of the partial region of the silicon substrate. It is characterized by being made of an oxidation resistant material which is a thin film formed on the side.
また、本願発明の半導体装置の製造方法は、第１の耐酸
化性材料を表面に有するシリコン基板上に、第１の材料
を堆積した後パターン形成して半導体素子が作り込まれ
る領域以外の領域にある上記第１の材料を除去する第１
の工程と、この上に方向性を有する膜堆積法によって第
２の材料を全面に堆積する第２の工程と、エッチングに
よって上記第１の材料のパターンの縁に付着した上記第
２の材料を除去することにより、上記第１の材料と上記
第２の材料によって第１の溝を形成する第３の工程と、
上記第１の溝の底に露出した上記第１の耐酸化性材料を
表面に有するシリコン基板を上記半導体素子が作り込ま
れる領域の上記シリコン基板表面からの深さよりも深い
領域までエッチングして上記シリコン基板に第２の溝を
形成する第４の工程と、上記第２の材料を除去する第５
の工程と、上記第１の材料をマスクにしてこれに覆われ
ていない領域の上記第１の耐酸化性材料を除去する第６
の工程と、上記第１の材料を除去した後上記シリコン基
板に第２の耐酸化性材料を堆積することにより、上記シ
リコン基板の上記第２の溝の中に上記第２の耐酸化性材
料を充填するとともに、パターン形成された上記第１の
耐酸化性材料の上も上記第２の耐酸化性材料で被覆する
第７の工程と、方向性エッチングを行うことにより、パ
ターン形成された上記第１の耐酸化性材料の側壁および
上記第２の溝の中に充填した上記第２の耐酸化性材料を
残し、それ以外の領域に堆積された上記第２の耐酸化性
材料をエッチングして上記シリコン基板を露出する第８
の工程と、上記第１の耐酸化性材料で被覆していない上
記シリコン基板を陽極化成によって多孔質化する第９の
工程と、熱酸化によって上記多孔質シリコン領域を多孔
質シリコン酸化膜にする第１０の工程と、上記第２の溝
の中に充填した上記第２の耐酸化性材料の一部を上記半
導体素子が作り込まれる領域の上記シリコン基板表面か
らの深さよりも深い領域まで除去する第１１の工程と、
上記シリコン基板を熱酸化する第１２の工程と、上記第
２の溝の中に薄膜堆積法によって絶縁物または半導体材
料を充填し、表面を平坦にする第１３の工程を含むこと
を特徴とする。Further, according to the method of manufacturing a semiconductor device of the present invention, a region other than a region where a semiconductor element is formed by depositing the first material and then patterning the same on a silicon substrate having a first oxidation resistant material on the surface. Removing the first material in
And the second step of depositing the second material on the entire surface by the directional film deposition method, and the second material adhered to the edge of the pattern of the first material by etching. A third step of forming a first groove by removing the first material and the second material,
The silicon substrate having the surface of the first oxidation resistant material exposed at the bottom of the first groove is etched to a region deeper than the depth of the region in which the semiconductor element is formed from the surface of the silicon substrate. Fourth step of forming a second groove in the silicon substrate and fifth step of removing the second material
And a step of removing the first oxidation resistant material in a region not covered by the first material as a mask.
And removing the first material and depositing a second oxidation resistant material on the silicon substrate, thereby forming the second oxidation resistant material in the second groove of the silicon substrate. And a second step of covering the patterned first oxidation-resistant material with the second oxidation-resistant material as well as the pattern-formed first oxidation-resistant material. Etching the second oxidation resistant material deposited in the other regions, leaving the second oxidation resistant material filled in the sidewalls of the first oxidation resistant material and the second groove. Exposing the above silicon substrate
And a ninth step of making the silicon substrate, which is not covered with the first oxidation resistant material, porous by anodization, and the porous silicon region is made into a porous silicon oxide film by thermal oxidation. Tenth step, and removing a part of the second oxidation resistant material filled in the second groove to a region deeper than the depth of the region in which the semiconductor element is formed from the surface of the silicon substrate. An eleventh step of
It includes a twelfth step of thermally oxidizing the silicon substrate, and a thirteenth step of filling the second groove with an insulating material or a semiconductor material by a thin film deposition method to make the surface flat. .
［発明の実施例］ 以下、図面により本発明の実施例を説明する。第１図
(a)〜(j)は本発明の半導体装置の製造方法の実施例を示
す工程図の一部である。まず，第１図(a)に示す様に，
シリコン基板１の上に熱酸化膜すなわちSiO2膜２を形成
し，その上に第１の耐酸化性材料としてCVD Si3N4膜３
を，さらに第１の材料としてレジストパターン４を形成
する。SiO2膜２の膜厚は500Å，CVD Si3N4膜３の膜厚は
1000Å，レジスト４の膜厚は１〜1.5μｍとする。この
上にECR形プラズマ堆積法，イオンビームスパッタ法，
マグネトロンスパッタ法等の方向性をもった膜堆積法で
第２の材料すなわちSiO2膜５を堆積して第１図(b)の構
造を得る。これらの膜堆積法はいずれも基板温度を100
℃以下に保持して良質のSiO2膜が形成できるため，第１
図(b)に示すようにレジスト４の上に堆積してもレジス
トパターンの変形の問題は生じない。又，方向性を有し
ているためレジスト４の段差側壁には粗な膜質をもつ薄
膜５′が堆積し，この膜はライトエッチングによって容
易に除去される。この性質を利用してライトエッチング
を施すことによって第１図(c)の構造を得る。レジスト
４の側壁に溝ａが生じその底の幅は0.1〜0.2μｍ程度に
容易に制御して形成できる。SiO2膜５が分離されてでき
たSiO2膜６，７とレジスト４をマスクにしてRIEによっ
てSi3N4膜３，SiO2膜２，基板シリコン１をエッチング
して第１図(d)の構造を得る。シリコン基板１に形成し
た溝の深さを３μｍとする。エッチングガスとしては例
えばCBrF3を用いる。この時，溝ｂの上端の幅は，SiO2
膜６，７とレジスト膜４がエッチングされるため0.6μ
ｍ程度に広がる。溝ｂの下端の幅は0.1〜0.2μｍであ
る。SiO2膜６と７を除去して第１図(e)の構造を得る。
レジスト４をマスクとしてSi3N4膜３とSiO2膜２を除去
して第１図(f)の構造を得る。レジスト４を除去した
後，この上に第２の耐酸化性材料としてCVD Si3N4膜８
を0.3μｍの膜厚で堆積して第１図(g)の構造を得る。RI
Eでエッチングして第１図(h)の構造を得る。陽極化成法
によって第１図(i)に示す様にSi3N4膜３と８をマスクに
して多孔質シリコン膜９を形成する。多孔質シリコン膜
９の厚さはSi3N4膜８のシリコン基板１内に埋め込まれ
た底よりも浅くなる様に形成する。Embodiments of the Invention Embodiments of the present invention will be described below with reference to the drawings. Fig. 1
(a)-(j) is a part of process drawing which shows the Example of the manufacturing method of the semiconductor device of this invention. First, as shown in Fig. 1 (a),
A thermal oxide film, that is, a SiO 2 film 2 is formed on a silicon substrate 1, and a CVD Si 3 N 4 film 3 is formed thereon as a first oxidation resistant material.
Further, a resist pattern 4 is formed as a first material. The thickness of the SiO 2 film 2 is 500Å and the thickness of the CVD Si 3 N 4 film 3 is
The thickness of the resist 4 is 1000 Å and 1 to 1.5 μm. On top of this, ECR plasma deposition method, ion beam sputtering method,
The second material, that is, the SiO 2 film 5 is deposited by a film deposition method having directionality such as a magnetron sputtering method to obtain the structure of FIG. 1 (b). All of these film deposition methods have a substrate temperature of 100
Since a high-quality SiO 2 film can be formed by keeping the temperature below ℃,
As shown in FIG. 2B, the problem of resist pattern deformation does not occur even if it is deposited on the resist 4. Also, since it has directionality, a thin film 5'having a rough film quality is deposited on the side wall of the step of the resist 4, and this film is easily removed by light etching. By utilizing this property and performing light etching, the structure of FIG. 1 (c) is obtained. A groove a is formed on the side wall of the resist 4, and the width of the bottom thereof can be easily controlled to be about 0.1 to 0.2 μm. Figure 1 and the Si 3 N 4 film 3, SiO 2 film 2 by RIE with the SiO 2 film 6 and resist 4 SiO 2 film 5 was Deki is separated into the mask, the substrate silicon 1 is etched (d) Get the structure of. The depth of the groove formed in the silicon substrate 1 is 3 μm. As the etching gas, for example, CBrF 3 is used. At this time, the width of the upper end of the groove b is SiO 2
0.6μ because the films 6 and 7 and the resist film 4 are etched
Spread about m. The width of the lower end of the groove b is 0.1 to 0.2 μm. The SiO 2 films 6 and 7 are removed to obtain the structure shown in FIG.
Using the resist 4 as a mask, the Si 3 N 4 film 3 and the SiO 2 film 2 are removed to obtain the structure shown in FIG. 1 (f). After removing the resist 4, a CVD Si 3 N 4 film 8 is formed as a second oxidation resistant material on the resist 4.
Is deposited to a film thickness of 0.3 μm to obtain the structure shown in FIG. RI
Etch with E to obtain the structure of FIG. 1 (h). A porous silicon film 9 is formed by anodization using the Si 3 N 4 films 3 and 8 as a mask as shown in FIG. 1 (i). The thickness of the porous silicon film 9 is formed so as to be shallower than the bottom of the Si 3 N 4 film 8 embedded in the silicon substrate 1.
多孔質シリコン膜９の生成条件としては，陽極化成液に
濃度が20〜50％の弗酸を用い，電流密度30〜100mA／cm2
の電流を通常使用する。多孔質シリコン膜９の酸化工
程，その他の熱処理工程に伴って生ずるウェハの反りや
基板内の欠陥の発生を防止するため，プロセスによって
最適な多孔質シリコンの形成条件を選択する。これを熱
酸化しSi3N4膜３，SiO2膜２を除去して第１図(j)の構造
を得る。この時，既によく知られているように多孔質シ
リコンの特性により，低温かつ短時間で厚い多孔質シリ
コンの酸化膜10が得られる。絶縁層としてのSi3N4膜８
が存在するためLOCOS法にみられるバーズビークやバー
ズヘッドは生じない。勿論，酸化膜10とSi基板１の表面
が第１図(j)において平坦となる様に，多孔質シリコン
膜およびその酸化条件を設定することも容易である。
又，レジスト４のかわりにSiO2膜を用いることも勿論可
能である。The conditions for forming the porous silicon film 9 are hydrofluoric acid having a concentration of 20 to 50% in the anodizing solution, and a current density of 30 to 100 mA / cm 2
The current of is normally used. In order to prevent the warp of the wafer and the generation of defects in the substrate caused by the oxidation process of the porous silicon film 9 and other heat treatment processes, the optimum conditions for forming the porous silicon are selected according to the process. This is thermally oxidized to remove the Si 3 N 4 film 3 and the SiO 2 film 2 to obtain the structure of FIG. 1 (j). At this time, as is well known, a thick porous silicon oxide film 10 can be obtained at low temperature and in a short time due to the characteristics of porous silicon. Si 3 N 4 film as insulating layer 8
The existence of the bird's beak and bird's head seen in the LOCOS method does not occur. Of course, it is also easy to set the porous silicon film and its oxidizing conditions so that the surfaces of the oxide film 10 and the Si substrate 1 become flat in FIG. 1 (j).
It is also possible to use a SiO 2 film instead of the resist 4.
第２図(a)〜(e)は本発明の半導体装置の製造方法の他の
実施例を示す工程図である。第２図(a)は，第１図(d)に
示した試料をリフトオフしてレジスト４とその上のSiO2
膜６を除去し，SiO2膜７をマスクにして，Si3N4膜３と
その下のSiO2膜２を除去した構造である。第２図(b)はS
iO2膜７を除去した後，CVD Si3N4膜８を堆積した構造で
ある。第２図(c)〜(e)は前述の実施例の工程（第１図
(h)〜(j)）と同様にして行う。2 (a) to 2 (e) are process drawings showing another embodiment of the method for manufacturing a semiconductor device of the present invention. Fig. 2 (a) shows the resist 4 and SiO 2 on it after lift-off of the sample shown in Fig. 1 (d).
The film 6 is removed, and the SiO 2 film 7 is used as a mask to remove the Si 3 N 4 film 3 and the underlying SiO 2 film 2. Figure 2 (b) shows S
After removing the iO 2 film 7, a CVD Si 3 N 4 film 8 is deposited. 2 (c) to (e) are the steps of the above-described embodiment (FIG. 1).
(h) to (j)).
第３図（ａ）〜（ｃ）は、第１図（ｊ）又は第２図
（ｅ）では、Ｓｉ３Ｎ４膜８とシリコン基板１の界面特
性がシリコン領域Ａ又はＢに製作した素子に隣接して悪
影響を与えるので、さらに行うプロセスを示す。第１図
（ｊ）の試料のＳｉ３Ｎ４膜８の一部を上方から熱リン
酸でエッチングして除去し、残りのＳｉ３Ｎ４膜１３を
溝の底に残して第３図（ａ）の構造を得る。これを洗浄
して熱酸化し第３図（ｂ）の構造を得る。１４は熱酸化
膜である。これにＣＶＤ法によって例えばＣＶＤＳｉＯ
２膜又はＣＶＤポリＳｉ膜１２を堆積する。上方から基
板表面までエッチングし第３図（ｃ）の構造を得る。本
実施例においては、シリコン領域Ｅと多孔質シリコン酸
化膜10との境界に介在する絶縁層８の表面に近い部分が
CVD SiO2膜又はCVDポリSi膜12からなり，残りの部分が
耐酸化性材料すなわちCVD Si3N4膜13からなる。熱リン
酸に対するSi3N4膜のエッチング速度は遅いため，この
方法は工程時間の短縮につながる。素子は熱酸化膜14に
接するのみであるため良好な素子特性が得られる。上記
の熱酸化膜11，14の厚さは高々500Åで十分である。FIGS. 3 (a) to 3 (c) show the device in which the interface characteristic between the Si 3 N 4 film 8 and the silicon substrate 1 is produced in the silicon region A or B in FIG. 1 (j) or FIG. 2 (e). Since it adversely affects adjacent to, the process to be performed is shown. Part of the Si 3 N 4 film 8 of the sample in FIG. 1 (j) is removed by etching from above with hot phosphoric acid, and the remaining Si 3 N 4 film 13 is left at the bottom of the groove. Obtain the structure of a). This is washed and thermally oxidized to obtain the structure of FIG. 3 (b). Reference numeral 14 is a thermal oxide film. In addition to this, for example, CVD SiO
2 film or CVD poly-Si film 12 is deposited. Etching is performed from above to the substrate surface to obtain the structure shown in FIG. 3 (c). In this embodiment, a portion near the surface of the insulating layer 8 which is interposed at the boundary between the silicon region E and the porous silicon oxide film 10 is
It is composed of a CVD SiO 2 film or a CVD poly-Si film 12, and the remaining part is composed of an oxidation resistant material, that is, a CVD Si 3 N 4 film 13. Since the etching rate of the Si 3 N 4 film with respect to hot phosphoric acid is slow, this method shortens the process time. Since the element only contacts the thermal oxide film 14, good element characteristics can be obtained. The thickness of the above-mentioned thermal oxide films 11 and 14 is 500 Å at most.
上記具体例においては耐酸化性材料としてCVD Si3N4膜
を取り上げて説明したが，他の耐酸化性材料例えばAl2O
3等でも使用可能であることは言うまでもない。又，以
上述べた具体例の中の各寸法や諸条件は一例であって，
個々のデバイスに応じてそれぞれ種々の値をとれる様に
設定可能なことは勿論である。又，シリコン基板もｐ
型，ｎ型どちらでもよい。ただし，ｎ型の場合はよく知
られている通り，陽極化成時にたとえば光照射をして正
孔を発生させる必要がある。Although the CVD Si 3 N 4 film is taken as an example of the oxidation resistant material in the above-mentioned specific examples, other oxidation resistant materials such as Al 2 O 4 are used.
Needless to say, it can be used in 3rd magnitude. In addition, each dimension and various conditions in the specific examples described above are examples,
Of course, it is possible to set such that various values can be taken for each device. Also, the silicon substrate is p
Either type or n type may be used. However, in the case of the n-type, as is well known, it is necessary to generate light by irradiating light during anodization.
以上説明した様に、本発明によれば、バーズビーク、バ
ーズヘッドがなく、かつ、膜厚の厚い多孔質シリコン酸
化膜を有し、隣接するＳｉ面と平坦な構造の半導体装置
を実現でき、かつ、このような半導体装置を高密度に形
成できる。したがって、ＬＳＩの素子間分離構造として
好適である。また、本発明の半導体装置では、素子領域
に接する部分の耐酸化性材料を除去して素子領域は熱酸
化膜と接するようにしそれよりも深い部分は耐酸化性材
料としているので、良好な素子特性と生産性の向上の両
立を図ることができる。さらに、一般に耐酸化性材料は
不純物を通しにくいので、溝の底に耐酸化性材料を残す
ことにより、仮に溝の底が汚染された場合でも汚染物質
が表面に出てきにくく、製作される素子の特性が安定す
る。また、多孔質シリコン酸化膜は低温でかつ短時間で
厚い酸化膜が形成できるため、生産性が向上し、結晶欠
陥や不純物拡散層の不都合な拡散の発生を防止できるの
で、本発明による素子間分離方法はＣ−ＭＯＳ ＬＳＩ
の高密度化に大きな効果を有する。As described above, according to the present invention, it is possible to realize a semiconductor device having no bird's beak, no bird's head, having a thick porous silicon oxide film, and having a flat structure with an adjacent Si surface, and It is possible to form such a semiconductor device with high density. Therefore, it is suitable as an element isolation structure of an LSI. Further, in the semiconductor device of the present invention, the oxidation resistant material in the portion in contact with the element region is removed so that the element region is in contact with the thermal oxide film and the portion deeper than that is made of the oxidation resistant material. Both characteristics and productivity can be improved. In addition, since oxidation resistant materials generally do not allow impurities to easily pass through, leaving the oxidation resistant material at the bottom of the groove prevents contaminants from coming out on the surface even if the bottom of the groove is contaminated. The characteristics of are stable. In addition, since a porous silicon oxide film can form a thick oxide film at a low temperature and in a short time, productivity is improved and crystal defects and inconvenient diffusion of an impurity diffusion layer can be prevented. Separation method is C-MOS LSI
It has a great effect on increasing the density.
第１図（ａ）〜（ｊ）は本発明の半導体装置の製造方法
の一実施例の一部を示す工程図，第２図（ａ）〜（ｅ）
は本発明の半導体装置の製造方法の別の一実施例の一部
を示す工程図，第３図（ａ）〜（ｃ）は第１図（ｊ）ま
たは第２図（ｅ）は本発明の半導体装置の製造方法の別
の一実施例を示す工程図，第３図(a)〜(c)および第４図
(a)〜(c)はそれぞれ第１図(j)または第２図(e)の工程の
後に引き続いて行われる製造方法の一実施例を示す工程
図である。 １…シリコン基板 ２…SiO2膜 ３，８…CVD Si3N4膜 ４…レジスト（第１の材料） ５，６，７…SiO2膜（第２の材料） ９…多孔質シリコン膜 10…多孔質シリコンの熱酸化膜 14…熱酸化膜 12…CVD SiO2膜又はCVDポリSi膜 13…CVD Si3N4膜 Ａ，Ｂ，Ｃ，Ｅ…シリコン領域 ａ，ｂ…溝1 (a) to 1 (j) are process diagrams showing a part of an embodiment of a method for manufacturing a semiconductor device of the present invention, and FIGS. 2 (a) to 2 (e).
Is a process diagram showing a part of another embodiment of the method for manufacturing a semiconductor device of the present invention, and FIGS. 3 (a) to 3 (c) are FIG. 1 (j) or 2 (e). Process charts showing another embodiment of the method for manufacturing a semiconductor device, FIG. 3 (a) to (c) and FIG.
(a)-(c) is process drawing which shows one Example of the manufacturing method performed after the process of FIG. 1 (j) or FIG. 2 (e), respectively. 1 ... Silicon substrate 2 ... SiO 2 film 3, 8 ... CVD Si 3 N 4 film 4 ... Resist (first material) 5, 6, 7 ... SiO 2 film (second material) 9 ... Porous silicon film 10 … Porous silicon thermal oxide film 14… Thermal oxide film 12… CVD SiO 2 film or CVD poly Si film 13… CVD Si 3 N 4 film A, B, C, E… Silicon regions a, b… Grooves
───────────────────────────────────────────────────── フロントページの続き (72)発明者 松尾 誠太郎 神奈川県厚木市小野1839番地 日本電信電 話公社厚木電気通信研究所内 (56)参考文献 特開 昭57−111042（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seitaro Matsuo 1839 Ono, Atsugi City, Kanagawa Pref. Atsugi Telecommunications Research Laboratories, Nippon Telegraph and Telephone Corporation (56) Reference JP-A-57-111042 (JP, A)
Claims (2)
まれている素子領域であるシリコン領域の周辺に、シリ
コン酸化膜が上記シリコン基板の表面から上記シリコン
基板の内部に向かって存在し、 上記シリコン領域と上記シリコン酸化膜の領域との境界
に絶縁層が介在する構造を有し、上記素子領域の上記シ
リコン基板表面からの深さよりも深い領域まで上記絶縁
層が存在しかつ、上記絶縁層の表面に近い部分の少なく
とも前記素子領域に接する部分が酸化シリコンからな
り、残りの深い部分が耐酸化性材料からなることを特徴
とする半導体装置。1. A silicon oxide film exists from the surface of the silicon substrate toward the inside of the silicon substrate in the periphery of a silicon region which is a device region in which a semiconductor device is formed on the surface of the silicon substrate. A structure in which an insulating layer is interposed at the boundary between the silicon region and the region of the silicon oxide film, the insulating layer exists up to a region deeper than the depth of the element region from the surface of the silicon substrate, and the insulating layer A semiconductor device, characterized in that at least a portion of the portion near the surface of the element in contact with the element region is made of silicon oxide and the remaining deep portion is made of an oxidation resistant material.
ン基板上に、第１の材料を堆積した後パターン形成して
半導体素子が作り込まれる領域以外の領域にある上記第
１の材料を除去する第１の工程と、この上に方向性を有
する膜堆積法によって第２の材料を全面に堆積する第２
の工程と、エッチングによって上記第１の材料のパター
ンの縁に付着した上記第２の材料を除去することによ
り、上記第１の材料と上記第２の材料によって第１の溝
を形成する第３の工程と、上記第１の溝の底に露出した
上記第１の耐酸化性材料を表面に有するシリコン基板を
上記半導体素子が作り込まれる領域の上記シリコン基板
表面からの深さよりも深い領域までエッチングして上記
シリコン基板に第２の溝を形成する第４の工程と、上記
第２の材料を除去する第５の工程と、上記第１の材料を
マスクにしてこれに覆われていない領域の上記第１の耐
酸化性材料を除去する第６の工程と、上記第１の材料を
除去した後上記シリコン基板に第２の耐酸化性材料を堆
積することにより、上記シリコン基板の上記第２の溝の
中に上記第２の耐酸化性材料を充填するとともに、パタ
ーン形成された上記第１の耐酸化性材料の上も上記第２
の耐酸化性材料で被覆する第７の工程と、方向性エッチ
ングを行うことにより、パターン形成された上記第１の
耐酸化性材料の側壁および上記第２の溝の中に充填した
上記第２の耐酸化性材料を残し、それ以外の領域に堆積
された上記第２の耐酸化性材料をエッチングして上記シ
リコン基板を露出する第８の工程と、上記第１の耐酸化
性材料で被覆していない上記シリコン基板を陽極化成に
よって多孔質化する第９の工程と、熱酸化によって上記
多孔質シリコン領域を多孔質シリコン酸化膜にする第１
０の工程と、上記第２の溝の中に充填した上記第２の耐
酸化性材料の少なくとも上記半導体素子が作り込まれる
領域に接する部分を除去し、残りの部分を上記第２の溝
の底に残す第１１の工程と、上記シリコン基板を熱酸化
する第１２の工程と、上記第２の溝の中に薄膜堆積法に
よって絶縁物または半導体材料を充填し、表面を平坦に
する第１３の工程を含むことを特徴とする半導体装置の
製造方法。2. The first material in a region other than a region in which a semiconductor element is formed by depositing the first material and then patterning it on a silicon substrate having a first oxidation resistant material on its surface. And a second step of depositing a second material on the entire surface by a directional film deposition method.
And the step of removing the second material adhering to the edge of the pattern of the first material by etching to form a first groove with the first material and the second material. And a silicon substrate having the surface of the first oxidation resistant material exposed at the bottom of the first groove, up to a region deeper than the depth of the region in which the semiconductor element is formed from the surface of the silicon substrate. A fourth step of forming a second groove in the silicon substrate by etching, a fifth step of removing the second material, and a region not covered with the first material as a mask A sixth step of removing the first oxidation resistant material, and depositing a second oxidation resistant material on the silicon substrate after removing the first material, The second acid-proof in the groove of 2 To fill the sexual material, patterns the top of the formed said first oxidation resistant material second
And a second step of filling the sidewalls of the patterned first oxidation resistant material and the second trenches by performing a directional etching. Of the second oxidation resistant material remaining in the region other than the above, and etching the second oxidation resistant material to expose the silicon substrate, and coating with the first oxidation resistant material. A ninth step of making the above-mentioned silicon substrate porous by anodization, and a first step of making the above-mentioned porous silicon region into a porous silicon oxide film by thermal oxidation
0 step and removing at least a portion of the second oxidation resistant material filled in the second groove, which is in contact with the region where the semiconductor element is formed, and the remaining portion of the second groove. Eleventh step of leaving on the bottom, twelfth step of thermally oxidizing the silicon substrate, and thirteenth step of filling the second groove with an insulator or a semiconductor material by a thin film deposition method to flatten the surface. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58149036A JPH067573B2 (en) | 1983-08-15 | 1983-08-15 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58149036A JPH067573B2 (en) | 1983-08-15 | 1983-08-15 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6041242A JPS6041242A (en) | 1985-03-04 |
| JPH067573B2 true JPH067573B2 (en) | 1994-01-26 |
Family
ID=15466253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58149036A Expired - Lifetime JPH067573B2 (en) | 1983-08-15 | 1983-08-15 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067573B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5028559A (en) * | 1989-03-23 | 1991-07-02 | Motorola Inc. | Fabrication of devices having laterally isolated semiconductor regions |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57111042A (en) * | 1980-12-27 | 1982-07-10 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1983
- 1983-08-15 JP JP58149036A patent/JPH067573B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6041242A (en) | 1985-03-04 |
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