JPS6159747A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6159747A
JPS6159747A JP18095384A JP18095384A JPS6159747A JP S6159747 A JPS6159747 A JP S6159747A JP 18095384 A JP18095384 A JP 18095384A JP 18095384 A JP18095384 A JP 18095384A JP S6159747 A JPS6159747 A JP S6159747A
Authority
JP
Japan
Prior art keywords
oxide film
film
field oxide
bird
silica
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18095384A
Other languages
Japanese (ja)
Inventor
Takeo Yoshikawa
吉川 武夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18095384A priority Critical patent/JPS6159747A/en
Publication of JPS6159747A publication Critical patent/JPS6159747A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To flatten a field oxide film surface by coating the entire surface of a semiconductor substrate on which a field oxide film is formed by a selective oxide film forming method with a silica film and executing ion etching with inactive gas ion. CONSTITUTION:A semiconductor element and a field oxide film 6 which protects a semiconductor element are formed on a semiconductor substrate 1 by the selective oxide film forming method. Next, entire surface of substrate is coated with a silica film 9. Thereby, the film 9 is formed thin at the recessed part corresponding to the bird's head 8. The ion etching (sputter etching) 10 is carried out using inactive gas such as Ar, etc. and the remaining film 9 is removed. Thereby, since the etching rate is almost equal in the case of film 9 and oxide film 6, the extruded part of bird's head 8 is etched and the element surface is flattened. Accordingly, disconnection at the stepped part of metal wirings is not easily generated.

Description

【発明の詳細な説明】 (M梁上の利用分野) 本発明は半導体装置の製造方法に関し、特に選択酸化膜
形成法により形成したフィールド酸化膜、の平坦化工程
を含む半導体装置の製造方法に関する。
Detailed Description of the Invention (Field of Application on M Beams) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of planarizing a field oxide film formed by a selective oxide film forming method. .

(従来技術) 従来、選択酸化膜形成法を使った素子分離技術はLSI
の高微細化、高集積化への決定版として数多く適用され
ている。第4図は従来の選択酸化膜形成法を適用したバ
イポーラトランジスタの一例の断面図である。第4図に
示されている様に、Pfi基板1上にコレクタN −N
epi領域2、ベースP領域3、エミッタN 領域4か
ら々る素子領域を形成し、最後に金属配線5を形成する
。このように形成された半導体装置は第4図から明らか
なように問題としてフィールド酸化膜6の端部にできる
ハース、ピーク(bird’s beak) 7現象と
フィールド酸化膜の表面にできるバーズ・ヘッド(bi
rd’s head ) B 現象カアル。
(Prior art) Conventionally, element isolation technology using selective oxide film formation was applied to LSI
It has been widely applied as the definitive solution to higher miniaturization and higher integration. FIG. 4 is a cross-sectional view of an example of a bipolar transistor to which the conventional selective oxide film formation method is applied. As shown in FIG. 4, a collector N-N is placed on the Pfi substrate 1.
An element region consisting of an epi region 2, a base P region 3, and an emitter N region 4 is formed, and finally a metal wiring 5 is formed. As is clear from FIG. 4, the semiconductor device formed in this manner suffers from problems such as the bird's beak phenomenon that occurs at the end of the field oxide film 6 and the bird's head phenomenon that occurs on the surface of the field oxide film. (bi
rd's head) B phenomenon Kaal.

バーズ・ピークは素子微細化の妨げとなり、一方バーズ
・ヘッドについては、それがフィールド酸化膜に凹凸状
の起伏を生じデバイス表面の平坦性が失われる。従って
この様なバーズヘットカ存在するフィールド酸化膜上に
金属配線を行うと断線を起しゃすく々る。特に多層配線
では、その頻度が、高く麦る傾向にあった。その結果チ
ップ歩留りは下がり、コストは上昇するという欠点があ
った。
Bird's peaks impede device miniaturization, while bird's heads cause unevenness in the field oxide film, resulting in loss of device surface flatness. Therefore, if metal wiring is formed on a field oxide film in which such bird's heads exist, disconnection will occur. Particularly in multilayer wiring, the frequency of such failures tended to be high. As a result, there were disadvantages in that the chip yield decreased and the cost increased.

(発明の目的) 本発明の目的は、上記欠点を除去し、す々わちフィール
ド酸化腰上の凹、凸を力くシ、デバイス表面の平坦性を
同上させることにより金属配線の断線を防ぎ、信頼性を
向上させコストを低下させることが可能な半導体装置の
製造方法を提供することにある。
(Objective of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks, eliminate the depressions and protrusions on the field oxidation layer, and prevent disconnection of metal wiring by improving the flatness of the device surface. Another object of the present invention is to provide a method for manufacturing a semiconductor device that can improve reliability and reduce costs.

(発明の構成) 本発明の半導体装置の製造方法は、半導体基板の一主面
上に選択激化膜形成方法によりフィールド酸化膜を形成
する工程と1回路素子形成領域に回路素子を形成する工
程と、フィールド酸化膜の形成された基板の全表面にシ
リカフィルムを塗布する工程と、不活性ガスイオンによ
り前記シリカフィルム上面よりイオンエツチングを行い
フィールド酸化膜の表面を平坦化する工程上を含んで構
成される。
(Structure of the Invention) A method for manufacturing a semiconductor device according to the present invention includes a step of forming a field oxide film on one main surface of a semiconductor substrate by a selective intensification film forming method, and a step of forming a circuit element in one circuit element formation region. , a step of applying a silica film to the entire surface of the substrate on which a field oxide film is formed, and a step of flattening the surface of the field oxide film by performing ion etching from the upper surface of the silica film using inert gas ions. be done.

(作用) 本発明によれば、選択酸化により形成されたフィールド
酸化膜の表面はパース・ピーク、バーズ・ヘッドのため
凹凸が大きいがこの表面に先ずシリカフィルムが塗布形
成される。従ってシリカフィルムは凸部で導く、凹部で
厚く形成されるのでシリカフィルム表面は凹凸部で#1
ぼ平坦になる。
(Function) According to the present invention, a silica film is first applied to the surface of the field oxide film formed by selective oxidation, which has large irregularities due to perspective peaks and bird's heads. Therefore, the silica film is guided at the convex portions and thickened at the concave portions, so the surface of the silica film is #1 at the concave and convex portions.
It becomes flat.

次にシリカフィルム上面よりAr等の不活性ガスをイオ
ン化し、イオンエツチングする。このエツチングは反応
性イオンエツチングと異なりシリカフィルムと酸化膜の
エツチングレートはほぼ等しいので、デバイス表面は均
一にエツチングされ平坦な酸化膜表面が形成できる。
Next, an inert gas such as Ar is ionized from the upper surface of the silica film to perform ion etching. Unlike reactive ion etching, this etching has approximately the same etching rate for the silica film and the oxide film, so the device surface can be uniformly etched and a flat oxide film surface can be formed.

従ってこの平坦化された表面に配線を形成すれば断線事
故のない信頼間の大きいコストの安い半導体装置が得ら
れる。
Therefore, if wiring is formed on this flattened surface, a highly reliable and low-cost semiconductor device without disconnection accidents can be obtained.

(実施例) 以下、本発明の実施例について図面を参照して説明する
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図(旬〜(6)は本発明の一実施例を説明するため
に工程順に示した断面図である。
FIG. 1 (6) is a sectional view showing the steps in order to explain an embodiment of the present invention.

先ず、第1図(a)Jc示すように、P型半導体基板1
の一生面にコレクタN”・Nepi 領域2、ベース、
P領域3、エミッ、りN+領域4、そして各素子を分離
し、又素子表面を保護するフィールド酸化膜6を形成す
る。第1 ff1(a)で7#iバーズ・ピーク、8は
バーズ・ヘッドである。これ゛までの工程は従来の選択
酸イヒ膜の形成方法にエリ形成することが1できる。
First, as shown in FIG. 1(a) Jc, a P-type semiconductor substrate 1 is
Collector N” Nepi area 2, base,
A P region 3, an emitter region, an N+ region 4, and a field oxide film 6 for isolating each element and protecting the element surface are formed. In the 1st ff1(a), 7#i is Bird's Peak and 8 is Bird's Head. The steps up to this point can be applied to the conventional method of forming a selective acid film.

次に、第1図(b)に示すように、各領域2,3゜4表
面及びフィールド酸化膜6表面にシリカフィルム9を全
面箆布形成する。同図に示されているように、バーズヘ
ッド8に対応する凸部では薄く。
Next, as shown in FIG. 1(b), a silica film 9 is formed on the entire surface of each region 2, 3.4 and the field oxide film 6. As shown in the figure, the convex portion corresponding to the bird's head 8 is thin.

凹部では厚く塗布され、シリカフィルム90表面は凹凸
部でほぼ平坦になる。
The silica film 90 is coated thickly in the concave portions, and the surface of the silica film 90 becomes substantially flat in the concave and convex portions.

次に、第1図(C)に示すように、シリカフィルム9上
面より、Ar等の不活比ガスをイオン化し、イオンエツ
チング(スパッタエツチングともいう)を行う。
Next, as shown in FIG. 1C, an inert gas such as Ar is ionized from the upper surface of the silica film 9, and ion etching (also referred to as sputter etching) is performed.

反応性イオンエツチングと異なり、シリカフィルムと酸
化膜のエツチングレートはほぼ等しく、従り、て均一に
エツチングされる。
Unlike reactive ion etching, the etching rates of the silica film and the oxide film are approximately equal, so they are etched uniformly.

次に、第1図(d)に示すように、適肖な時間イオンエ
ツチングし、シリカフィルムと共にバーズ・ヘッドの凸
部を除去する。しかる後残ったシリカ7、イkA’&除
去すると、パース・ヘッド8の凸部が緩和され、はば平
坦化された表面が得られる。
Next, as shown in FIG. 1(d), ion etching is performed for an appropriate time to remove the convex portion of the bird's head together with the silica film. Thereafter, the remaining silica 7 is removed, the protrusions of the parsing head 8 are relaxed, and a flattened surface is obtained.

次に、第1図(e)に示すように、金属配線5を施こす
と図示のような平坦な表面に金属配線の形成された本実
施例で形成された半導体装置が得られる。
Next, as shown in FIG. 1(e), a metal wiring 5 is formed to obtain the semiconductor device formed in this embodiment in which the metal wiring is formed on a flat surface as shown in the figure.

本実施例にエリ形成された半導体装iはバーズ・ヘッド
8面の金属配線の段差が大きく減少し、本実施例におい
ては、第1図(a)〜(e)に示した実施例においてフ
ィールド酸化膜を平坦化し、シリカフィルムを除去した
後再び酸化を行ないフィールド酸化膜を厚くし、多結晶
シリコンコンタクト11又はTi  W材からなるコン
タクト12を設けて金属配線の信頼性を向上させた列で
ある。フィールド酸化膜を厚くすることによりパースヘ
ッドの緩和と平坦化は損なわれることなく、むしろ信頼
性と共に向上する。
In the semiconductor device i formed with an edge in this example, the level difference in the metal wiring on the 8th surface of the bird's head is greatly reduced. After planarizing the oxide film and removing the silica film, oxidation is performed again to thicken the field oxide film, and a polycrystalline silicon contact 11 or a contact 12 made of TiW material is provided to improve the reliability of the metal wiring. be. By increasing the thickness of the field oxide, relaxation and planarization of the perspective head are not compromised, but rather are improved along with reliability.

(発明の効JJ7:) 以上説明したとおり、本発明によれば、選択酸化膜形成
法により形成されたバーズヘッドをイオンエツチングす
ることにより緩和もしくは消減し、配線段切れのない、
歩留りの高い半導体装置を製造することができる。
(Effects of the Invention JJ7:) As explained above, according to the present invention, the bird's head formed by the selective oxide film formation method is relaxed or eliminated by ion etching, and there is no wiring step breakage.
Semiconductor devices can be manufactured with high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1@(a)〜(e)は本発明の一実施例を説明するた
めに工程順に示した断面図、第2図は本発明の他の実施
例を説明するための断面図、第3図は従来の選択酸化膜
形成法を用いて製造したバイポーラトランジスタの断面
図で6る。 1・・・・・・P型半導体基板、2・・・・・・コレク
タ ・Nepi領域、3・・・・・・ベースP領域、4
・・・・・・エミッタN+領域、5・・・・・・金属配
線、6・・・・・・フィールド酸化膜、7・・・・・・
バーズ・ピーク、8・・・・・・バーズ・ヘッド、9・
・・・・・シリカフィルム、10・・・・・−不活性ガ
スイオン、11・・・・・・多結晶シリコンコンタクト
、12・・・・・・Ti  Wコンタクト。 第1圀
1@(a) to (e) are sectional views shown in the order of steps to explain one embodiment of the present invention, FIG. 2 is a sectional view to explain another embodiment of the present invention, and 3. Figure 6 is a cross-sectional view of a bipolar transistor manufactured using a conventional selective oxide film formation method. 1... P-type semiconductor substrate, 2... Collector/Nepi region, 3... Base P region, 4
...Emitter N+ region, 5...Metal wiring, 6...Field oxide film, 7...
Bird's Peak, 8...Bird's Head, 9.
..... Silica film, 10 ....-Inert gas ion, 11 ..... Polycrystalline silicon contact, 12 ..... Ti W contact. 1st area

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の一主面上に選択酸化膜形成法によりフィー
ルド酸化膜を形成する工程と、回路素子形成領域に回路
素子を形成する工程と、フィールド酸化膜の形成された
基板全表面にシリカフィルムを塗布形成する工程と、不
活性ガスイオンにより前記シリカフィルム上面よりイオ
ンエッチングを行いフィールド酸化膜の表面を平坦化す
る工程とを含むことを特徴とする半導体装置の製造方法
A step of forming a field oxide film on one principal surface of a semiconductor substrate by a selective oxide film formation method, a step of forming a circuit element in a circuit element formation area, and a step of forming a silica film on the entire surface of the substrate on which the field oxide film has been formed. 1. A method of manufacturing a semiconductor device, comprising the steps of coating and forming the field oxide film, and planarizing the surface of the field oxide film by performing ion etching from the upper surface of the silica film using inert gas ions.
JP18095384A 1984-08-30 1984-08-30 Manufacture of semiconductor device Pending JPS6159747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18095384A JPS6159747A (en) 1984-08-30 1984-08-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18095384A JPS6159747A (en) 1984-08-30 1984-08-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6159747A true JPS6159747A (en) 1986-03-27

Family

ID=16092159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18095384A Pending JPS6159747A (en) 1984-08-30 1984-08-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6159747A (en)

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