JPH02281757A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02281757A JPH02281757A JP10433089A JP10433089A JPH02281757A JP H02281757 A JPH02281757 A JP H02281757A JP 10433089 A JP10433089 A JP 10433089A JP 10433089 A JP10433089 A JP 10433089A JP H02281757 A JPH02281757 A JP H02281757A
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- Prior art keywords
- opening
- insulating film
- section
- semiconductor region
- film
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000002184 metal Substances 0.000 claims description 32
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 2
- 230000003190 augmentative effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 28
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に半導体領域に絶縁膜
の開口部を通して被着される金属電極の被着面積の制御
性及び段切れ防止を改善するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to controllability of the deposition area of a metal electrode deposited on a semiconductor region through an opening in an insulating film and prevention of disconnection. It is something to improve.
本発明は、半導体領域に絶縁膜の開口部を通して金属電
極が被着されてなる半導体装置において、その絶縁膜の
開口部の断面形状を上部でテーパー状とし、下部で円弧
状とすることにより、金属電極の半導体領域に対する被
着面積の制御性を維持しながら、金属電極の段切れを防
止できるようにしたものである。The present invention provides a semiconductor device in which a metal electrode is adhered to a semiconductor region through an opening in an insulating film, in which the cross-sectional shape of the opening in the insulating film is tapered at the top and arcuate at the bottom. This makes it possible to prevent breakage of the metal electrode while maintaining controllability of the adhesion area of the metal electrode to the semiconductor region.
高周波用の半導体ダイオード、例えばミキサー用GaA
sショットキーダイオードにおいては、周波数特性を向
上するために接合面積の縮小9例えば直径10μm以下
の縮小が必要である。この場合、デバイスの均一性を維
持するだめの寸法制御は、より厳密さが要求される。Semiconductor diodes for high frequencies, e.g. GaA for mixers
In order to improve the frequency characteristics of the S Schottky diode, it is necessary to reduce the junction area 9, for example, to a diameter of 10 μm or less. In this case, stricter dimensional control is required to maintain device uniformity.
通常、これらダイオードのショットキー接触の形成は、
第3図に示すように半導体領域(1)の主面上に1μm
以上の厚い絶縁膜例えば5i02膜(2)を堆積し、こ
のSi0g膜(2)をフォトレジスト層によるマスクを
介して選択エツチングして開口部(3)を形成し、この
開口部(3)を通してショットキー電極即ちショットキ
ーメタル(4)を半導体領域(1)に被着して行われる
。ショットキーメタル(4)上には、図示せざるもパッ
ドメタルが被着される。そして、この場合、通常のHF
系エツチング液によるウェットエツチングで開口部(3
)を形成すると開口部(3)の上端縁aが直角に近くな
り、この上端縁aでショットキーメタル(4)(バンド
メタルを含む)の段切れが生じ信頼性の劣化が問題とな
る。従来、このメタル段切れを避けるために、第4図に
示すように半導体領域(])に堆積したSiO□膜(2
)の開口部(3)の断面形状をテーパー状(6)とし、
開口部(3)の上端縁aの角度を大きくしてショットキ
ーメタル(4)を含むメタル段切れを防止している。Typically, the formation of Schottky contacts for these diodes is
1 μm on the main surface of the semiconductor region (1) as shown in Figure 3.
A thick insulating film such as 5i02 film (2) is deposited, and this Si0g film (2) is selectively etched through a photoresist layer mask to form an opening (3). This is done by depositing a Schottky electrode or Schottky metal (4) on the semiconductor region (1). A pad metal (not shown) is deposited on the Schottky metal (4). And in this case, normal HF
The opening (3
), the upper edge a of the opening (3) becomes close to a right angle, and the Schottky metal (4) (including the band metal) is broken at this upper edge a, resulting in a problem of deterioration of reliability. Conventionally, in order to avoid this metal step break, a SiO□ film (2
) has a tapered cross-sectional shape (6) in the opening (3);
The angle of the upper edge a of the opening (3) is increased to prevent metal steps including the Schottky metal (4) from breaking.
しかし乍ら、第4図の構成においてはショットキーメタ
ル(4)と半導体領域(1)との接触部端縁すでの5i
Oz膜(2)の角度θが小さくなる。この端縁すの位置
寸法はSin、膜(2)のエツチングシートβに対して
β/ tanθで依存するから、例えばθ=20°の場
合2.75Xβで変化することになり、ショットキー接
合の幅W、従ってショットキー接合面積の制御性を悪化
させるものであった。However, in the configuration shown in FIG. 4, the edge of the contact area between the Schottky metal (4) and the semiconductor region (1) is already
The angle θ of the Oz film (2) becomes smaller. Since the positional dimension of this edge depends on Sin and the etched sheet β of the film (2) by β/tanθ, for example, when θ=20°, it changes by 2.75×β, which is the Schottky junction. This worsened the controllability of the width W and therefore the Schottky junction area.
また、ショットキー接合面積の縮小に伴い、S i 0
2 膜(2)のテーパ一部分の容量による寄生成分が相
対的に増すために周波数特性が低下するものであった。In addition, with the reduction of the Schottky junction area, S i 0
2. Frequency characteristics deteriorated due to a relative increase in parasitic components due to the capacitance of the tapered portion of the film (2).
なお、上述ではショットキー電極の場合であるが、その
他生導体領域とオーミック接触する電極配線等について
も同じように段切れ、被着面積の制御性等の問題がある
。Although the above description deals with the case of Schottky electrodes, other electrode wirings that make ohmic contact with live conductor regions also have similar problems such as breakage and controllability of the adhesion area.
本発明は、上述の点に鑑み、金属電極の半導体領域に対
する被着面積の制御性を維持しながら、金属電極の段切
れを防止できるようにした半導体装置を提供するもので
ある。In view of the above-mentioned points, the present invention provides a semiconductor device that can prevent the metal electrode from breaking while maintaining controllability of the area to which the metal electrode is adhered to the semiconductor region.
本発明は、半導体領域(21)に絶縁膜(12)の開口
部(19)を通して金属電極(4)が被着されてなる半
導体装置において、開口部(19)の断面形状を上部が
テーパー状(17)になり、下部が円弧状(18)にな
るように形成する。The present invention provides a semiconductor device in which a metal electrode (4) is adhered to a semiconductor region (21) through an opening (19) of an insulating film (12), in which the cross-sectional shape of the opening (19) is tapered at the top. (17), and the lower part is formed into an arc shape (18).
半導体領域(21)上に形成した絶縁膜(12)の開口
部(19)の断面形状が半導体領域(21)に接する下
部で円弧状(17)となっているので、金属電極(4)
と半導体領域(21)との接触部端縁すでの接触角即ち
絶縁膜(12)の角度θが大きくなり、金属電極(4)
の半導体領域との被着面積の制御性が上る。また、開口
部(19)の上部がテーパー状(17)になっているの
で、y!!、li膜(12)の開口部上端縁aの角度は
大きくなり、金属電極(4)の段切れが防止される。Since the cross-sectional shape of the opening (19) of the insulating film (12) formed on the semiconductor region (21) is arcuate (17) at the lower part in contact with the semiconductor region (21), the metal electrode (4)
The contact angle at the edge of the contact portion between the metal electrode (4) and the semiconductor region (21), that is, the angle θ of the insulating film (12) increases, and the metal electrode (4)
The controllability of the adhesion area with the semiconductor region is improved. Also, since the upper part of the opening (19) is tapered (17), y! ! , the angle of the upper edge a of the opening of the Li film (12) becomes large, and step breakage of the metal electrode (4) is prevented.
以下、本発明の詳細な説明する。 The present invention will be explained in detail below.
第2図Aに示すように、基体(11)上に形成した絶縁
膜(12)を3層構造とし、各層(13) (14)
(15)のエツチングレートβ〔β1.β2.β3ゴの
関係がβ3〉β1)β2.各層(13) (14) (
15)の膜厚d(L 、dz、d3]の関係がd、>d
z)dzとなるように選んだ構成を考える。具体的に、
基体(11)としてGaAs半導体を用いた場合の各絶
縁膜(13) (14) (15)の−例を表Iに示す
。As shown in FIG. 2A, the insulating film (12) formed on the base (11) has a three-layer structure, and each layer (13) (14)
(15) Etching rate β [β1. β2. The relationship between β3 and β3 is β3>β1)β2. Each layer (13) (14) (
15) The relationship between the film thickness d (L, dz, d3) is d, > d
z) Consider a configuration chosen so that dz. specifically,
Table I shows examples of the insulating films (13), (14), and (15) when a GaAs semiconductor is used as the base (11).
この3層構造は絶縁膜(12)をフォトレジスト層(1
6)をマスクとして選択エツチングすると、第2図B以
下のような経過でエツチングされる。This three-layer structure consists of an insulating film (12) and a photoresist layer (1).
When selectively etching is performed using 6) as a mask, the etching progresses as shown in FIG. 2B and below.
即ち、第3層の膜(I5)及び第2層の膜(14)をエ
ツチングして窓あけしだ後(第2図B〜第2図E参照)
、更に第1層の膜(13)をHF系エツチング液を用い
てエツチングすると、エツチング初期は第2図Fに示す
ように第1層の膜(13)の断面形状は第2層の膜(1
4)をマスクとした等方性エツチングとなり、エツチン
グ開始時の第2層の膜(14)の開口端縁の位置B0を
中心とした円弧状となる。That is, after etching the third layer film (I5) and the second layer film (14) and opening a window (see FIGS. 2B to 2E).
When the first layer film (13) is further etched using an HF-based etching solution, the cross-sectional shape of the first layer film (13) at the initial stage of etching is similar to that of the second layer film (13), as shown in FIG. 2F. 1
4) is used as a mask, the etching is isotropic, and the etching becomes an arc shape centered on the position B0 of the opening edge of the second layer film (14) at the start of etching.
しかし、エツチングが進むにつれて、第1層のIII(
13)と第3層の膜(14)のエツチングレートの関係
がβ、〉β、なるがゆえに、第1層の膜(13)と第2
層の膜(14)の接触点A(以下A点という)とそれよ
り奥の第3層の膜(15)と第2層の膜(14)の接触
点C(以下C点という)との間隔I!、1がしだいに大
きくなる。一方、81点と0点の距離12はエツチング
レートβ2とβ、によって決まる一定値以下であるため
、ある時点でB1点はA点より内側に入るため、それ以
降第1層の膜(13)のマスクとして作用している第2
Nの膜(14)によるA点が第3層の膜(15)のエツ
チングレートβ3で後退し、第1層の膜(13)の上部
断面はテーパー状(17)を呈するようになる(第2図
H参照)。しかし、その際エツチング前半で等方性エツ
チングされた部分は88点を中心とした円弧状(18)
のエツチングが継続される。従って、絶縁膜(12)の
基体(11)に達する開口部(19)が形成された後の
開口部断面形状は、第2図Iに示すように上部がテーパ
ー状(17)をなし、下部が円弧状(18)となした断
面形状となる。これにより、開口寸法Wは非テーパーエ
ツチングと同様に第1層の膜(13)のエツチングレー
トβ1程度の制御性か得られる。However, as the etching progresses, the first layer III (
13) and the third layer film (14) are β, >β. Therefore, the relationship between the etching rate of the first layer film (13) and the second
The contact point A (hereinafter referred to as point A) of the layer film (14) and the contact point C (hereinafter referred to as point C) between the third layer film (15) and the second layer film (14) located further back than that. Interval I! , 1 gradually becomes larger. On the other hand, since the distance 12 between point 81 and point 0 is less than a certain value determined by etching rates β2 and β, point B1 will be inside point A at a certain point, and from then on, the first layer film (13) The second mask acts as a mask for
The point A formed by the N film (14) retreats at the etching rate β3 of the third layer film (15), and the upper cross section of the first layer film (13) takes on a tapered shape (17). (See Figure 2H). However, in this case, the isotropically etched part in the first half of the etching process has a circular arc shape (18 points) centered at 88 points.
Etching continues. Therefore, after the opening (19) reaching the base (11) of the insulating film (12) is formed, the cross-sectional shape of the opening is tapered (17) at the upper part and tapered at the lower part, as shown in FIG. 2I. has an arcuate cross-sectional shape (18). As a result, the opening size W can be controlled to the extent of the etching rate β1 of the first layer film (13), similar to non-taper etching.
なお、第1層の膜(13)のエツチング開始後、テーパ
ー状エツチングに移る時間txはtx=β3d2/β!
(β、−β1)で計算される。表1に揚げた具体例では
Lx =4分となる。Note that the time tx from which the first layer film (13) starts etching to tapered etching is tx=β3d2/β!
It is calculated as (β, −β1). In the specific example listed in Table 1, Lx = 4 minutes.
他の方法としては、前記第3層の膜(15)を用いずに
、絶縁膜(12)を2層構造とし、その際第2層の膜(
14)とフォトレジストj!! (16)との密着性を
ある程度低下させ、エツチングとともにフォトレジスト
層(16)と第2層の膜(14)との間にエツチング液
がしだいに浸入していくことを利用する方法である。こ
の場合には、前記第3層の膜(15)のエツチングレー
トβ3をエツチング液の浸入速度に置き換えれば同様の
作用で第1層の膜(13)の部分的テーパー形状が得ら
れ、最終的に上部がテーパー状(17)で下部が円弧状
(18)の断面形状を有する第2図Iと同様の開口部(
19)が得られる。Another method is to make the insulating film (12) have a two-layer structure without using the third layer film (15), and in this case, the second layer film (15) is not used.
14) and photoresist j! ! This method utilizes the fact that the adhesion between the photoresist layer (16) and the photoresist layer (16) is reduced to some extent, and the etching solution gradually penetrates between the photoresist layer (16) and the second layer film (14) during etching. In this case, if the etching rate β3 of the third layer film (15) is replaced with the penetration rate of the etching solution, a partially tapered shape of the first layer film (13) can be obtained by the same effect, and the final An opening (17) similar to that in Fig. 2I has a tapered upper part (17) and an arcuate lower part (18) in cross-section.
19) is obtained.
本発明は、上述の方法を利用するものであり、次にGa
Asショットキーダイオードに適用した実施例をその製
法と共に説明する。The present invention utilizes the method described above, and then
An embodiment applied to an As Schottky diode will be described together with its manufacturing method.
第1図Aに示すようにGaAs基板(21)の−主面上
に第1層、第2層及び第3層の膜(13)、 (14)
及び(15)からなる絶縁膜(12)を被着形成する。As shown in FIG. 1A, first, second and third layers of films (13), (14) are formed on the main surface of the GaAs substrate (21).
An insulating film (12) consisting of (15) and (15) is deposited.
各層(13)、 (14)及び(15)は例えば表1に
示すと同様のものを用いる。For each layer (13), (14) and (15), the same ones as shown in Table 1 are used, for example.
次に、第1図Bに示すように絶縁膜(12)上に所定の
開口(22)を有するフォトレジスト層(16)を被着
形成した後、第1図Cに示すようにフォトレジスト層(
16)をマスクにして第3層の膜(15)をHF系エツ
チング液で選択エツチングした後、第2層の膜(14)
をCF、及び02のガスを用いたドライエツチングによ
り選択エツチングする。Next, as shown in FIG. 1B, a photoresist layer (16) having a predetermined opening (22) is deposited on the insulating film (12), and then a photoresist layer (16) is formed as shown in FIG. 1C. (
After selectively etching the third layer film (15) with an HF-based etching solution using 16) as a mask, the second layer film (14)
is selectively etched by dry etching using CF and 02 gas.
次に、第1層の膜(13)をHF系エツチング液で選択
エツチングする。このとき50%のオーバーエツチング
を行う。このエツチングでは第2図で説明したと同様の
作用により絶縁膜(12)には上部がテーパー状(17
)となり、下部が円弧状(18)となった断面形状の開
口部(19)が形成される(第1図り参照)。Next, the first layer film (13) is selectively etched using an HF-based etching solution. At this time, 50% overetching is performed. In this etching, the upper part of the insulating film (12) is tapered (17) due to the same effect as explained in FIG.
), and an opening (19) having a cross-sectional shape with an arcuate lower part (18) is formed (see first diagram).
次に、フォトレジスト層(16)を剥離し、第3層の膜
(15)をHF系エツチング液でエンチング除去した後
、第1図上に示すように、開口部(19)を含むように
ショットキー電極即ちショットキーメタル(4)を形成
しGaAs1板(21)との間にショットキー接合を形
成する。各層(13)、 (14)及び(15)を表1
のように設定するときには開口部(19)において非テ
ーパ一部の高さhは2000人、テーパ一部の幅Xは2
.4μmとなる。図示せざるもショットキーメタル(4
)上にはパッドメタルを形成する。こようにして、目的
のGaAsショットキーダイオード(23)を得る。Next, the photoresist layer (16) is peeled off, and the third layer film (15) is etched away using an HF-based etching solution. A Schottky electrode, that is, a Schottky metal (4) is formed, and a Schottky junction is formed between it and the GaAs1 plate (21). Table 1 shows each layer (13), (14) and (15)
When setting as follows, the height h of the non-tapered part of the opening (19) is 2000, and the width X of the tapered part is 2.
.. It becomes 4 μm. Schottky metal (4)
) Form a pad metal on top. In this way, the desired GaAs Schottky diode (23) is obtained.
尚、第3層の膜(15)を用いない方法では、第1図の
工程で第3層の膜(15)に関する部分を省略すれば良
い。In addition, in a method that does not use the third layer film (15), the portion related to the third layer film (15) may be omitted in the process shown in FIG.
上述のGaAsショットキーダイオード(23)によれ
ば、その絶縁膜(12)の開口部(19)の断面形状が
上部でテーパー状(17)となされているので、絶縁膜
(12)の開口部上端縁aの角度が大きくなりショット
キーメタル(4)を含むメタル段切れを防止することが
できると共に、下部では円弧状(18)となされている
ので、シヨ・ントキーメタル(4)とGaAs基板板(
21)との接触部端縁すでの絶縁膜(12)の角度θが
大きくなりGaAs基板(21)の面が臨む開口寸法即
ち開口部幅Wの制御性が良く、その結果、ショットキー
接合面積の制御性を上げることができる。また開口部(
9)の下部が円弧状(18)であるので、ショットキー
接合面積を縮小しても、従来の第4図の場合に比して寄
生容量を抑えることができる。従って、GaAsショッ
トキーダイオードの周波数特性をより向上することがで
きる。According to the above-mentioned GaAs Schottky diode (23), since the cross-sectional shape of the opening (19) of the insulating film (12) is tapered (17) at the upper part, the opening of the insulating film (12) The angle of the upper edge a becomes larger, which prevents metal breakage including the Schottky metal (4), and the lower part is arcuate (18), so that the Schottky metal (4) and GaAs Substrate board (
The angle θ of the insulating film (12) at the edge of the contact portion with the GaAs substrate (21) becomes larger, and the opening dimension, that is, the opening width W, facing the surface of the GaAs substrate (21) is better controlled, and as a result, a Schottky junction is formed. It is possible to improve the controllability of the area. Also, the opening (
Since the lower part of 9) is arcuate (18), even if the Schottky junction area is reduced, the parasitic capacitance can be suppressed compared to the conventional case shown in FIG. Therefore, the frequency characteristics of the GaAs Schottky diode can be further improved.
尚、上側ではショットキーダイオードにおけるショット
キーメタルの形成に適用したが、その他の半導体装置で
絶縁膜の開口部を通して半導体領域にオーミックメタル
を被着形成する場合にも通用可能である。Although the above method is applied to the formation of a Schottky metal in a Schottky diode, it can also be applied to the formation of an ohmic metal on a semiconductor region through an opening in an insulating film in other semiconductor devices.
(発明の効果〕
本発明によれば、半導体領域に絶縁膜の開口部を通して
金属電極が被着されてなる半導体装置におてい、開口部
の断面形成を上部がテーパー状で下部が円弧状として形
成することによって、金属電極の半導体領域との被着面
積の制御性を維持しながら、金属電極の段切れを防止す
ることができる。(Effects of the Invention) According to the present invention, in a semiconductor device in which a metal electrode is adhered to a semiconductor region through an opening in an insulating film, the cross section of the opening is formed so that the upper part is tapered and the lower part is circular. By forming this, it is possible to prevent the metal electrode from breaking while maintaining controllability of the adhesion area of the metal electrode to the semiconductor region.
【図面の簡単な説明】
第1図A−Eは本発明をGaAsショットキーダイオー
ドに適用した場合の製造工程図、第2図A〜■は本発明
に係る絶縁膜の開口部の形成法を示すエツチング経過類
の断面図、第3図及び第4図は夫々従来のGaAsショ
ットキーダイオードの要部の断面図である。
(11)は基体、(12)は3層構造の絶縁膜、(13
) 。
(14)、 (15)はその各層、(16)はフォトレ
ジスト層、(17)はテーパー状、(18)は円弧状、
(21)はGaAs基板である。
1−一一半遍A仁順A
2−・−5i02月夷[Brief Description of the Drawings] Figures 1A to 1E are manufacturing process diagrams when the present invention is applied to a GaAs Schottky diode, and Figures 2A to 2 illustrate the method for forming an opening in an insulating film according to the present invention. 3 and 4 are cross-sectional views of essential parts of a conventional GaAs Schottky diode, respectively. (11) is the substrate, (12) is the three-layer insulating film, (13)
). (14), (15) are the respective layers, (16) is the photoresist layer, (17) is tapered, (18) is circular arc,
(21) is a GaAs substrate. 1-11hanpen A Jinjun A 2-・-5i0February
Claims (1)
されてなる半導体装置において、 上記開口部は上部をテーパー状とし、下部を円弧状とし
た断面形状を有して成る半導体装置。[Claims] In a semiconductor device in which a metal electrode is deposited on a semiconductor region through an opening in an insulating film, the opening has a cross-sectional shape with a tapered upper part and an arcuate lower part. Semiconductor equipment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10433089A JPH02281757A (en) | 1989-04-24 | 1989-04-24 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10433089A JPH02281757A (en) | 1989-04-24 | 1989-04-24 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02281757A true JPH02281757A (en) | 1990-11-19 |
Family
ID=14377925
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10433089A Pending JPH02281757A (en) | 1989-04-24 | 1989-04-24 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02281757A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05183211A (en) * | 1991-11-13 | 1993-07-23 | Alps Electric Co Ltd | Thin film laminated body and formation thereof |
US5933756A (en) * | 1995-10-18 | 1999-08-03 | Ricoh Company, Ltd. | Fabrication process of a semiconductor device having a multilayered interconnection structure |
JP2015046500A (en) * | 2013-08-28 | 2015-03-12 | 三菱電機株式会社 | Silicon carbide semiconductor device |
JP2017098578A (en) * | 2017-01-31 | 2017-06-01 | 三菱電機株式会社 | Silicon carbide semiconductor device and manufacturing method of the same |
-
1989
- 1989-04-24 JP JP10433089A patent/JPH02281757A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05183211A (en) * | 1991-11-13 | 1993-07-23 | Alps Electric Co Ltd | Thin film laminated body and formation thereof |
US5933756A (en) * | 1995-10-18 | 1999-08-03 | Ricoh Company, Ltd. | Fabrication process of a semiconductor device having a multilayered interconnection structure |
JP2015046500A (en) * | 2013-08-28 | 2015-03-12 | 三菱電機株式会社 | Silicon carbide semiconductor device |
JP2017098578A (en) * | 2017-01-31 | 2017-06-01 | 三菱電機株式会社 | Silicon carbide semiconductor device and manufacturing method of the same |
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