JPS60121778A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60121778A
JPS60121778A JP58230292A JP23029283A JPS60121778A JP S60121778 A JPS60121778 A JP S60121778A JP 58230292 A JP58230292 A JP 58230292A JP 23029283 A JP23029283 A JP 23029283A JP S60121778 A JPS60121778 A JP S60121778A
Authority
JP
Japan
Prior art keywords
epitaxial layer
insulating film
layer
electrode
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58230292A
Other languages
Japanese (ja)
Inventor
Tadashi Sugiki
忠 杉木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58230292A priority Critical patent/JPS60121778A/en
Publication of JPS60121778A publication Critical patent/JPS60121778A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a semiconductor device, which operates in a ultra-high frequency region, with high reliability and less in skin effect loss, by coating a P-N junction section as a boundary section between an epitaxial layer and a diffusion layer with an insulating film and forming a metallic film on the surface of a substrate. CONSTITUTION:An epitaxial layer 2 having the same conduction type as a low- resistivity semiconductor substrate 1 is formed on the substrate 1, and an epitaxial layer or a diffusion layer 3 having a conduction type reverse to the epitaxial layer 2 is shaped on the epitaxial layer 2. An electrode metal 4 is formed on the layer 3. The substrate 1 is mesa-etched so as to obtain desired electrical characteristics while using the electrode metal 4 as a mask. An insulating film 6 is formed on the substrate 1. A positive group resist is applied and the whole surface is exposed and developed, thus leaving a resist 7 under the overhang section of the electrode 4. The insulating film 6 is etched while using the photo-resist 7 as a mask, thus leaving the insulating film 6 under the overhang section of the electrode 4. A P-N junction section as a boundary section between the layers 2 and 3 is coated with the insulating film 6. A proper metal is vapor deposited on the surface of the substrate 1 to form a metallic layer 8.

Description

【発明の詳細な説明】 (技術分野) 本発明は半導体装置の製造方法に関し、特に超高周波用
半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device for ultra-high frequencies.

(従来技術) ミリ波等の高い周波数で使用する半導体装置はQを大き
くするために寸法が小さくなり、電極等の加工が困難に
なるため、単純なメサをを採用する場合が多め。
(Prior art) Semiconductor devices used at high frequencies such as millimeter waves have to have smaller dimensions to increase Q, making it difficult to process electrodes, etc., so simple mesas are often used.

メ’I11ダイオードでは表皮効果による損失を少なく
したり、信頼度をあげるためにバックベーションを行な
ったシする方法が種々行なわれている。
Various backbation methods have been used to reduce the loss due to the skin effect and increase the reliability of the Me'I11 diode.

表皮効果による損失を少なくする方法としては第1図に
示すような構成がとられている。第1図におiて、lは
低比抵抗の半導体基板% 2は半導体基板lと同じ導電
をのエピタキシャル層、3は半導体基板lと異なる導電
型のエピタキシャル層又は拡散層、4は電極金属% 5
は金属層である。
As a method of reducing the loss due to the skin effect, a configuration as shown in FIG. 1 has been adopted. In Fig. 1, l is a low resistivity semiconductor substrate %, 2 is an epitaxial layer with the same conductivity as the semiconductor substrate l, 3 is an epitaxial layer or diffusion layer of a different conductivity type from the semiconductor substrate l, and 4 is an electrode metal. % 5
is a metal layer.

すなわち、電極金属4f:マスクにしてメサエッチング
を行なった後、半導体基板に金属層5を蒸着することに
より表皮効果による損失を少なくしていた。
That is, after performing mesa etching using the electrode metal 4f as a mask, the metal layer 5 is deposited on the semiconductor substrate to reduce loss due to the skin effect.

また、信頼度をあげるためのノ(ツシベーシコンとして
は、電極金属4金マスクにメサエッチングを行なった後
、CVD法により絶縁膜を半導体基板l上に被覆した後
、ポジ系のホトレジストを塗布し、全面露光を行な匹、
電極メタル40オーパーツ・ング部の下の部分に絶縁膜
6を残し、PN接合部を絶縁膜で被覆することにより信
頼度の向上をはかつている。
In addition, in order to increase the reliability, after performing mesa etching on the electrode metal 4-metal mask, and coating the semiconductor substrate with an insulating film by the CVD method, a positive photoresist is applied. Fully exposed,
Reliability is improved by leaving an insulating film 6 under the outer ring portion of the electrode metal 40 and covering the PN junction with the insulating film.

しかし前記し友ように高い周波数の半導体装置ではQを
大きくするため寸法が小さくなり、電極等の加工が困難
になり必然的に第1図、第2図の構造のものが製作され
ていた。
However, as mentioned above, in high-frequency semiconductor devices, the dimensions become smaller in order to increase Q, making it difficult to process electrodes, etc., and inevitably the structures shown in FIGS. 1 and 2 have been manufactured.

しかしながら、第1図の半導体基板底面に金属層5を付
着させることによV表皮効果による損失は少なく出来る
がPN接合表面には絶縁膜が形成されていないので信頼
度に欠ける欠点がある。
However, although the loss due to the V skin effect can be reduced by attaching the metal layer 5 to the bottom surface of the semiconductor substrate shown in FIG. 1, there is a drawback that reliability is lacking because no insulating film is formed on the PN junction surface.

一方%第2図のバックベーションをする方法にお^ては
PN接合の保護により信頼度は向上するが、金属層が形
成されていないため表皮効果による損失を低減すること
ができないと^う欠点がありた。
On the other hand, in the backbation method shown in Figure 2, reliability is improved by protecting the PN junction, but the drawback is that it is not possible to reduce loss due to the skin effect because no metal layer is formed. There was.

しかも、前記し友ように寸法が小さいため、これらの問
題点を解決するためには自己整合的方法の採用が強く望
まれていた。
Furthermore, as mentioned above, since the dimensions are small, it has been strongly desired to adopt a self-aligning method in order to solve these problems.

(発明の目的) 本発明の目的は、以上の問題を除去し、比較的簡単な工
程で、超高周波領吠で動作する信頼度の高い表皮効果の
損失が少ない半導体装置の製造方法を提供するにある。
(Objective of the Invention) An object of the present invention is to eliminate the above-mentioned problems and provide a method for manufacturing a highly reliable semiconductor device that operates at ultra-high frequency and has little loss due to the skin effect, using a relatively simple process. It is in.

(発明の構成) 本発明の半導体装置の製造方法は、−導電をの半導体基
板上に半導体基板と同−導電型のエピタキシャル層を形
成する工程と、該エピタキシャル層に該エピタキシャル
層と逆導電型のエピタキシャル層又は拡散層を形成する
工程と、該逆導電壁のエピタキシャル層又は拡散層上に
金属電極を形成する工程と、該金属電極上マスクにして
、前記エピタキシャル層等の形成された半導体基板をメ
サエッチングすると共に前記金属電極のオーバーへンー
グ部を形成する工程と、メサエッチングされた半導体基
板表面に絶縁膜を形成しホトエツチング技術により電極
のオーパーツ・ンダ部の下の部分に絶縁膜を残す工程と
、該半導体基板に金属を蒸着しホトエツチング技術によ
り金属電極の上及び前記オーバーハング部の下の部分を
除く半導体基板表面に金属層を形成する工程と、前記半
導体基板裏面にオーミック電極を形成する工程とを含ん
で構成される。
(Structure of the Invention) A method for manufacturing a semiconductor device of the present invention includes a step of forming an epitaxial layer having the same conductivity type as the semiconductor substrate on a semiconductor substrate having conductivity, and forming an epitaxial layer on the epitaxial layer having a conductivity type opposite to that of the epitaxial layer. a step of forming an epitaxial layer or a diffusion layer of the opposite conductive wall, a step of forming a metal electrode on the epitaxial layer or the diffusion layer of the reverse conductive wall, and a semiconductor substrate on which the epitaxial layer etc. is formed by using a mask on the metal electrode. A step of mesa-etching the metal electrode and forming an overhang portion of the metal electrode, forming an insulating film on the surface of the mesa-etched semiconductor substrate, and using a photo-etching technique to form an insulating film under the overhang portion of the electrode. a step of depositing metal on the semiconductor substrate and forming a metal layer on the surface of the semiconductor substrate except for the portion above the metal electrode and under the overhang portion using a photo-etching technique; and forming an ohmic electrode on the back surface of the semiconductor substrate. The structure includes a step of forming.

(実施例) 以下2本発明の実施例について、図面を参照して説明す
る。
(Example) Two examples of the present invention will be described below with reference to the drawings.

第3図(a)〜(e)は本発明の詳細な説明のための工
程順に示した断面図である。
FIGS. 3(a) to 3(e) are cross-sectional views showing the process order for detailed explanation of the present invention.

第3図18)に示すように、低比抵抗半導体基板l上に
、基板と同一導電型のエピタキシャル層2を形成し1次
にエピタキシャル層2上にエピタキシャル層2と逆導電
酸のエピタキシャル層又は拡散層3を形成する。次いで
エピタキシャル層又は拡散層3の上に金属を蒸着、ホト
エツチング技術を使い電極金属4を形成する。
As shown in FIG. 3 18), an epitaxial layer 2 of the same conductivity type as the substrate is formed on a low resistivity semiconductor substrate l, and then an epitaxial layer 2 or an epitaxial layer of a conductivity opposite to that of the epitaxial layer 2 is formed on the epitaxial layer 2. A diffusion layer 3 is formed. Next, metal is deposited on the epitaxial layer or diffusion layer 3, and an electrode metal 4 is formed using a photoetching technique.

次に、第3図(b)に示すように、電極金属4をマスク
として硫酸系のエツチング液により半導体基板を所望の
電気的特性が得られるようメサエッチングする。このと
き電極金属4の下はオーバーエツチングしてオーバーハ
ング部を形成する。なおオーバーエツチングの横方向の
深さは、絶縁膜とホトレジストの膜厚の和程度の深さが
望まれる。
Next, as shown in FIG. 3(b), the semiconductor substrate is mesa-etched using a sulfuric acid-based etching solution using the electrode metal 4 as a mask so as to obtain desired electrical characteristics. At this time, the bottom of the electrode metal 4 is over-etched to form an overhang portion. The lateral depth of the overetching is preferably approximately the sum of the thicknesses of the insulating film and the photoresist.

次に、第3図(C)に示すように、半導体基板上にCV
D法により絶縁膜6を形成する。次^でポジ系のレジス
トを塗布して全面露光、現像することにより電極4のオ
ーバーハング部の下のレジスト7が残り、他の部分のレ
ジストはすべて除去される。
Next, as shown in FIG. 3(C), CV
An insulating film 6 is formed by method D. Next, a positive resist is applied, exposed to light over the entire surface, and developed, so that the resist 7 under the overhang portion of the electrode 4 remains, and all other resists are removed.

次に第3図(d)に示すように、ホトレジスト71ft
:マスクとして適当なエツチング液により絶縁膜をエツ
チングすることにより電極4のオーバーハング部の下の
絶縁膜6を残すことができる。この絶#膜6はエピタキ
シャル層2とエピタキシャル又は拡散層3との境界部で
あるP −N接合部を被覆している。次いで字導体基板
表面に適当な金属を蒸着し、金属層8を形成する。
Next, as shown in FIG. 3(d), 71 ft of photoresist
: By etching the insulating film using an appropriate etching solution as a mask, the insulating film 6 under the overhang portion of the electrode 4 can be left. This insulation film 6 covers the PN junction which is the boundary between the epitaxial layer 2 and the epitaxial or diffusion layer 3. Next, a suitable metal is deposited on the surface of the conductor substrate to form a metal layer 8.

次に、第3図(e)に示すように、半導体基板の裏面を
機械的又は化学的に食刻し所定の厚さに仕上げた後、オ
ーミック電極9t−形成する。
Next, as shown in FIG. 3(e), the back surface of the semiconductor substrate is mechanically or chemically etched to a predetermined thickness, and then an ohmic electrode 9t is formed.

以上により本発明の一実施例の半導体装置が得られるが
1本実施例ではP−N接合部は絶縁膜6により完全に被
覆されているので信頼度の向上がはかれる。
As described above, a semiconductor device according to an embodiment of the present invention is obtained. In this embodiment, the P-N junction portion is completely covered with the insulating film 6, so that reliability can be improved.

まfc、低比抵抗層lの表面には金属層8が被着されて
いるので表皮効果による損失を減小させることができる
Since the metal layer 8 is deposited on the surface of the low resistivity layer 1, loss due to the skin effect can be reduced.

また、これらの製造方法の主要工程は自己整合的に実施
できるので小壁の半導体装置を確実に製造することがで
きる。
Furthermore, since the main steps of these manufacturing methods can be carried out in a self-aligned manner, small-walled semiconductor devices can be reliably manufactured.

(発明の効果) 以上説明したとおり、本発明によれば、比較的簡単な工
程で、超高周波領威で動作する信頼度の高い衆皮効果の
損失が少ない半導体装置を得ることができる。
(Effects of the Invention) As described above, according to the present invention, it is possible to obtain a highly reliable semiconductor device that operates at ultra-high frequency power and has little loss due to the collective skin effect, through a relatively simple process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は従来の超高周波用の半導体装置の断面
図、第3図(a)〜(e)は本発明の一実施例を説明す
るための工程順に示した断面図である。 ■・・・・−・低比抵抗半導体基板、2・・・・・・l
と同一導電をのエピタキシャル層、3・・・・・・2と
異なる13電蟹のエピタキシャル層又は拡散層、4・・
・・・・電極金属、5.8・・・−・・金属層、6・・
・・・−絶縁膜、7・・・・・・ホトレジスト、9・・
・・・・オーミック電極。 峯1回 卒2旧 v−3回
1 and 2 are cross-sectional views of a conventional ultra-high frequency semiconductor device, and FIGS. 3(a) to 3(e) are cross-sectional views shown in the order of steps for explaining an embodiment of the present invention. . ■・・・・・・−・Low resistivity semiconductor substrate, 2・・・・・・l
Epitaxial layer with the same conductivity as 3... 13 epitaxial layer or diffusion layer different from 2, 4...
...Electrode metal, 5.8...-Metal layer, 6...
...-Insulating film, 7... Photoresist, 9...
...Ohmic electrode. Mine 1st year graduate 2nd year old v-3rd time

Claims (1)

【特許請求の範囲】[Claims] 一導電型の半導体基板上に半導体基板と同−導電蟹のエ
ピタキシャル層を形成する工程と、該エピタキシャル層
に該エピタキシャル層と逆導電賊のエピタキシャル層又
は拡散層を形成する工程と、該逆導電戴のエピタキシャ
ル層又は拡散層上に金属電極を形成する工程と、該金属
電極をマスクにして、前記エピタキシャル層等の形成さ
れた半導体基板をメチエツチングすると共に前記金属電
極のオーバーハング部を形成する工程と、メサエッチン
グされた半導体基板表面に絶縁膜を形成しホトエツチン
グ技術により電極のオーバーハング部の下の部分に絶縁
膜を残す工程と、該半導体基板に金属を蒸着しホトエツ
チング技術により金属電極の上及び前記オーバーハング
部の下の部分を除く半導体基板表面に金属層を形成する
工程と、前記半導体基板裏面にオーミック電極を形成す
る工程とを含むことを特徴とする半導体装置の製造方法
a step of forming an epitaxial layer of the same conductivity as the semiconductor substrate on a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer or a diffusion layer of conductivity opposite to the epitaxial layer in the epitaxial layer, and a step of forming an epitaxial layer or a diffusion layer of conductivity opposite to the epitaxial layer; A step of forming a metal electrode on the epitaxial layer or diffusion layer, and a step of etching the semiconductor substrate on which the epitaxial layer etc. is formed, using the metal electrode as a mask, and forming an overhang portion of the metal electrode. , forming an insulating film on the surface of the mesa-etched semiconductor substrate and using photo-etching technology to leave the insulating film under the overhang of the electrode; and depositing metal on the semiconductor substrate and using photo-etching technology to leave the insulating film on the metal electrode. A method for manufacturing a semiconductor device, comprising the steps of: forming a metal layer on the surface of the semiconductor substrate except for a portion below the overhang portion; and forming an ohmic electrode on the back surface of the semiconductor substrate.
JP58230292A 1983-12-06 1983-12-06 Manufacture of semiconductor device Pending JPS60121778A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58230292A JPS60121778A (en) 1983-12-06 1983-12-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58230292A JPS60121778A (en) 1983-12-06 1983-12-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60121778A true JPS60121778A (en) 1985-06-29

Family

ID=16905526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58230292A Pending JPS60121778A (en) 1983-12-06 1983-12-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60121778A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61191077A (en) * 1985-02-20 1986-08-25 Rohm Co Ltd High frequency diode
JPH01503423A (en) * 1987-05-14 1989-11-16 ヒユーズ・エアクラフト・カンパニー 2 terminal semiconductor diode device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61191077A (en) * 1985-02-20 1986-08-25 Rohm Co Ltd High frequency diode
JPH01503423A (en) * 1987-05-14 1989-11-16 ヒユーズ・エアクラフト・カンパニー 2 terminal semiconductor diode device

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