JPS6161545B2 - - Google Patents
Info
- Publication number
- JPS6161545B2 JPS6161545B2 JP1790580A JP1790580A JPS6161545B2 JP S6161545 B2 JPS6161545 B2 JP S6161545B2 JP 1790580 A JP1790580 A JP 1790580A JP 1790580 A JP1790580 A JP 1790580A JP S6161545 B2 JPS6161545 B2 JP S6161545B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- insulating film
- silicon film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
この発明はMOS型半導体装置の製造方法に係
り、特に半導体基板あるいはゲート電極と配線金
属とを結合させるためのコンタクト穴を絶縁膜に
形成する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a MOS type semiconductor device, and more particularly to a method of forming a contact hole in an insulating film for coupling a semiconductor substrate or a gate electrode to a wiring metal.
従来のMOS型半導体装置の製造方法、特に上
記コンタクト穴の形成方法および配線の形成方法
は次の方法が公知である。すなわち、第１図ａに
おいて、１はシリコン基板、２はシリコン基板１
と反対導電型の拡散層、３はゲート酸化膜、４は
通常導電型の多結晶シリコンが用いられるゲート
電極、５は寄生容量効果を防ぐため、通常厚い膜
が使用されるフイールド部の酸化膜であり、まず
これらの全面に絶縁膜６を形成する（第１図ｂ参
照）。この絶縁膜６は、通常化学気相蒸着法によ
り形成され、一般にはパツシベーシヨン効果被覆
性などを考慮し、リンガラス膜（P2O5／SiO2）が
用いられる。 The following methods are known as conventional methods for manufacturing MOS semiconductor devices, particularly for forming the contact holes and wiring. That is, in FIG. 1a, 1 is a silicon substrate, 2 is a silicon substrate 1
3 is a gate oxide film, 4 is a gate electrode in which polycrystalline silicon of normal conductivity type is used, and 5 is an oxide film in the field part, which is usually thick to prevent parasitic capacitance effects. First, an insulating film 6 is formed on these entire surfaces (see FIG. 1b). This insulating film 6 is usually formed by chemical vapor deposition, and generally a phosphorous glass film (P 2 O 5 /SiO 2 ) is used in consideration of passivation effect and coverage.
次いで、上記絶縁膜６上にホトレジスト材を塗
布してホトレジスト膜７を形成し、さらに写真食
刻によりパターニングを行つてホトレジスト膜７
に開口部８を形成する（第１図ｃ参照）。 Next, a photoresist material is applied on the insulating film 6 to form a photoresist film 7, and patterning is performed by photolithography to form the photoresist film 7.
An opening 8 is formed in (see FIG. 1c).
そして、このホトレジスト膜７をマスクとして
絶縁膜６を拡散層２およびゲート電極４に至るま
で化学エツチを行い、コンタクト穴９を形成する
（第１図ｄ参照）。 Then, using the photoresist film 7 as a mask, the insulating film 6 is chemically etched down to the diffusion layer 2 and the gate electrode 4 to form a contact hole 9 (see FIG. 1d).
しかる後は、ホトレジスト膜７を除去した上で
配線金属１０を蒸着し、さらに写真食刻、エツチ
ングにより配線金属１０を所定のパターンに形成
するものである（第１図ｅ参照）。 Thereafter, the photoresist film 7 is removed and the wiring metal 10 is deposited, and the wiring metal 10 is further formed into a predetermined pattern by photolithography and etching (see FIG. 1e).
しかるに、このような従来の方法は次のような
欠点を有する。 However, such conventional methods have the following drawbacks.
(1) 絶縁膜６のエツチングのマスクとしてホトレ
ジスト膜７を用いているが、ホトレジスト膜７
の場合は、絶縁膜６とホトレジスト膜７との密
着性の問題により界面におけるエツチング液の
浸み込みが発生し、安定した形状のコンタクト
穴９を再現性よく得られない。そこで、上記界
面の密着性を改善する手段として、ベーキング
を繰り返すことが通常行われるが、やはり安定
した形状のコンタクト穴９を再現性よく得るこ
とは困難であり、しかもこの場合は工程が非常
に繁雑となる。(1) The photoresist film 7 is used as a mask for etching the insulating film 6;
In this case, the problem of adhesion between the insulating film 6 and the photoresist film 7 causes the etching solution to seep into the interface, making it impossible to obtain a contact hole 9 with a stable shape with good reproducibility. Therefore, as a means to improve the adhesion of the interface, repeated baking is usually performed, but it is still difficult to obtain a contact hole 9 with a stable shape with good reproducibility, and in this case, the process is extremely difficult. It becomes complicated.
(2) コンタクト穴９の形状としては、できる限り
傾斜が緩いことが望ましいが、そのように再現
性よく制御することが困難であり、第１図ｄの
ように急峻になることが多い。そして、コンタ
クト穴９の傾斜が急峻になると、第１図ｅに示
すようにその開口端部において配線金属１０の
厚みが薄くなり易く、信頼性上問題がある。(2) Although it is desirable that the shape of the contact hole 9 be as gentle as possible, it is difficult to control the shape with good reproducibility, and the shape often becomes steep as shown in FIG. 1d. If the slope of the contact hole 9 becomes steep, the thickness of the wiring metal 10 tends to become thinner at the opening end, as shown in FIG. 1e, which poses a problem in terms of reliability.
(3) 絶縁膜６が露出した状態で、その上に配線金
属１０を蒸着することになるが、配線金属１０
を電子ビームやスパツタ方式で蒸着すると、露
出している絶縁膜６中にイオンなどを励起して
半導体装置の完成後に、正電荷のスロートラツ
ピング効果などの特性変動を生じ易くなる。(3) With the insulating film 6 exposed, the wiring metal 10 is deposited on it.
When evaporated by an electron beam or sputtering method, ions and the like are excited in the exposed insulating film 6, which tends to cause characteristic fluctuations such as slow trapping effect of positive charges after the semiconductor device is completed.
この発明は上記の点に鑑みなされたもので、
簡便な方法により、安定した形状のコンタクト
穴を再現性よく得ることができるとともに、コ
ンタクト穴を望ましい形状とすることができ、
しかも配線金属蒸着時の絶縁膜の電子線損傷を
防止することが可能となり、工程の簡素化、歩
留り、信頼性の向上を図ることができるMOS
型半導体装置の製造方法を提供することを目的
とする。 This invention was made in view of the above points,
By using a simple method, it is possible to obtain a contact hole with a stable shape with good reproducibility, and also to make the contact hole into a desired shape.
Moreover, it is possible to prevent electron beam damage to the insulating film during wiring metal evaporation, making it possible to simplify the process and improve yield and reliability.
The object of the present invention is to provide a method for manufacturing a type semiconductor device.
以下この発明の実施例を図面を参照して説明す
る。第２図ａないしｈはこの発明の実施例を説明
するための図である。第２図ａにおいて、１１は
単結晶のシリコン基板（半導体基板）、１２はシ
リコン基板１１と反対導電型の拡散層、１３はゲ
ート酸化膜、１４はゲート電極、１５はフイール
ド酸化膜である。実施例では、まず、上記拡散層
１２などを有するるシリコン基板１１の全表面
に、たとえばリンガラスからなる絶縁膜１６を形
成し、さらにその上に多結晶シリコン膜１７を形
成する（第２図ａ参照）。 Embodiments of the present invention will be described below with reference to the drawings. FIGS. 2a to 2h are diagrams for explaining an embodiment of the present invention. In FIG. 2a, 11 is a single crystal silicon substrate (semiconductor substrate), 12 is a diffusion layer of the opposite conductivity type to the silicon substrate 11, 13 is a gate oxide film, 14 is a gate electrode, and 15 is a field oxide film. In this embodiment, first, an insulating film 16 made of phosphorus glass, for example, is formed on the entire surface of the silicon substrate 11 having the diffusion layer 12, etc., and then a polycrystalline silicon film 17 is formed thereon (see FIG. 2). (see a).
次に、多結晶シリコン膜１７上にホトレジスト
材を塗布してホトレジスト膜１８を形成した後、
それのパターニングを行い、開口部１９をホトレ
ジスト膜１８に形成することにより多結晶シリコ
ン膜１７を露出させる（第２図ｂ参照）。 Next, after coating a photoresist material on the polycrystalline silicon film 17 to form a photoresist film 18,
The polycrystalline silicon film 17 is exposed by patterning it and forming an opening 19 in the photoresist film 18 (see FIG. 2b).
しかる後は、ホトレジスト膜１８の開口部１９
を通して、つまりホトレジスト膜１８をマスクと
して多結晶シリコン膜１７を除去し、多結晶シリ
コン膜１７に除去部２０を形成することにより絶
縁膜１６を露出させる（第２図ｃ参照）。 After that, the opening 19 of the photoresist film 18 is
In other words, the polycrystalline silicon film 17 is removed using the photoresist film 18 as a mask, and the insulating film 16 is exposed by forming a removed portion 20 in the polycrystalline silicon film 17 (see FIG. 2c).
次いで、ホトレジスト膜１８のい突開口部１９
および多結晶シリコン膜１７の除去部２０を通し
て、つまりホトレジスト膜１８と多結晶シリコン
膜１７をマスクとして絶縁膜１６をエツチングす
る。この場合、絶縁膜１６は、拡散層１２および
ゲート電極１４に達するまでエツチングせずに、
全膜厚の半分程度でエツチングを中止する。その
結果、絶縁膜１６には皿状の空胴部２１が形成さ
れる（第２図ｄ参照）。 Next, the protruding opening 19 of the photoresist film 18 is
Then, the insulating film 16 is etched through the removed portion 20 of the polycrystalline silicon film 17, that is, using the photoresist film 18 and the polycrystalline silicon film 17 as a mask. In this case, the insulating film 16 is not etched until it reaches the diffusion layer 12 and the gate electrode 14.
Etching is stopped when the total film thickness is about half. As a result, a dish-shaped cavity 21 is formed in the insulating film 16 (see FIG. 2d).
その後、再度ホトレジスト膜１８をマスクして
多結晶シリコン膜１７のエツチングを行う。この
場合は、多結晶シリコン膜１７の除去部２０を拡
張させるために、多結晶シリコン膜１７と絶縁膜
１６の界面より、除去部２０側方の多結晶シリコ
ン膜１７をサイドエツチングするものである（第
２図ｅ参照）。 Thereafter, the polycrystalline silicon film 17 is etched while masking the photoresist film 18 again. In this case, in order to expand the removed portion 20 of the polycrystalline silicon film 17, the polycrystalline silicon film 17 on the side of the removed portion 20 is side-etched from the interface between the polycrystalline silicon film 17 and the insulating film 16. (See Figure 2e).
しかる後は、ホトレジスト膜１８を除去した上
で、多結晶シリコン膜１７の拡張された除去部２
０を通して、つまりり多結晶シリコン膜１７をマ
スクとして絶縁膜１６をエツチングすることによ
り、拡散層１２およびゲート電極１４に到達する
階段状ののテーパコンタクト穴２２を絶縁膜１６
に形成する（第２図ｆ参照）。 After that, after removing the photoresist film 18, the expanded removed portion 2 of the polycrystalline silicon film 17 is removed.
In other words, by etching the insulating film 16 using the polycrystalline silicon film 17 as a mask, a step-like tapered contact hole 22 reaching the diffusion layer 12 and the gate electrode 14 is formed in the insulating film 16.
(see Figure 2 f).
そして、上記コンタクト穴２２を形成した後
は、多結晶シリコン膜１７を残存させた状態で全
面に配線金属２３を蒸着し、さらに写真食刻、エ
ツチングを行つて配線金属２３を所定のパターン
に形成するものである（第２図ｇ，ｈ参照）。こ
の場合、必然的にコンタクト部分以外のフイール
ド上のの配線は、配線金属２３、多結晶シリコン
膜１７の二層構造となる。 After forming the contact hole 22, a wiring metal 23 is deposited on the entire surface with the polycrystalline silicon film 17 remaining, and then photolithography and etching are performed to form the wiring metal 23 into a predetermined pattern. (See Figure 2 g and h). In this case, the wiring on the field other than the contact portion inevitably has a two-layer structure of the wiring metal 23 and the polycrystalline silicon film 17.
以上実施例で詳述したように、この発明の方法
では、絶縁膜上に多結晶シリコン膜を形成し、こ
の多結晶シリコン膜をマスクとして絶縁膜のエツ
チングを行う。したがつて、簡単な工程により、
絶縁膜とマスクとの密着性の問題を考慮すること
なく極めて安定した形状のコンタクト穴を再現性
よく得ることができ、歩留りが向上する。 As described in detail in the embodiments above, in the method of the present invention, a polycrystalline silicon film is formed on an insulating film, and the insulating film is etched using this polycrystalline silicon film as a mask. Therefore, through a simple process,
Contact holes with extremely stable shapes can be obtained with good reproducibility without considering the problem of adhesion between the insulating film and the mask, improving yield.
また、多結晶シリコン膜奪の除去部を通して絶
縁膜を全膜厚の半分程度皿状にエツチングした
後、多結晶シリコン膜の除去部を拡張した上で、
再度その拡張された除去部を通して絶縁膜をエツ
チングすることによりコンタクト穴を形成する。
したがつて、階段状テーパのコンタクト穴を得る
ことができ、このコンタクト穴によれば、その開
口端部において配線金属が薄くなることが防止さ
れ、配線の信頼性を上げることができる。この効
果は、特に配線金属膜厚に対して絶縁膜厚が大き
い場合、顕著である。 In addition, after etching the insulating film into a dish shape through the removed portion of the polycrystalline silicon film, about half of the total film thickness, and after expanding the removed portion of the polycrystalline silicon film,
A contact hole is formed by etching the insulating film through the expanded removed portion again.
Therefore, a step-like tapered contact hole can be obtained, and this contact hole prevents the wiring metal from becoming thinner at the open end, thereby increasing the reliability of the wiring. This effect is particularly noticeable when the thickness of the insulating film is greater than the thickness of the wiring metal film.
さらに、エツチングマスクとして用いた多結晶
シリコン膜を絶縁膜上に残した状態で配線金属の
蒸着を行う。したがつて、配線金属蒸着時の絶縁
膜の電子線損傷を防止することができ、信頼性を
上げることができる。また、フイールド上の配線
構造が二層となるので、配線金属としてアルミニ
ウムなどを用いた場合、エレクトロマイグレーシ
ヨンが減少され配線寿命の向上が期待される。 Furthermore, wiring metal is vapor-deposited while the polycrystalline silicon film used as an etching mask remains on the insulating film. Therefore, damage to the insulating film by electron beams during wiring metal deposition can be prevented, and reliability can be improved. Furthermore, since the wiring structure on the field is two-layered, when aluminum or the like is used as the wiring metal, it is expected that electromigration will be reduced and the life of the wiring will be improved.
第１図ａないしｅは従来のMOS型半導体装置
の製造方法におけるコンタクト穴の形成方法およ
び配線の形成方法を説明するための図、第２図ａ
ないしｈはこの発明によるMOS型半導体装置の
製造方法の実施例を説明するための図である。
１１……シリコン基板、１６……絶縁膜、１７
……多結晶シリコン膜、１８……ホトレジスト
膜、１９……開口部、２０……除去部、２１……
空胴部、２２……コンタクト穴。
Figures 1a to 1e are diagrams for explaining the method of forming contact holes and the method of forming interconnections in the conventional manufacturing method of MOS type semiconductor devices, and Figure 2a
1 to 3 are diagrams for explaining an embodiment of a method for manufacturing a MOS type semiconductor device according to the present invention. 11...Silicon substrate, 16...Insulating film, 17
... Polycrystalline silicon film, 18 ... Photoresist film, 19 ... Opening, 20 ... Removal section, 21 ...
Cavity part, 22...Contact hole.
Claims (1)
と、この絶縁膜上に多結晶シリコン膜を形成する
工程と、この多結晶シリコン膜上にレジスト膜を
塗布した後、多結晶シリコン膜の表面を露出させ
るため、レジスト膜に開口部を形成する工程と、
この開口部を通して上記多結晶シリコン膜を除去
し、上記絶縁膜の表面を露出させる工程と、上記
開口部および多結晶シリコン膜の除去部を通して
絶縁膜を除去し、絶縁膜に皿状の空胴部を形成す
る工程と、上記多結晶シリコン膜の除去部を拡張
するため、除去部側方の多結晶シリコン膜をサイ
ドエツチングする工程と、上記レジスト膜を除去
した後、上記多結晶シリコン膜の拡張された除去
部を通して上記絶縁膜をエツチングすることによ
り、階段状のテーパコンタクト穴を絶縁膜に形成
する工程とを具備することを特徴とするMOS型
半導体装置の製造方法。 ２ 絶縁膜がリンガラス、半導体基板が単結晶シ
リコンからなることを特徴とする特許請求の範囲
第１項記載のMOS型半導体装置の製造方法。[Claims] 1. A process of forming an insulating film on the surface of a semiconductor substrate, a process of forming a polycrystalline silicon film on this insulating film, and a process of forming a polycrystalline silicon film on the polycrystalline silicon film after applying a resist film on the polycrystalline silicon film. forming an opening in the resist film to expose the surface of the crystalline silicon film;
removing the polycrystalline silicon film through the opening to expose the surface of the insulating film; and removing the insulating film through the opening and the removed portion of the polycrystalline silicon film to form a dish-shaped cavity in the insulating film. a step of side etching the polycrystalline silicon film on the sides of the removed portion in order to expand the removed portion of the polycrystalline silicon film; and a step of side etching the polycrystalline silicon film on the side of the removed portion after removing the resist film A method of manufacturing a MOS type semiconductor device, comprising the step of etching the insulating film through the expanded removal portion to form a step-like tapered contact hole in the insulating film. 2. The method of manufacturing a MOS type semiconductor device according to claim 1, wherein the insulating film is made of phosphorus glass and the semiconductor substrate is made of single crystal silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1790580A JPS56115566A (en) | 1980-02-18 | 1980-02-18 | Manufacture of mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1790580A JPS56115566A (en) | 1980-02-18 | 1980-02-18 | Manufacture of mos semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56115566A JPS56115566A (en) | 1981-09-10 |
| JPS6161545B2 true JPS6161545B2 (en) | 1986-12-26 |
Family
ID=11956752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1790580A Granted JPS56115566A (en) | 1980-02-18 | 1980-02-18 | Manufacture of mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56115566A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02115857A (en) * | 1988-10-26 | 1990-04-27 | Buyoudou Seisanbu:Kk | Method for registration of ps plate and plural sheets of films |
| JPH02115856A (en) * | 1988-10-26 | 1990-04-27 | Buyoudou Seisanbu:Kk | Method for registration of ps plate and plural sheets of films |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01255265A (en) * | 1988-04-05 | 1989-10-12 | Nec Corp | Manufacture of semiconductor device |
-
1980
- 1980-02-18 JP JP1790580A patent/JPS56115566A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02115857A (en) * | 1988-10-26 | 1990-04-27 | Buyoudou Seisanbu:Kk | Method for registration of ps plate and plural sheets of films |
| JPH02115856A (en) * | 1988-10-26 | 1990-04-27 | Buyoudou Seisanbu:Kk | Method for registration of ps plate and plural sheets of films |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56115566A (en) | 1981-09-10 |
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