JPH11121457A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH11121457A
JPH11121457A JP9283786A JP28378697A JPH11121457A JP H11121457 A JPH11121457 A JP H11121457A JP 9283786 A JP9283786 A JP 9283786A JP 28378697 A JP28378697 A JP 28378697A JP H11121457 A JPH11121457 A JP H11121457A
Authority
JP
Japan
Prior art keywords
insulating film
pad electrode
semiconductor device
forming
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9283786A
Other languages
Japanese (ja)
Inventor
Masanori Kasai
正礼 河西
Mitsunori Fukura
満徳 福羅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP9283786A priority Critical patent/JPH11121457A/en
Publication of JPH11121457A publication Critical patent/JPH11121457A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve adhesion between an insulating film and a metallic pad electrode and between the pad electrode and a wire, by forming the insulating film and then making irregularities on the surfaces of the insulating film and the pad electrode in a bonding pad region to spread contact areas between the insulating film and the pad electrode and between the pad electrode and wire. SOLUTION: An insulating film 2 is formed on a semiconductor substrate 1, and a photoresist 6 is coated on the film 2 as an etching mask to an etching mask pattern in a bonding pad region. Next, the substrate is etched with use of the etching mask pattern of the photoresist 6 to make irregularities on the surface of the insulating film 2 in the pad region. Further, a metallic pad electrode 3 is formed so that the rough surface of the film 2 is reflected on the surface of the electrode 3. Thereafter, a protective film 4 is formed and a wire 5 is connected to the pad electrode 4.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置の内部
回路素子とワイヤとの接続に必要なボンディングパッド
領域を有する半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a bonding pad region necessary for connecting an internal circuit element of a semiconductor device to a wire.

【０００２】[0002]

【従来の技術】近年、半導体集積回路は微細化が進行
し、前記半導体集積回路素子とワイヤを接続するボンデ
ィングパッド領域の面積が縮小している。2. Description of the Related Art In recent years, semiconductor integrated circuits have been miniaturized, and the area of a bonding pad region for connecting the semiconductor integrated circuit element to a wire has been reduced.

【０００３】以下に、従来の半導体装置の製造方法につ
いて説明する。図１４〜１７は、従来の半導体装置の製
造方法の工程断面図である。図１４において半導体基板
１上に周知のＣＶＤ（ｃｈｅｍｉｃａｌ ｖａｐｏｕｒ
ｄｅｐｏｓｉｔｉｏｎ）法で絶縁膜２を形成する。図
１５においてボンディングパッド領域の前記絶縁膜２上
に金属パッド電極４を周知のスパッタ、リソグラフィ
ー、エッチングにてパターンを形成する。さらに、図１
６において前記金属パッド電極３上にボンディング窓を
開口した保護膜４を形成する。その後、図１７において
前記ボンディング窓を通してワイヤ５を前記金属パッド
電極３に接続する。[0003] A conventional method for manufacturing a semiconductor device will be described below. 14 to 17 are process cross-sectional views of a conventional method for manufacturing a semiconductor device. In FIG. 14, a well-known CVD (chemical vapor) is formed on a semiconductor substrate 1.
The insulating film 2 is formed by a deposition method. In FIG. 15, a pattern of a metal pad electrode 4 is formed on the insulating film 2 in the bonding pad region by well-known sputtering, lithography, and etching. Further, FIG.
In 6, a protective film 4 having a bonding window is formed on the metal pad electrode 3. Thereafter, in FIG. 17, the wire 5 is connected to the metal pad electrode 3 through the bonding window.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、上記の
従来例の半導体装置の製造方法においては、絶縁膜２と
金属パッド電極３及び、金属パッド電極３とワイヤ５と
の接触面積が小さいため接着性が弱く、ワイヤボンディ
ング時あるいはワイヤボンディング後に絶縁膜２と金属
パッド電極３または、金属パッド電極３とワイヤ５のそ
れぞれの界面で剥がれが発生するという欠点がある。However, in the above-described conventional method for manufacturing a semiconductor device, the contact area between the insulating film 2 and the metal pad electrode 3 and between the metal pad electrode 3 and the wire 5 are small, so that the adhesive property is low. However, there is a disadvantage that peeling occurs at the interface between the insulating film 2 and the metal pad electrode 3 or at the interface between the metal pad electrode 3 and the wire 5 during or after wire bonding.

【０００５】上記課題について鑑み、本発明の目的は上
記の課題を解決するもので金属パッド電極と絶縁膜及
び、金属パッド電極とワイヤとの接着性を向上した半導
体装置の製造方法を提供するものである。In view of the above problems, an object of the present invention is to solve the above problems and to provide a method of manufacturing a semiconductor device with improved adhesion between a metal pad electrode and an insulating film and between a metal pad electrode and a wire. It is.

【０００６】[0006]

【課題を解決するための手段】この目的を達成するため
に、本発明の半導体装置の製造方法は、半導体基板上に
絶縁膜を形成した後、ボンディングパッド領域内の絶縁
膜表面に凹凸を形成するためのエッチングマスクを形成
する工程と、エッチングマスクを介してボンディングパ
ッド領域内の絶縁膜をエッチングし凹凸を形成する工程
と、ボンディングパッド領域内に絶縁膜の凹凸形状によ
り表面が凹凸形状となる金属パッド電極パターンを形成
する工程とを有することを特徴とする。In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention comprises forming an insulating film on a semiconductor substrate and then forming irregularities on the surface of the insulating film in a bonding pad region. Forming an etching mask for performing the etching, etching the insulating film in the bonding pad region through the etching mask to form irregularities, and forming an irregular shape in the bonding pad region due to the irregularities of the insulating film. Forming a metal pad electrode pattern.

【０００７】また、本発明の半導体の製造方法は、半導
体基板上に絶縁膜を形成した後、絶縁膜上に薄膜を形成
する工程と、ボンディングパッド領域内に凹凸を有する
ように薄膜の一部を残したエッチングマスクを形成する
工程と、エッチングマスクを介してボンディングパッド
領域内の薄膜をエッチングし絶縁膜表面に凹凸を形成す
る工程と、ボンディングパッド領域内に絶縁膜と薄膜と
からなる凹凸形状により表面が凹凸形状となる金属パッ
ド電極パターンを形成する工程とを有することを特徴と
する。Further, according to the method of manufacturing a semiconductor of the present invention, after forming an insulating film on a semiconductor substrate, a thin film is formed on the insulating film, and a part of the thin film is formed so as to have unevenness in a bonding pad region. Forming an etching mask with the pattern remaining, etching a thin film in the bonding pad region through the etching mask to form irregularities on the surface of the insulating film, and forming an irregular shape formed of the insulating film and the thin film in the bonding pad region. Forming a metal pad electrode pattern having an uneven surface.

【０００８】[0008]

【発明の実施の形態】以下、本発明の半導体装置の製造
方法における第１の実施の形態について、図１〜６に示
す工程断面図を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to sectional views shown in FIGS.

【０００９】図１は、半導体基板１、絶縁膜２が従来の
技術と同様の方法で形成される。図２において、絶縁膜
２にエッチングマスクとしてフォトレジスト６を塗布
し、ボンディングパッド領域内にエッチングマスクパタ
ーンを形成する。図３において前記フォトレジスト６に
よるエッチングマスクパターンを介してエッチングを行
うことで前記ボンディングパッド領域内の絶縁膜２表面
に凹凸を形成する。さらに、図４に示すように金属パッ
ド電極３を絶縁膜２の表面の凹凸形状が金属パッド電極
３表面に反映されるように形成する。その後、図５に示
すように従来の技術と同様の方法で、保護膜４を形成
し、図６に示すようにワイヤ５を金属パッド電極４に接
続を行う。In FIG. 1, a semiconductor substrate 1 and an insulating film 2 are formed in the same manner as in the prior art. In FIG. 2, a photoresist 6 is applied as an etching mask to the insulating film 2 to form an etching mask pattern in the bonding pad region. In FIG. 3, the etching is performed through an etching mask pattern of the photoresist 6 to form irregularities on the surface of the insulating film 2 in the bonding pad region. Further, as shown in FIG. 4, the metal pad electrode 3 is formed such that the irregularities on the surface of the insulating film 2 are reflected on the surface of the metal pad electrode 3. After that, as shown in FIG. 5, the protective film 4 is formed by the same method as the conventional technique, and the wire 5 is connected to the metal pad electrode 4 as shown in FIG.

【００１０】次に、本発明の半導体装置の製造方法にお
ける第２の実施の形態について、図７〜１３に示す工程
断面図を参照しながら説明する。Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to sectional views shown in FIGS.

【００１１】図７は、半導体基板１、絶縁膜２が従来の
技術と同様の方法で形成される。図８において、絶縁膜
２上に薄膜としてポリシリコン７を形成する。図９にお
いてポリシリコン上にエッチングマスクとしてフォトレ
ジスト６を塗布し、ボンディングパッド領域内にエッチ
ングマスクパターンを形成する。図１０において前記フ
ォトレジスト６によるエッチングマスクパターンを介し
てポリシリコン７をエッチングすることで前記ボンディ
ングパッド領域内の絶縁膜２表面に凸型のポリシリコン
７を形成する。さらに、図１１に示すように金属パッド
電極３を絶縁膜２の表面の凹凸形状が金属パッド電極３
表面に反映されるように形成する。その後、図１２に示
すように従来の技術と同様の方法で、保護膜４を形成
し、図１３に示すようにワイヤ５を金属パッド電極３に
接続を行う。In FIG. 7, a semiconductor substrate 1 and an insulating film 2 are formed by the same method as in the prior art. In FIG. 8, polysilicon 7 is formed as a thin film on insulating film 2. In FIG. 9, a photoresist 6 is applied as an etching mask on polysilicon, and an etching mask pattern is formed in a bonding pad region. In FIG. 10, the polysilicon 7 is etched on the surface of the insulating film 2 in the bonding pad region by etching the polysilicon 7 through the etching mask pattern of the photoresist 6. Further, as shown in FIG. 11, the metal pad electrode 3 is
Formed to be reflected on the surface. Thereafter, as shown in FIG. 12, a protective film 4 is formed by the same method as the conventional technique, and the wires 5 are connected to the metal pad electrodes 3 as shown in FIG.

【００１２】なお、第１の実施の形態及び第２の実施の
形態においてエッチングマスクとしてフォトレジストを
用いたが、特に限定されるものではなく、絶縁膜のエッ
チングを防ぐことができる材料であれば同様の効果が得
られる。また、第２の実施の形態において薄膜７はポリ
シリコンを用いたが薄膜が形成できて、エッチングの容
易な材料であれば、特に限定されるものではなく、同様
の効果が得られる。その他、特に限定されるものではな
いが、半導体基板１としては、シリコン基板などが、絶
縁膜２としては、酸化シリコン膜などが、金属パッド電
極３としては、アルミニウム合金などが、保護膜４とし
ては、窒化シリコン膜などが挙げられる。In the first and second embodiments, a photoresist is used as an etching mask. However, the present invention is not limited to this. Any material that can prevent etching of an insulating film is used. Similar effects can be obtained. In the second embodiment, the thin film 7 is made of polysilicon, but is not particularly limited as long as the thin film can be formed and is easily etched, and the same effect can be obtained. In addition, although not particularly limited, the semiconductor substrate 1 is a silicon substrate or the like, the insulating film 2 is a silicon oxide film or the like, the metal pad electrode 3 is an aluminum alloy or the like, and the protective film 4 is Is a silicon nitride film or the like.

【００１３】[0013]

【発明の効果】以上のように、本発明は、絶縁膜形成
後、ボンディングパッド領域内の絶縁膜と金属パッド電
極表面に凹凸を形成することにより絶縁膜と金属パッド
電極及び、金属パッド電極とワイヤとの接触面積を広げ
ることで絶縁膜と金属パッド電極及び、金属パッド電極
とワイヤとの接着性を向上することができる。そのた
め、ワイヤボンディング時あるいはワイヤボンディング
後に、ワイヤの張力により絶縁膜と金属パッド電極また
は、金属パッド電極とワイヤとの界面での剥がれの防止
効果を発揮できるすぐれた半導体装置の製造方法を提供
できる。As described above, according to the present invention, after the formation of the insulating film, the surface of the insulating film and the metal pad electrode in the bonding pad region are formed with irregularities to thereby form the insulating film, the metal pad electrode, and the metal pad electrode. By increasing the contact area with the wire, the adhesion between the insulating film and the metal pad electrode and between the metal pad electrode and the wire can be improved. Therefore, it is possible to provide an excellent method of manufacturing a semiconductor device capable of exhibiting an effect of preventing peeling at the interface between the insulating film and the metal pad electrode or the interface between the metal pad electrode and the wire due to the tension of the wire during or after wire bonding.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態における半導体装置
の製造方法の一工程断面図。FIG. 1 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第１の実施の形態における半導体装置
の製造方法の一工程断面図。FIG. 2 is a process cross-sectional view of the semiconductor device manufacturing method according to the first embodiment of the present invention;

【図３】本発明の第１の実施の形態における半導体装置
の製造方法の一工程断面図。FIG. 3 is a sectional view of one step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

【図４】本発明の第１の実施の形態における半導体装置
の製造方法の一工程断面図。FIG. 4 is a sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

【図５】本発明の第１の実施の形態における半導体装置
の製造方法の一工程断面図。FIG. 5 is a sectional view of one step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

【図６】本発明の第１の実施の形態における半導体装置
の製造方法の一工程断面図。FIG. 6 is a process cross-sectional view of the manufacturing method of the semiconductor device according to the first embodiment of the present invention;

【図７】本発明の第２の実施の形態における半導体装置
の製造方法の一工程断面図。FIG. 7 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

【図８】本発明の第２の実施の形態における半導体装置
の製造方法の一工程断面図。FIG. 8 is a sectional view of one step of a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

【図９】本発明の第２の実施の形態における半導体装置
の製造方法の一工程断面図。FIG. 9 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

【図１０】本発明の第２の実施の形態における半導体装
置の製造方法の一工程断面図。FIG. 10 is a process cross-sectional view of the semiconductor device manufacturing method according to the second embodiment of the present invention;

【図１１】本発明の第２の実施の形態における半導体装
置の製造方法の一工程断面図。FIG. 11 is a process cross-sectional view of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

【図１２】本発明の第２の実施の形態における半導体装
置の製造方法の一工程断面図。FIG. 12 is a process cross-sectional view of the semiconductor device manufacturing method according to the second embodiment of the present invention;

【図１３】本発明の第２の実施の形態における半導体装
置の製造方法の一工程断面図。FIG. 13 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

【図１４】従来の半導体装置の製造方法の一工程断面図FIG. 14 is a cross-sectional view of one step of a conventional method for manufacturing a semiconductor device.

【図１５】従来の半導体装置の製造方法の一工程断面図FIG. 15 is a cross-sectional view of one step of a conventional method for manufacturing a semiconductor device.

【図１６】従来の半導体装置の製造方法の一工程断面図FIG. 16 is a cross-sectional view of one step of a conventional method for manufacturing a semiconductor device.

【図１７】従来の半導体装置の製造方法の一工程断面図FIG. 17 is a sectional view of one step of a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

１ 半導体基板 ２ 絶縁膜 ３ 金属パッド電極 ４ 保護膜 ５ ワイヤ ６ フォトレジスト ７ ポリシリコン Reference Signs List 1 semiconductor substrate 2 insulating film 3 metal pad electrode 4 protective film 5 wire 6 photoresist 7 polysilicon

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上に絶縁膜を形成した後、ボ
ンディングパッド領域内の絶縁膜表面に凹凸を形成する
ためのエッチングマスクを形成する工程と、エッチング
マスクを介してボンディングパッド領域内の絶縁膜をエ
ッチングして凹凸を形成する工程と、ボンディングパッ
ド領域内に絶縁膜の凹凸形状により表面が凹凸形状とな
る金属パッド電極パターンを形成する工程とを有する半
導体装置の製造方法。A step of forming an etching mask for forming irregularities on the surface of the insulating film in the bonding pad region after forming the insulating film on the semiconductor substrate; and forming an insulating film in the bonding pad region through the etching mask. A method for manufacturing a semiconductor device, comprising: a step of etching a film to form irregularities; and a step of forming a metal pad electrode pattern in which a surface becomes irregular due to the irregularities of an insulating film in a bonding pad region. 【請求項２】 半導体基板上に絶縁膜を形成した後、絶
縁膜上に薄膜を形成する工程と、ボンディングパッド領
域内に凹凸を有するように薄膜の一部を残したエッチン
グマスクを形成する工程と、エッチングマスクを介して
ボンディングパッド領域内の薄膜をエッチングをし絶縁
膜表面に凹凸を形成する工程と、ボンディングパッド領
域内に絶縁膜と薄膜とからなる凹凸形状により表面が凹
凸形状となる金属パッド電極パターンを形成する工程と
を有する半導体装置の製造方法。2. A step of forming a thin film on the insulating film after forming an insulating film on the semiconductor substrate, and a step of forming an etching mask leaving a part of the thin film so as to have irregularities in a bonding pad region. And a step of etching the thin film in the bonding pad region through an etching mask to form irregularities on the surface of the insulating film, and forming a metal having an irregular surface on the surface of the bonding pad region due to the irregularities formed by the insulating film and the thin film. Forming a pad electrode pattern.
JP9283786A 1997-10-16 1997-10-16 Manufacture of semiconductor device Pending JPH11121457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9283786A JPH11121457A (en) 1997-10-16 1997-10-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9283786A JPH11121457A (en) 1997-10-16 1997-10-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11121457A true JPH11121457A (en) 1999-04-30

Family

ID=17670125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9283786A Pending JPH11121457A (en) 1997-10-16 1997-10-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11121457A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100396787B1 (en) * 2001-11-13 2003-09-02 엘지전자 주식회사 Wire bonding pad structure of semiconductor package pcb
WO2004088736A1 (en) * 2003-04-03 2004-10-14 International Business Machines Corporation Internally reinforced bond pads
JP2005026691A (en) * 2003-07-01 2005-01-27 Stmicroelectronics Inc System and method for increasing strength of bond formed with small-diameter wire in ball bonding
JP2006213027A (en) * 2005-02-07 2006-08-17 Alps Electric Co Ltd Thermal head and its manufacturing method
JP2007227556A (en) * 2006-02-22 2007-09-06 Nec Electronics Corp Semiconductor device
JP2012129299A (en) * 2010-12-14 2012-07-05 Nissan Motor Co Ltd Dissimilar material junction-type diode and method for manufacturing the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100396787B1 (en) * 2001-11-13 2003-09-02 엘지전자 주식회사 Wire bonding pad structure of semiconductor package pcb
WO2004088736A1 (en) * 2003-04-03 2004-10-14 International Business Machines Corporation Internally reinforced bond pads
CN100373569C (en) * 2003-04-03 2008-03-05 国际商业机器公司 Internally reinforced bond pads
JP2005026691A (en) * 2003-07-01 2005-01-27 Stmicroelectronics Inc System and method for increasing strength of bond formed with small-diameter wire in ball bonding
JP2006213027A (en) * 2005-02-07 2006-08-17 Alps Electric Co Ltd Thermal head and its manufacturing method
JP4668637B2 (en) * 2005-02-07 2011-04-13 アルプス電気株式会社 Thermal head and manufacturing method thereof
JP2007227556A (en) * 2006-02-22 2007-09-06 Nec Electronics Corp Semiconductor device
JP2012129299A (en) * 2010-12-14 2012-07-05 Nissan Motor Co Ltd Dissimilar material junction-type diode and method for manufacturing the same

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