JPH04258125A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04258125A JPH04258125A JP3019638A JP1963891A JPH04258125A JP H04258125 A JPH04258125 A JP H04258125A JP 3019638 A JP3019638 A JP 3019638A JP 1963891 A JP1963891 A JP 1963891A JP H04258125 A JPH04258125 A JP H04258125A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- film
- plasma
- oxide film
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000001681 protective effect Effects 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000000992 sputter etching Methods 0.000 abstract description 2
- 238000005121 nitriding Methods 0.000 abstract 3
- 238000009413 insulation Methods 0.000 abstract 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/1191—Forming a passivation layer after forming the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置に関し、特に
ＴＡＢ（ｔａｐｅ ａｕｔｏｍａｔｅｄ ｂｏｎｄ
ｉｎｇ）方式の半導体装置に関する。[Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to TAB (tape automated bond) devices.
ing) type semiconductor device.
【０００２】0002
【従来の技術】半導体装置の高集積化に伴い多ピン化が
進んでおり、最近ではＴＡＢ方式が多く用いられている
。2. Description of the Related Art As semiconductor devices become more highly integrated, the number of pins increases, and recently the TAB method has been widely used.
【０００３】図３は従来の半導体装置の一例を示す半導
体チップの断面図である。FIG. 3 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
【０００４】図３に示すように、シリコン基板１の上に
設けた酸化シリコン膜２の上に設けたアルミニウム配線
３と、アルミニウム配線３の上に設けた５〜２０μｍの
厚さの金属層からなるバンプ４と、バンプ４の側面に密
着して設けたボンディングの際の圧力にもある程度耐え
られるポリイミド系樹脂膜９の保護膜を有して構成され
る。As shown in FIG. 3, aluminum wiring 3 is formed on a silicon oxide film 2 formed on a silicon substrate 1, and a metal layer with a thickness of 5 to 20 μm is formed on the aluminum wiring 3. The protective film 9 is made of a polyimide resin film 9 which is provided in close contact with the side surface of the bump 4 and can withstand pressure to some extent during bonding.
【０００５】[0005]
【発明が解決しようとする課題】この従来の半導体装置
では、組立時にリードをバンプにボンディングする際、
バンプの周囲に保護膜が密着しているため、ボンディン
グ時の外部圧力により、バンプの横拡がりは防げるもの
の、逆にバンプが圧力により十分変形しないためリード
とバンプとの圧着強度が十分に得られなかった。また、
前記リードとバンプとの圧着強度を大きくするため、さ
らに圧力を加えボンディングすると、図４に示すように
リード１０の圧着部付近に生ずるくびれた部分１１に力
が集中し、リード１０が断線するという問題点があった
。[Problems to be Solved by the Invention] In this conventional semiconductor device, when bonding leads to bumps during assembly,
Since the protective film is in close contact with the periphery of the bump, external pressure during bonding can prevent the bump from spreading laterally, but on the other hand, the bump does not deform sufficiently due to pressure, so sufficient pressure bonding strength between the lead and the bump cannot be obtained. There wasn't. Also,
In order to increase the strength of the crimping between the leads and the bumps, if more pressure is applied to bond them, the force will be concentrated on the constricted part 11 of the lead 10 near the crimped part, as shown in FIG. 4, and the lead 10 will break. There was a problem.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に設けた最上層の配線と、前記配線上に設
けたバンプと、前記バンプの側面に間隙を有して設けた
保護膜とを有する。[Means for Solving the Problems] A semiconductor device of the present invention includes:
The semiconductor device includes an uppermost wiring provided on a semiconductor substrate, a bump provided on the wiring, and a protective film provided with a gap on the side surface of the bump.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【０００８】図１（ａ），（ｂ）は本発明の一実施例を
示す半導体チップの平面図及びＡ−Ａ′線断面図、図２
（ａ）〜（ｄ）は本発明の一実施例の製造方法を説明す
るための工程順に示した半導体チップの断面図である。FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view taken along line A-A' of a semiconductor chip showing one embodiment of the present invention, and FIG.
(a) to (d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.
【０００９】まず、図２（ａ）に示すように、シリコン
基板１の上に設けた酸化シリコン膜２の上に最上層のア
ルミニウム配線３を選択的に設け、アルミニウム配線３
の上に厚さ５〜２０μｍの金層を選択的に設けてバンプ
４を形成する。次に、バンプ４を含む表面にプラズマＣ
ＶＤ法により厚さ１〜２μｍの酸化シリコン膜（以下プ
ラズマ酸化膜と記す）５及び窒化シリコン膜（以下プラ
ズマ窒化膜と記す）６を順次堆積して保護膜を形成する
。First, as shown in FIG. 2(a), an uppermost aluminum wiring 3 is selectively provided on a silicon oxide film 2 provided on a silicon substrate 1.
Bumps 4 are formed by selectively providing a gold layer with a thickness of 5 to 20 μm on top of the bumps 4 . Next, plasma C is applied to the surface including the bumps 4.
A protective film is formed by sequentially depositing a silicon oxide film (hereinafter referred to as plasma oxide film) 5 and a silicon nitride film (hereinafter referred to as plasma nitride film) 6 with a thickness of 1 to 2 μm using the VD method.
【００１０】次に、図２（ｂ）に示すように、プラズマ
窒化膜６の上にフォトレジスト膜８を塗布して表面を平
坦化する。Next, as shown in FIG. 2(b), a photoresist film 8 is coated on the plasma nitride film 6 to planarize the surface.
【００１１】次に、図２（ｃ）に示すように、イオンエ
ッチングにより全面をエッチバックしてバンプ４の上面
を露出させる。Next, as shown in FIG. 2C, the entire surface is etched back by ion etching to expose the upper surface of the bump 4.
【００１２】次に、図２（ｃ）に示すように、フォトレ
ジスト膜８を剥離した後、バッファード弗酸等の選択性
のあるエッチング液を用いてプラズマ酸化膜５をエッチ
ングし、バンプ４の周囲のバンプ４とプラズマ窒化膜６
との間に間隙７を設け、図１（ａ），（ｂ）に示す半導
体装置を構成する。Next, as shown in FIG. 2(c), after the photoresist film 8 is peeled off, the plasma oxide film 5 is etched using a selective etching solution such as buffered hydrofluoric acid to form the bumps 4. bumps 4 and plasma nitride film 6 around
A gap 7 is provided between the two, and the semiconductor device shown in FIGS. 1(a) and 1(b) is constructed.
【００１３】なお、プラズマ窒化膜６の代りに回転塗布
法により形成したシリカフィルムを用いても良く、プラ
ズマ窒化膜６よりも膜厚を厚く、且つ表面を平坦に形成
できるため、リードをボンディングする際に印加される
圧力に対する耐性が強化される利点がある。Note that a silica film formed by a spin coating method may be used instead of the plasma nitride film 6, and since it is thicker than the plasma nitride film 6 and can be formed with a flat surface, it is suitable for bonding the leads. This has the advantage of enhanced resistance to the pressure applied during the process.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、バンプの
周囲に設けた絶縁膜との間に間隙を設けることにより、
リードボンディング時の外部圧力によって生じる応力を
吸収してバンプの変形による一定幅以上の横広がりを防
止すると同時に、外部圧力によるバンプの横広がりを利
用してリードの圧着強度をも増大させることができると
いう効果を有する。[Effects of the Invention] As explained above, the present invention provides a gap between the bump and the insulating film provided around the bump.
It absorbs the stress caused by external pressure during lead bonding and prevents the bump from expanding beyond a certain width due to deformation, while at the same time increasing the crimp strength of the lead by utilizing the lateral expansion of the bump due to external pressure. It has this effect.
【００１５】また、リードの圧着部付近のくびれた部分
にも無理な力が集中せず、リードの切断事故も防止でき
るという効果を有する。[0015] Further, there is an effect that unreasonable force is not concentrated on the constricted portion near the crimped portion of the lead, and accidents of cutting the lead can be prevented.
【図１】本発明の一実施例を示す半導体チップの平面図
及びＡ−Ａ′線断面図である。FIG. 1 is a plan view and a cross-sectional view taken along line A-A' of a semiconductor chip showing an embodiment of the present invention.
【図２】本発明の一実施例の製造方法を説明するための
工程順に示した半導体チップの断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.
【図３】従来の半導体装置の一例を示す半導体チップの
断面図である。FIG. 3 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
【図４】従来の半導体装置の実施例を示す半導体チップ
の平面図である。FIG. 4 is a plan view of a semiconductor chip showing an example of a conventional semiconductor device.
１ シリコン基板 ２ 酸化シリコン膜 ３ アルミニウム配線 ４ バンプ ５ プラズマ酸化膜 ６ プラズマ窒化膜 ７ 間隙 ８ フォトレジスト膜 ９ ポリイミド系樹脂膜 １０ リード １１ くびれた部分 1 Silicon substrate 2 Silicon oxide film 3 Aluminum wiring 4 Bump 5 Plasma oxide film 6 Plasma nitride film 7 Gap 8 Photoresist film 9 Polyimide resin film 10 Lead 11 Narrow part
Claims (1)
、前記配線上に設けたバンプと、前記バンプの側面に間
隙を有して設けた保護膜とを有することを特徴とする半
導体装置。1. A semiconductor device comprising: a top layer wiring provided on a semiconductor substrate; a bump provided on the wiring; and a protective film provided with a gap on the side surface of the bump. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3019638A JPH04258125A (en) | 1991-02-13 | 1991-02-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3019638A JPH04258125A (en) | 1991-02-13 | 1991-02-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04258125A true JPH04258125A (en) | 1992-09-14 |
Family
ID=12004764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3019638A Pending JPH04258125A (en) | 1991-02-13 | 1991-02-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04258125A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5956605A (en) * | 1996-09-20 | 1999-09-21 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
| JP2009524932A (en) * | 2006-01-25 | 2009-07-02 | フリースケール セミコンダクター インコーポレイテッド | Semiconductor interconnect having adjacent storage for bonding and method of forming |
| JP2013214558A (en) * | 2012-03-30 | 2013-10-17 | Olympus Corp | Wiring board and manufacturing method of the same, and semiconductor device and manufacturing method of the same |
| WO2017103978A1 (en) * | 2015-12-14 | 2017-06-22 | 三菱電機株式会社 | Semiconductor device and manufacturing method therefor |
| CN112885799A (en) * | 2019-11-29 | 2021-06-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
-
1991
- 1991-02-13 JP JP3019638A patent/JPH04258125A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5956605A (en) * | 1996-09-20 | 1999-09-21 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
| US6528894B1 (en) | 1996-09-20 | 2003-03-04 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
| US6972249B2 (en) | 1996-09-20 | 2005-12-06 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
| JP2009524932A (en) * | 2006-01-25 | 2009-07-02 | フリースケール セミコンダクター インコーポレイテッド | Semiconductor interconnect having adjacent storage for bonding and method of forming |
| JP2013214558A (en) * | 2012-03-30 | 2013-10-17 | Olympus Corp | Wiring board and manufacturing method of the same, and semiconductor device and manufacturing method of the same |
| WO2017103978A1 (en) * | 2015-12-14 | 2017-06-22 | 三菱電機株式会社 | Semiconductor device and manufacturing method therefor |
| JPWO2017103978A1 (en) * | 2015-12-14 | 2018-03-15 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| CN112885799A (en) * | 2019-11-29 | 2021-06-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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