JPS5848445A - Manufacture of film carrier - Google Patents
Manufacture of film carrierInfo
- Publication number
- JPS5848445A JPS5848445A JP56147680A JP14768081A JPS5848445A JP S5848445 A JPS5848445 A JP S5848445A JP 56147680 A JP56147680 A JP 56147680A JP 14768081 A JP14768081 A JP 14768081A JP S5848445 A JPS5848445 A JP S5848445A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film carrier
- film
- gold
- protruded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はフィルムキャリ、アの製造法に関するもので、
特にフィルムキャリアのリード先端に突起電極を形成す
る方法を提供するものである。[Detailed Description of the Invention] The present invention relates to a method for producing a film carrier, a.
In particular, the present invention provides a method for forming protruding electrodes at the leading ends of film carriers.
従来より半導体装置（以下半導体ディバイスとよぶ）、
即ちＩＣ，ＬＳＩ等は金属細線を用いたワイヤポンディ
ングにより収納容器リードに接続されていた。一方、最
近、フィルムキャリアによる接続方式が開発され、電卓
９時計等の小型・薄型機器の実装に非常に多く使用され
ている。第１図（ムＪ 、 （Ｂ）に通常のフィルムキ
ャリア方式（米国特許３，６８９，９９１号明細書）を
示した。第１図（Ａ）のフィルムキャリア１において、
２は半導体ディバイス、３は半導体ディバイス上に形成
された金の突起電極、４は錫メッキの銅リード、５はリ
ードを保持する樹脂フィルムである。Traditionally, semiconductor devices (hereinafter referred to as semiconductor devices)
That is, ICs, LSIs, etc. were connected to storage container leads by wire bonding using thin metal wires. On the other hand, recently, a connection method using a film carrier has been developed and is widely used for mounting small and thin devices such as calculators and watches. Figure 1 (B) shows a typical film carrier system (US Pat. No. 3,689,991). In the film carrier 1 in Figure 1 (A),
2 is a semiconductor device, 3 is a gold protrusion electrode formed on the semiconductor device, 4 is a tin-plated copper lead, and 5 is a resin film that holds the lead.
第１図（Ｂ）はフィルムキャリア１と半導体ディバイス
２とを接続した状態を示す。FIG. 1(B) shows a state in which the film carrier 1 and the semiconductor device 2 are connected.
以上の方式では、半導体デバイス２のアルミ電極上に金
の突起電極３を形成する必要がある。この突起電極３の
形成はウェハのままの状態で行なりｔｚるが、ホトエツ
チング、メタライゼーションに関しある程度の技術力と
大幅な設備を必要とする。In the above method, it is necessary to form the protruding gold electrode 3 on the aluminum electrode of the semiconductor device 2. Although the protruding electrodes 3 are formed on the wafer as it is, it requires a certain degree of technical skill and extensive equipment regarding photoetching and metallization.
３ ′
そこでこのような欠点を解決するため、突起電極付フィ
ルムキャリアが発明されている。第２図（ム）に突起電
極付フィルムキャリアの概略を示したが構造的には第１
図に示すものとはゾ同様である。3' In order to solve these drawbacks, a film carrier with protruding electrodes has been invented. Figure 2 (m) shows an outline of the film carrier with protruding electrodes, but the structure is similar to the first one.
It is similar to what is shown in the figure.
異なる点は第２図（Ａ）に示すように、樹脂フィルム２
１に付着されたリード２１の先端に突起２３が形成さ扛
ていることである。この突起２３の作成法は種々考えら
れているが、現状、実用的な方法として銅のエツチング
又はメッキにより突起を作るものがある。そしてこの突
起上に通常は金メッキがなされる。The difference is that the resin film 2
A protrusion 23 is formed at the tip of the lead 21 attached to the lead 1. Various methods have been considered for creating the protrusion 23, but at present, as a practical method, the protrusion is formed by copper etching or plating. This protrusion is usually plated with gold.
しかしながら、銅の突起電極はアルミ電極（半導体デバ
イス上の電極）に比べ固いため、接合面は第２図（Ｂ）
の如くになる。即ち、半導体デバイス２６上のアルミ電
極２４に金メッキされた銅バンプ（突起）２３の先端が
めり込むが、銅は固いため横方向のつぶれが生じない。However, since copper protruding electrodes are harder than aluminum electrodes (electrodes on semiconductor devices), the bonding surface is as shown in Figure 2 (B).
It will be like this. That is, the tip of the gold-plated copper bump (protrusion) 23 sinks into the aluminum electrode 24 on the semiconductor device 26, but since copper is hard, lateral collapse does not occur.
したがってアルミ電極２４上の酸化膜はそのまま沈み込
むにすぎず、接合はほとんど側面２６でしか生じない。Therefore, the oxide film on the aluminum electrode 24 simply sinks, and bonding occurs almost only on the side surfaces 26.
これは通常、金線を用いたボールボンドでは金ボールが
つぶれる際、横方向への「ひしゃげ」があシその流れに
よってアルミ電極表面の酸化膜が破壊され、良い接合が
できるのと比べると極めて不適合なことである。This is extremely different from the normal ball bonding using gold wire, where when the gold ball collapses, there is a lateral "shake" and the flow destroys the oxide film on the surface of the aluminum electrode, resulting in a good bond. This is inappropriate.
以上のことを考慮して、リード先端につける突起電極と
して次のことが要求される。Considering the above, the following is required for the protruding electrode attached to the tip of the lead.
（１） アルミと同等もしくはそれ以下の硬さの金属
が望ましい。(1) A metal with hardness equal to or less than aluminum is desirable.
（２）半導体デバイス上の電極に接する部分は球状又は
、とがっていることが望ましい。これは接触してから、
接合までの間に突起電極が大きく変形し、それによりア
ルミ電極上の酸化膜が破られる稍為らである。゛
本発明、上記の点を勘案してなされたものであり、あら
かじめ突起電極を別の基板上に形成しておき、その突起
電極とフィルムキャリアのリード先端部を位置合せして
接着させリード側に突起電極を転写する方法に関するも
のであシ、特に突起電極の先端形状を理想的な形にする
方法を提供するものである。(2) It is desirable that the portion of the semiconductor device in contact with the electrode be spherical or pointed. This is after contact
This is because the protruding electrode is greatly deformed before bonding, which may break the oxide film on the aluminum electrode.゛The present invention has been made in consideration of the above points, and the protruding electrodes are formed in advance on another substrate, and the protruding electrodes and the lead tips of the film carrier are aligned and bonded to each other on the lead side. The present invention relates to a method of transferring a protruding electrode to a surface, and particularly provides a method for making the tip of a protruding electrode into an ideal shape.
以下第３図（Ａ）〜（Ｈ）をもとにして本発明の一実施
におけるフィルムキャリアの製造法について説明する。A method for manufacturing a film carrier in one embodiment of the present invention will be described below with reference to FIGS. 3(A) to 3(H).
第３図（ム）に示す３１はシリコン単結晶基板である。31 shown in FIG. 3(m) is a silicon single crystal substrate.
該基板３１の主面に保護膜３２を形成する。この保護膜
３２はシリコンのエツチングに耐えるものならば何でも
良く通常は感光性樹脂を用いる。第３図（Ｂｌの３３は
半導体デバイス電極配置に対応する部分であり、突起電
極を形成する部分で保護膜はない。A protective film 32 is formed on the main surface of the substrate 31. This protective film 32 may be made of any material as long as it is resistant to silicon etching, and photosensitive resin is usually used. FIG. 3 (33 in Bl is a portion corresponding to the semiconductor device electrode arrangement, a portion where a protruding electrode is formed, and there is no protective film.
７次に第３図（Ｃ）に示すように異方性エツチング（例
えばＫＯＨ水溶液によるエツチング）を行うが、基板面
指数によりピラミッド型又は三角離型の穴３４ができる
。7. Next, as shown in FIG. 3(C), anisotropic etching (for example, etching with a KOH aqueous solution) is performed, and a pyramid-shaped or triangular-shaped hole 34 is formed depending on the substrate surface index.
次に第３図（Ｄｌに示す如く表面に金属膜３６等の膜−
を形成する。なお、この膜は金属膜でなく、高濃度の拡
散を行なった層でも良い。次に第３図（ＩＣ）に示す如
く、突起電極に相当する窓あけ３７を有する保護膜３６
を形成する。金属膜３６を一方の電極とし、金メッキす
ると第３図（Ｆｌの３８で示す突起電極ができる。Next, as shown in FIG.
form. Note that this film is not a metal film, but may be a layer in which high concentration diffusion is performed. Next, as shown in FIG. 3 (IC), a protective film 36 having a window 37 corresponding to a protruding electrode is shown.
form. By using the metal film 36 as one electrode and plating it with gold, a protruding electrode shown at 38 in FIG. 3 (Fl) is formed.
６ °−′
次に第３図（Ｇ）に示す如〈従来の錫メツキ銅リードの
フィルムキャリア３９を突起電極３８に位置合せし加熱
・加圧することによシ（金−錫）合金ができ、第３図（
Ｈ）に示す如く、突起電極４ｏは基板をはなれ、フィル
ムキャリア３９のリード側につく。6°-' Next, as shown in FIG. 3(G), a (gold-tin) alloy is formed by aligning the conventional tin-plated copper lead film carrier 39 with the protruding electrode 38 and heating and pressurizing it. , Figure 3 (
As shown in H), the protruding electrode 4o is separated from the substrate and attached to the lead side of the film carrier 39.
第４図（ム） 、 （Ｂｌはこのようにして製造したフ
ィルムキャリアを半導体デバイスにポンディングする状
態を示している。第４図（ム）の如く、半導体デバイス
４２上の電極４３とリード先端４１を位置合せし、加熱
・加圧することにより第４図（Ｂ）に示す如くボンディ
ングされる。Figures 4 (m) and (Bl) show the state in which the film carrier manufactured in this way is bonded to a semiconductor device. As shown in Figure 4 (m), the electrode 43 on the semiconductor device 42 and the lead tip 41, and by applying heat and pressure, bonding is performed as shown in FIG. 4(B).
なお、上記実施例では金の突起電極と錫メツキ銅リード
で説明したが、金メツキ銅リード又はアルミリードでも
良い。Although the above embodiments have been described using gold protruding electrodes and tin-plated copper leads, gold-plated copper leads or aluminum leads may also be used.
以上説明したように本発明のフィルムキャリアの製造法
は、突起電極を別基板で作製して転写するので、フィル
ムキャリアとしての歩留りは非常に良い。さらに、突起
電極先端形状がピラミッド状又は三角錐状になってるた
め、半導体デバイス上のアルミ電極に接続する際に、ア
ルミ電極上の酸化膜が破扛、強固な接続が得られる。さ
らに本発明は基板がくり返し使用できるため、非常に実
用的である等の利点を有し、工業上の利用価値が高い。As explained above, in the method for manufacturing a film carrier of the present invention, the protruding electrodes are produced on a separate substrate and transferred, so the yield as a film carrier is very high. Further, since the tip of the protruding electrode is pyramid-shaped or triangular pyramid-shaped, when connecting to an aluminum electrode on a semiconductor device, the oxide film on the aluminum electrode is destroyed, and a strong connection can be obtained. Furthermore, the present invention has the advantage of being extremely practical since the substrate can be used repeatedly, and has high industrial utility value.
第１図（ム） 、 （Ｂｌは従来のフィルムキャリアに
よってボンディングする工程を示す図、第２図（Ａ）
、 ＦＢ）は従来の突起電極付フィルムキャリアによっ
てボンディングする工程を示す図、第３図（Ａ）〜（Ｈ
ｌは本って得られたフィルムキャリアでボンディングす
る工程を示す図である。
３１・・・・・・基板（シリコン単結晶基板）、３３・
・・・・・凹部（穴）、３６・・・・・・金属膜、３８
・・・・・・突起電極、３９・・・・・・フィルムキャ
リア、４ｏ・・・・・・突起電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
（ｌｒン
第２図
第３図
Ｉ
第３図
〃
第４図
２Figure 1 (M), (Bl is a diagram showing the bonding process using a conventional film carrier, Figure 2 (A)
, FB) are diagrams showing the bonding process using a conventional film carrier with protruding electrodes, and Figures 3(A) to (H
1 is a diagram showing a step of bonding with the obtained film carrier. 31...Substrate (silicon single crystal substrate), 33.
...Concavity (hole), 36...Metal film, 38
...Protruding electrode, 39... Film carrier, 4o... Protruding electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Fig. 2 Fig. 3 Fig. I Fig. 3 Fig. 4 Fig. 2
Claims (2)
、前記凹部内に形成した金属層を介して電極用全域を前
記凹部に充填する工程と、フィルムキャリアのリード先
端部を前記電極用金属に位置合せし、前記リード先端部
と電極用金属とを接合した後、前記電極用金属を前記凹
部より離反せしめる工程とを含むことを特徴とするフィ
ルムキャリアの製造法。(1) A step of forming a recess at a predetermined position on one principal surface of the substrate, a step of filling the entire area for the electrode into the recess via a metal layer formed in the recess, and a step of filling the recess with the lead tip of the film carrier. A method for manufacturing a film carrier, comprising the steps of: aligning with the electrode metal, bonding the lead tip and the electrode metal, and then separating the electrode metal from the recess.
の所定位置に異方性エツチングによシ凹部を形成したこ
とを特徴とする特許請求の範囲第１項記載のフィルムキ
ャリアの製造法。(2) A method for manufacturing a film carrier according to claim 1, wherein the substrate is made of single crystal silicon, and a recess is formed at a predetermined position on the main surface of the substrate by anisotropic etching. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56147680A JPS5848445A (en) | 1981-09-17 | 1981-09-17 | Manufacture of film carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56147680A JPS5848445A (en) | 1981-09-17 | 1981-09-17 | Manufacture of film carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5848445A true JPS5848445A (en) | 1983-03-22 |
| JPS6234142B2 JPS6234142B2 (en) | 1987-07-24 |
Family
ID=15435845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56147680A Granted JPS5848445A (en) | 1981-09-17 | 1981-09-17 | Manufacture of film carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5848445A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5999095U (en) * | 1982-12-23 | 1984-07-04 | 三菱重工業株式会社 | press |
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
| JPH08241914A (en) * | 1996-02-13 | 1996-09-17 | Kyushu Hitachi Maxell Ltd | Electroforming metal body |
| US7197817B2 (en) | 2003-01-17 | 2007-04-03 | Nec Electronics Corporation | Method for forming contact bumps for circuit board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4869471A (en) * | 1971-12-22 | 1973-09-20 | ||
| JPS5469383A (en) * | 1977-11-15 | 1979-06-04 | Toshiba Corp | Production of semiconductor device |
-
1981
- 1981-09-17 JP JP56147680A patent/JPS5848445A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4869471A (en) * | 1971-12-22 | 1973-09-20 | ||
| JPS5469383A (en) * | 1977-11-15 | 1979-06-04 | Toshiba Corp | Production of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5999095U (en) * | 1982-12-23 | 1984-07-04 | 三菱重工業株式会社 | press |
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
| JPH08241914A (en) * | 1996-02-13 | 1996-09-17 | Kyushu Hitachi Maxell Ltd | Electroforming metal body |
| US7197817B2 (en) | 2003-01-17 | 2007-04-03 | Nec Electronics Corporation | Method for forming contact bumps for circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6234142B2 (en) | 1987-07-24 |
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